Transcript Physical_Verification_session_intro_Manoj_Chackox

Physical Signoff with Cadence PVS
Manoj Chacko
Director Product Management
Signoff Summit
November 21, 2003
Cadence Physical Verification System
In-design
Unique
debug
Design
intent
PHYSICAL
VERIFICATION
SYSTEM
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+
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+
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In-Design, and Full Chip Signoff
Increasing Foundry Coverage from 180nm down to 16/14N FF
Comprehensive Integration with Virtuoso, Encounter, & QRC
Advanced Node, DFM, SiP/3D-IC Integrations
100+ companies switched to PVS in past 24 months
Drivers: Alternative to Calibre, in-design signoff, adv. node, mixed signal
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Wide Foundry Coverage
PVS Rule Deck Availability
TSMC
GF
180nm, 130nm, 65nm and 40nm: available; 28nm, 20nm, and 14nm: ongoing.
ST
20nm, B9mw, H9A, B7RF, 28FDSOI, 14FDSOI
IBM
SAMSUNG
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180 , 65, 55, 45, 40, 28nm, 20nm, 16nm decks available
14nm: ongoing
20nm, 28nm and14nm: ongoing
SMIC
40nm, 28nm, 20nm, 14nm: ongoing
UMC
130nm, 110nm, 65nm and 45nm
XFAB
XH018, XH035, XA035: available online; other process nodes: per request
AMS
C35: available online; 2H2013: H35
Huali
55nm: available online
© 2013 Cadence Design Systems, Inc. All rights reserved.
Adopting to PVS as Golden Signoff
65nm - 28nm
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PRESS RELEASE
Source: http://www.cadence.com/cadence/newsroom/press_releases/pages/pr.aspx?xml=053013_pmc
PMC Adopts Cadence Physical Verification System as
Signoff Technology for Large Complex SoC
SAN JOSE, Calif., 30 May 2013
HIGHLIGHTS
• PMC is producing working silicon on 65- and 40-nanometer designs, and is currently
deploying the product for its 28-nanometer designs.
• Technology chosen for turnaround time and ready foundry support
• Physical Verification System signoff decks certified by major foundries
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design
innovation, announced today that PMC® has adopted the Cadence® Physical Verification
System as signoff technology for its global design centers. PMC has used the Physical
Verification System for several successful tapeouts, including PMC’s DIGI 120, described as
the industry’s only single-chip processor supporting 10G, 40G and 100G speeds for OTN
transport, aggregation and switching. The device, with 200+ million gates and 180+ Mbits of
RAM, is the largest production SoC that PMC has delivered.
Presented at CDNLive2013, (www.cadence.com)
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Transitioning to In-Design and Signoff PVS
IBM
SAMSUNG
100+
QUALCOMM
CUSTOMERS GLOBALLY
KLA TENCOR
FUJITSU
NXP
HITACHI
JAPAN DISPLAY
IPVS, PVSCV,
PVS PERC, PVS
SIGNOFF
STMICROELECTRONICS
RENESAS ELECTRONICS
HITTITE MICROWAVE
SHARP
RESEARCH IN MOTION
SEMTECH
TELEDYNE TECHNOLOGIES
PMC SIERRA
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•
HONEYWELL INTERNATIONAL
13
OF
THE
TOP
SEMICONDUCTOR
COMPANIES
Faster Path to Sign-Off with In-Design PVS
Verification Time to
Tapeout
20% on
runtime
80% time spent
debugging
Source: Cadence
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Virtuoso
Custom
IC Platform
Encounter
Digital
Platform
Faster
Turnaround
Time
Efficient
Debugging
In-Design
PVS
In-Design
PVS
Higher
Productivity
PVS Signoff
Tight
Integration
Improved Productivity with PVS Signoff
Live
Demo in
Lobby
Design Platform
GDSII
Layout Seat
In Memory
Dynamic
IPVS
PVS
Verify
Design
Std Interfaces
Standalone
PVS signoff
INEFFICIENT - Traditional (batch) signoff forces long loops
BETTER - PVS interactive (batch) signoff executing off Virtuoso® in-memory data
BEST - Virtuoso IPVS Dynamic In-Design Verification, checks as you edit
Enhances Productivity of Layout Teams
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Coming Up - Customer experience of adopting PVS
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