Transcript Document
Ultrafast 16-channel ADC for
NICA-MPD Forward Detectors
A.V. Shchipunov
Join Institute for Nuclear Research
Dubna, Russia
http://afi.jinr.ru
Motivation
Create a PCB Design for digitizing signals
from NICA-MPD’s Forward Detectors
http://afi.jinr.ru
General view of the MPD
http://afi.jinr.ru
Time Projection Chamber
Outer radius
Inner radius
Drift length
Number of sectors (each side)
Total number of readout chambers
Drift time
http://afi.jinr.ru
~ 110 cm
27 cm
~ 150 cm
12
24 (12 - each side)
~ 25-30 ms
Multiplicity for charged particles
Total pad/channels number
dE/dx resolution
Spatial resolution (sx, sy, sz)
Maximal rate
Two track resolution
~ 500
~ 80000
~ 6%
0.6 x 1.0 x 2.0 mm
~ 6 kHz
~ 1 cm
Time Of Flight
• Radius from the beam line
• Time resolution
• Max momentum of π/K system
separated better than 2,5 σ
http://afi.jinr.ru
1.3 m
100 ps
1,3 GeV/c
16 input channels
high sampling rate — up to 5 GHz — for each channel
VME compatible PCB design
Self-calibration
Contain 72-bit QDR SRAM
Spartan-6 FPGA family
http://afi.jinr.ru
Specifications and readout characteristics
Specifications
Number of channels
16
Effective resolution
11.5 bits
Bandwidth -3dB
950 MHz
Full scale range
±1V on 50 Ω
Sampling speed
1, 1.7, 2, 3.4, 4, 5 GS/s
Sampling ring buffer
1024 samples
FPGA buffer size
4Mb / 256k samples
SRAM buffer size
64Mb / 4M samples
Readout characteristics
http://afi.jinr.ru
Waveform size
256
1024
DRS readout time
7,8 μs
31 μs
Event rate to RAM
124 kHz
31 kHz
FPGA buffer
1024 waveforms
256 waveforms
SRAM buffer
16384 waveforms
4096 waveforms
Functional diagram
16 Input Channels
Preamplifiers
Sampling signals
Trigger
SRAM
buffer
FPGA
VME itnerface
http://afi.jinr.ru
ADCs
Self-calibration
Trigger logic
DRS4 — Functional block diagram
Sampling speed – 0,7 to 5 GSPS
8+1 channels with 1024 storage cells each
Differential inputs with 950 MHz bandwidth
Readout time: 30ns * number of samples
Simultaneous reading and writing
http://afi.jinr.ru
CY7C1515KV18 — 72-Mb QDR® II SRAM 4-Word
Burst Architecture
Separate independent read and write data ports
4-word burst for reducing address bus frequency
DDR interfaces for on both read and write ports
Full data coherency, providing most current data
http://afi.jinr.ru
FPGA Spartan 6 — XC6SLX150T
147.443 logic cells
configurable logic blocks: 23.038 slices, 184.304 flip-flops, 1,355 MAX
distributed RAM
4.824 RAM Blocks
4 memory controller blocks
6 banks
540 user I/O pins
http://afi.jinr.ru
AD9788 — 16-bit 800 MSPS DAC
Adjustable analog output: 8.7mA to 31.7mA, RL = 25Ω to 50Ω
Internal digital upconversion capability
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
http://afi.jinr.ru
ADC16V-DRS
Preamplifiers &
analog switches
Output connectors
16 input channels
2 x DRS4 &
2 x ADCs
SRAM
buffer
TxDAC
FPGA
VME interface
http://afi.jinr.ru
TTC Connector
TxDAC
FPGA
DRS4 & ADC
http://afi.jinr.ru
EtherNET interface
8 input channels
Preamplifiers &
analog switches
ADC8BE-DRS