Transcript Slide 1

STR910F
Series
Technical Overview
Sept 2006
32-bit
ARM9-based
Flash Microcontrollers
What’s In This Presentation?
A technical overview of each major feature and function of
STR91xF MCUs
Please see the STR7/STR9 MCU Product Presentation for
general product and tool information
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
1 x USB FS
Device w/DMA
256KB + 32KB,
512KB + 32KB
Burst Flash
64KB or 96KB
SRAM
2 x I 2C
Other Features:
2 x SPI
DSP Functions
8 Channel
DMA
Intr Control
33 Priority Lvls
ARM Peripheral Bus
1 x Ethernet
MAC w/DMA
ACCEL
96MHz
DTCM
ARM966 CPU
ITCM
ETM
ARM Hi-Speed Bus
JTAG
ARBITER
Click Any Block to See More Info
EMI,
Data x8 or x16
1 x CAN 2.0B
3-Phase
Motor Control
ARM Periph Bus
Bridge
3 x UART / IrDA
Memory Map
Up to 80 I/Os
Low Power Modes
4 x 16-bit Timer
Watchdog
RTC
STR910F – Flash ARM9 MCU
Voltage Inputs:
3.0V I/O, 1.8V Core,
Opt. Battery for
RTC and SRAM
WUU
Clock Control
External Components
PLL
Detailed Block Diagram
Crystal Inputs:
Main &
Optional RTC
Configuration Tool
8 x 10-bit ADC
POR
LVD
BOD
Battery Standby
Technical Overview
Sept 2006, v1.0
Thank You
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
TO I/O MATRIX
STR912F
32 B
OTP
ETM9
32 KB 256 KB or 512 KB
FLASH
MAIN FLASH
VREF
VDDQ
2.7V to 3.6V
I/O SOURCE
VDD
1.8V CORE
SOURCE
VBATT
BATTERY
BACKUP
CRYSTAL
I-TCM
PHY
64 KB or 96 KB SRAM
10/100
ETHERNET
MAC
D-TCM
ARBITER
AMBA
USB FULL
SPEED
DEVICE
DUAL VIC
DMA
6-96 MHz
OUT, PLL
4-25 MHz
SYSCLK
ADC
REFERENCE
MII
JTAG
ARM966E-S RISC
CPU 96 MHz
BURST FLASH
CONTROLLER
CRYSTAL
TO I/O MATRIX
AHB
AHB / APB
BRIDGE 1
AUTOMATIC
SWITCH
CLK & PWR
CNTL
REQUESTS FROM:
USB, SPI, UART,
I2C, TIMERS
WATCHDOG
32 KHz
CLK
AHB / APB
BRIDGE 0
8 CHANNEL DMA
CONTROLLER
SUPERVISOR
TO SRAM
APB1
RTC with
TAMPER
SEPARATE
POWER
DOMAIN
CAN
2.0B
2 X I2C
FROM FROM
ETM9
MII
3X
UART
w/IrDA
2 X SSP
(SPI)
APB0
3ph
INDUCTION
MOTOR
CONTROL
8 x ADC
10-bit
EXT
MEMORY
4x
TIMERS
16-bit
WAKE
UP UNIT
I/O SWITCH MATRIX
80 GPIO
P0
P1
P2
P3
P4
8
8
8
STR910F – Flash
ARM9
MCU
8
CPU SYSTEM
ANALOG
MEMORY
I/O
P5
P6
8
8
8
Technical
Overview
TIMER
P7
8
P8
P9
8 Sept 2006,
8
v1.0
Return to Tech Specs
ARM9E Core Architecture Advantages
Harvard Architecture with 5-Stage Pipeline
Tightly Coupled Memories (TCM)
Buffered Write Backs to Data Memory
Single-Cycle DSP Instructions
The ARM966E-S core was chosen because it
Does not include a costly cache memory (die size)
Has Multi-Master AHB
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
ARM966E Benefits vs. ARM7TDMI
5 stage pipeline reduces
Clocks Per Instruction (CPI)
Harvard Architecture
improves Load/Store
performance
Tightly Coupled
Memories (TCM),
more deterministic
AHB and DTCM Write
Buffers for less stalls
ARMv5TE Architecture
with DSP Instructions
(1-cycle 32x16 MAC,
Saturated Math, and others)
ARM966E
5-STAGEPIPELINE
PIPELINE
F
CPU
CPU
CORE
CORE
AHB/
AHB/
APB
APB
D
F
E
D
F
M
E
D
F
W
M
E
D
F
F
W
M
E
D
D
F
W
M
E
E
D
F
W
M
M
E
D
F
W
CODE
I-TCM
DATA
D-TCM
CODE
MEMORY
WRITE
BUFFER
Harvard Architecture
ARM7TDMI
CPU
CPU
CORE
CORE
BUS/
BUS/
APB
APB
F
D
F
3-STAGEPIPELINE
PIPELINE
E F D E F
D E F D E
F D E F D
D
F
E
E
D
F
CODE & DATA
Von Neumann Architecture
F = Fetch
D = Decode
E = Execute
M = Memory Read
W = Memory Write-Back
STR910F – Flash ARM9 MCU
DATA
MEMORY
Technical Overview
Sept 2006, v1.0
CODE AND
DATA
MEMORY
COMBINED
STR910 Enhancements of ARM966E
ARM966E
5-STAGE PIPELINE
FF
CPU
CPU
CORE
CORE
AHB/
AHB/
APB
APB
D
E
M
W
F
D
E
M
F
D
F
E
D
F
M
E
D
F
W
M
E
D
F
W
M
E
D
F
W
M
E
D
F
W
CODE
DATA
I-TCM
D-TCM
PFQ /
BC
32-bit wide
BURST
CODE
Burst Flash
I/F
MEMORY
(to 544KB)
WRITE
BUFFER
32-bit wide
DATA
SRAM
MEMORY
(to 96KB)
BASIC CORE ARCHITECTURE
Pre-Fetch Queue (PFQ) and
Cache (BC)
32-bit wide Single-Cycle SRAM
32-bit wide Burst Flash Memory
Burst Memory interface Operates up to
96MHz (10.4 ns) when retrieving
Sequential 1-Word Instructions
STR910F – Flash ARM9 MCU
Branch
PFQ always looks ahead fetching
instructions during idle bus cycles
BC remembers last four jumps,
immediately loading PFQ upon jump
(branch)
Technical Overview
Sept 2006, v1.0
Pre-Fetch Queue and Branch Cache
What
happens
when
instructions
are not
sequential?
Will PFQ
stall?
IRQ
READ READ READ READ
HANDLER
VIC
VIC
VIC
VIC
PREVIOUS
INST INST INST INST
BRANCH 4
4A
4B
4C
4D
ADDR INST INST INST INST
PREVIOUS
COMPARE
BRANCH 3
3A
3B
3C
3D
ADDR INST INST INST INST
PREVIOUS
BRANCH 2
2A
2B
2C
2D
ADDR
PREVIOUS
INST INST INST INST
BRANCH 1
1A
1B
1C
1D
ADDRESS
Branch
Cache
(BC)
LOAD IF BRANCH MATCH
CURRENT
BRANCH
ADDRESS
32 wide
ARM966E
CPU
32 wide
BURST
FLASH
MEMORY
4 Words of Instruction
(programmable depth to 8)
Pre-Fetch Queue (PFQ)
BC holds 4 instructions for each of 4
most recent branches
PFQ stall reduced upon a branch match
BC loads PFQ with all 4 instructions
into PFQ if branch address matches
PFQ will not flush when CPU reads a literal (a
constant in instruction memory)
STR910F – Flash ARM9 MCU
5th BC entry has instructions to read VIC
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
STR910F DSP Capability
STR910F architecture compliments the ARM9E core
Single cycle DSP Instructions (MAC, Saturated Math, CLZ)
Large Flash for Complex Algorithms and Look Up Tables
Large SRAM for Data Capture and run time storage of Coefficients
Harvard Architecture great for DSP functions
Benefits of Harvard Architecture and single-cycle DSP instructions
clearly demonstrated by FFT performance with Code in Flash and
Coefficients in SRAM
1024 Point FFT
STR912 Code in
Radix 4 complex FFT, 16-bit wide data, bit reverse inputs
Flash & Coefficients in SRAM
787 microseconds
STR912 Code in SRAM & Coefficients in SRAM
942 microseconds
STR912 Code in Flash & Coefficients in Flash
1266 microseconds
More FFT measurements (code in Flash, coefficients in SRAM):
64-pt FFT in 32 usec, 128-pt FFT in 160 usec
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
DSP Benchmark Results
6 times
slower
Normalized
Time
Required to
Complete
1024 point
FFT
3.15 times
slower
1.0
(Normalized,
787 usec)
STR91XF, 96MHz.
Code in Flash,
Coefficients in SRAM
(Harvard Architecture)
STR910F – Flash ARM9 MCU
Competitor
2
Competitor
1
ARM7, 60MHz.
Code in Flash,
Coefficients in
Flash or SRAM
Technical Overview
ARM7, 48MHz.
Code in Flash,
Coefficients in
Flash or SRAM
Sept 2006, v1.0
Return to Tech Specs
Why is DMA Important?
Direct Memory Access (DMA) offloads the CPU
STR910F has 17 peripherals
What if they all need to transfer data at same time?
CPU would be over-loaded
Real-time performance would end
Independent control
CPU sets up DMA channels for peripheral only once
DMA channels automatically manage source and destination of
data
DMA channels competes with the CPU for access to the SRAM
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
ARM7 Without DMA
Peripheral Data Transfers Directly Impact Performance
Instruction fetch
INSTRUCTIONS
& DATA
Store register
FLASH (Code)
Memory
Controller
PERIPHERALS
SRAM (Data)
ARM7TDMI
CORE
AHB
Load register
All data transfers under software control
ARM is load/store architecture requiring data to be read from peripheral into internal register
before being written from internal register to SRAM
ARM7 core has to wait for peripheral read to complete – stalling ARM7 core for slow peripherals
ARM7 Core not available for other operations while transferring data
Instructions and Data share same bus
CPU stalls during Data read/write
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
ARM7 With DMA
Removes Software Overhead
FLASH
INSTRUCTIONS
& DATA
ARM7TDMI
CORE
Memory
Controller
PERIPHERALS
SRAM
DMA
AHB
DMA
DMA transfer frees CPU for other tasks
Memory Controller becomes the bottleneck
Instruction Fetch, Data Read/Write and DMA all trying share same pipeline
through the Memory Controller
DMA transfer will stall CPU
CPU Instruction fetch or Data Read/Write will stall DMA
CPU cannot fetch instructions and read/write data in same cycle
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
STR910
Efficient DMA and Rapid Data Flow
ITCM
DTCM
INSTRUCTIONS
DATA
1 DMA
8 DMA
PFQ/BC BURST FLASH
ARBITER
SRAM
ARM966
CORE
AHB
ENET
USB
UART
SPI
I2C
TIMERS
DMA
Simultaneous ARM9 Core Execution and DMA Transfer
ARM9 Core Executing From Flash through ITCM
Data transfers to/from SRAM
Arbiter shares SRAM access between ARM9 Core and DMA/AHB
Special design guarantees access to each requestor on every other cycle
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
DMA Data Specifics
The AHB bus is “freed up” from normal Data/Instruction
access via the ARM 966 TCM’s
Provides increased AHB bandwidth for DMA units
STR910 has Two DMA Units on the AHB bus
A dedicated DMA unit for Ethernet MAC
Second General Purpose DMA unit
8 programmable channels
Peripherals served (USB, SPI, I2C, UART, Timers, EMI and
external request pins)
Single word and burst transfers
Memory-to-peripherals and memory-to-memory transfers
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
STR910 Dual DMA Controllers
Each DMA Controller is AHB Bus Master taking full
advantage of ARM966 Harvard Architecture for simultaneous
CPU execution and DMA transfer
ARM966 core executing code from flash through i-TCM
DMA AHB Bus master transferring data into or out of SRAM
Dedicated Ethernet DMA Controller
Second General Purpose DMA unit
8 programmable channels
Peripherals served (USB, SPI, I2C, UART, Timers, EMI and
external request pins)
Single word and burst transfers
Memory-to-peripherals, memory-to-memory and peripheral-toperipheral transfers
Scatter or gather DMA using linked lists
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
GP DMAC Scatter Gather DMA
0x00200
Memory
0x00E00
Peripheral
0x0A00
0x0B00
0x0C000
0x0D000
0x0E00
0x0F00
0x1000
0x11000
0
A series of Linked Lists define source and destination
Each linked list defines
Source Address
Destination Address
Transfer Width
Source/Destination burst size
Next Linked List Address
First linked list (source address 0x0A200, destination peripheral, transfer width,
transfer size 3072 bytes [0x0C00], burst size, next linked list address)
Next linked list (source address 0x0B200, destination peripheral, transfer width, transfer
size 3072 bytes [0x0C00], burst size, next linked list address)
And so on…..
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
DMA Acceleration for USB Transfer
USB Transfer Rate
MBits/Second
Without DMA
CPU Utilization (%)
With DMA
CPU Utilization (%)
(DMA Interrupt Service Time Only)
7.4
67
9.1
6.6
53
8.1
5.5
46
4.7
36
4.3
32
5.3
3.7
25
4.6
3.0
21
3.7
2.1
13
2.6
1.6
10
2.0
STR910F – Flash ARM9 MCU
CPU
OVER
LOAD
!!!!
Technical Overview
6.8
5.8
Sept 2006, v1.0
DMA Speeds Ethernet Transfers
Ethernet Transfer Rate*
(MBits/sec)
STR910F CPU
Utilization (%)
STR910F CPU Available for
Application (%)
94
20
80
91
10
90
87
6
94
68
4
96
59
2
98
33
1
99
* Equivalent Raw Ethernet data frames transferred between Ethernet MAC and SRAM
DMA Controller manages data transfer with little CPU intervention
Programmable TX and RX FIFO threshold – automatically triggers AHB transfers
DMA supports fixed address, auto-incrementing and circular buffers in CPU memory
Support for chained descriptors – once DMA transfer completes it can either interrupt
CPU or fetch new DMA descriptor
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
Very Large SRAM
96KB is largest in class today (Flash ARM MCUs)
Why is large SRAM important?
Combination of RTOS, TCP/IP stack, USB stack, DSP functions,
complex application consume SRAM very quickly
Large SRAM needed to cover this, plus communication packet
buffers
Larger packets transferred on serial comm lines mean less
overhead
Less overhead means higher transmission throughput
CPU core can execute code from SRAM if desired
SRAM contents can be automatically backed up by a voltage
on VBATT pin if desired (only 0.5 uA at 25oC)
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
Very Large Flash Memories
Up to 588 KB of dual-bank burst Flash memory
100K erase cycles, 20 year data retention
Large size supports needs:
RTOS + application
TCP/IP code, embedded HTML page(s)
Multinational products, multi-application products
Self-diagnostic code or Data recording
Dual bank architecture
True read-while-write capability, good for safe In-Application-Programming and
EEPROM emulation
Write by single-word, erase by sector
8usec/word write time, 8 sec erase for 512KB bank , 4 sec erase for 256KB bank,
700 usec erase for 32KB bank
Smaller secondary Flash has four 8KB sectors
Larger primary Flash has either four or eight 64KB sectors
Can boot from either Flash memory, programmable option
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
STR910 Memory Map
0xFFFF.FFFF
Single Linear Address Range
4 Gigabyte range
Harvard busses transparent to firmware
Code and data separated in silicon
High Speed Peripherals on AHB
VICs
AHB NONBUFFERED
WRITES
Lower Speed Peripherals on APB
Firmware accesses APB through a bridge,
or window, on the AHB
APB BRIDGE
NON-BUFFERED
WRITES
Separate Ranges for Write Buffer
APB
Peripherals have two address ranges
One for buffered writes and another for
non-buffered writes
Buffered writes increase overall
performance
Non-buffered writes guarantee data
coherency
Dual Flash Bank Memories
MCU can write/erase one while reading
other
Either Flash can reside at boot location
(address 0x00000000)
Bank order is user defined
STR910F – Flash ARM9 MCU
PERIPHERALS
APB BRIDGE
AHB
BUFFERED
WRITES
D-TCM
(SRAM)
I-TCM
(Flash)
Technical
Overview
0x0000.0000
BUFFERED WRITES
ORDER OF BANKS IS USER DEFINED
SECONDARY
FLASH BANK
PRIMARY
FLASH BANK
PRIMARY
FLASH BANK
SECONDARY
Sept 2006, v1.0 FLASH BANK
Return to Tech Specs
OTP Specifics
32 bytes of OTP memory
Ideal for storing MAC address, serial numbers, factory
calibration constants, or other permanent data
Programmed once though JTAG interface or by CPU
OTP bytes can be read by either JTAG or the CPU
Once programmed these bytes can never be altered
2 Reserved Bytes for CPU rev ID and MAC Address
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
Low-Power Modes
RUN MODE
1.7 mA/MHz All Periph Clocks ON
CPU ON, PLL ON
1.0 mA/MHz All Periph Clocks OFF
IDLE MODE
CPU OFF, PLL ON
1.1 mA/MHz All Periph Clocks ON
0.45 mA/MHz All Periph Clocks OFF
WAIT FOR INTERRUPT (WFI) MODE
CPU: 32KHz, PLL OFF, Periph Slow, RTC and WUI ON
700
uA
SLEEP MODE
55
uA
CPU, PLL, Peripherals, I/O STATIC. RTC and WUI ON
BATTERY BACKUP MODE
Device Quiescent except for RTC ON
0.3
uA
o
•Typical IDD Values Shown at 25 C with VDD at 1.8V. WUI = Wake Up Unit
• Battery Mode Shown at 25oC, with VDD < VBATT, current Measured at VBATT pin.
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Low-Power Modes
Full performance, individual Periph Clocks can be gated on/off
Clock speed scaled as needed to balance perf. and consumption
Min Interrupt Response Time: 280 nsec (96 MHz, FIQ interrupting NOP stream)
RUN
Specify which Periph Clocks will stop before entering Idle
Exit Idle from: Ext reset, WDG reset, Intr, RTC alarm, Wake-up Unit
Interrupt Response Time: XX nsec
IDLE
CPU running at 32KHz, switch to 96MHz upon Interrupt
Can do very simple tasks between receiving an Interrupt. Low average pwr
Max Interrupt Response Time: 3.6 msec
WFI
All clocks off except for RTC and Wake up Unit
Exit Sleep from: Ext reset, RTC Alarm, Wake-up Event
Max Interrupt Response Time: 3.6 msec
SLEEP
BATT
STR910F – Flash ARM9 MCU
Entire device quiescent except for RTC and 32KHz osc pads
Restart from voltage returning to VDD pins
Min Interrupt Response Time: 13.6 msec (includes POR)
Optionally backup SRAM contents for an additional 5 uA
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
Battery Standby Circuit – RTC/SRAM
Battery standby circuit isolated from other supplies
Can choose to backup both RTC and SRAM, or just RTC
Automatic crossover switch to VBATT pin when main drops
RTC backup draws only:
0.3uA max at room temp of 25C
0.9uA at max temp of 85C
0.0uA while main CPU supply (VDD) is present.
If using SRAM back-up option:
Additional draw on VBATT pin is 5uA at 25C, 85uA at 85C
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
Supervisor Specifics
STR910 System Supervisor monitors system and environmental
inputs
Generates an Interrupt, System Reset or Global Reset depending on
nature of input
Global (Cold) Reset clears all functions of STR910
System (Warm) Reset clears all but Clock Control Unit (CCU) settings
Interrupt
System Reset
Global Reset
VDD Brown Out
VDDQ Brown Out
Watchdog Timer
External RESET_INn
JTAG Debug Command
VDD Drop Out
VDDQ Drop Out
Power Up
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
Typical Surrounding Components
+
LQFP128
• Dual voltage regulator –
3.3 V and 1.8 V
=
1 TO263
3 capacitors
• System Clock Xtal
(4 – 25 MHz)
=
1 low cost Xtal
2 capacitors
• RTC Xtal (32KHz)
=
1 low cost Xtal
2 capacitors
• Ethernet PHY (STE100P)
and cable connection
=
1 64LQFP pkg
(transformer in RJ45)
• Decoupling caps between
all power and ground
=
13 capacitors
• JTAG, resistors
=
7 pull up / pull down
resistors
31 components
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
ADC Specifics
8 Ch/10-bit successive
approximation
Single, scan or continuous modes
Independent Supply and Ref
Voltage
APB
8 Channel
10-bit ADC
External AVREF for better accuracy
on low voltage inputs
LQFP128 and BGA144 pkgs only
Analog watchdog mode with two
thresholds
8 Analog Inputs
Fast conversion time, as low as
0.7uS
AVREF
AVDD
AVSS
AVDD and AVSS are on separate pins on 128 pin
On 80 pin AVDD is shared with AVREF
Low power standby mode
Total Unadjusted Error (TUE)
+/- 2 LSB (4 counts) typical
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
3-Phase MC Specifics
Six PWM Outputs
Three outputs generated by 10-bit PWM counter (phase U, V, W)
Complementary outputs generated for each phase
Classic or zero-centered PWM generation modes
6-bit dead-time generator for each output
8-bit repetition counter
Rotor speed measurement (16-bit resolution)
Schmidt trigger tachometer input
Hardware asynchronous emergency stop
Dedicated CPU interrupt with 8 flags
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
Interrupt Control and Wake-Up
5 intr from wake up unit
One is ‘logical or’ of 32 inputs to wake
up unit
Remaining 4 are groupings of 8 inputs
Interrupt sources for wake up unit are
30 external inputs (from enabled GPIO),
RTC Interrupt and USB resume
interrupt.
Wake-Up from Sleep direct to CPI
30 GPIO
Lines
RTC
Interrupt
Wake-up Unit
USB Resume
Interrupt
5 Wake-up
Interrupts
27 intr from on-chip periphs
Any of the 32 intr sources can be
assigned to Fast Interrupt reQuest
(FIQ)
IRQ is vectored interrupt and is logical
OR of all 32 Interrupts
FIQ
RTC Interrupt
USB Resume Interrupt
Interrupt
Controller
(VIC0 & VIC1)
27 Interrupts from on-chip peripherals
Priority levels can be assigned by MCU
firmware
Wake-up Unit reamins powered on
during sleep mode.
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
IRQ
Fast Interrupt reQuest (FIQ)
Non-vectored interrupt
CPU executes without need to
determine priority or source
FIQ is last vector in vector
table allowing interrupt
handler to run sequentially
from FIQ vector
FIQ has own dedicated banked
registers allowing faster
context switch
Any one of the 32 interrupt
sources can be assigned to
FIQ
FIQ handler
0x1C
FIQ
0x18
IRQ
0x14
(Reserved)
0x010
Data Abort
0x0C
Prefetch Abort
0x08
Software Interupt
0x04
Undefined Instruction
0x00
Reset
Vector Table
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Interrupt Request (IRQ)
0.FFFF.FFFF
Vectored Interrupt
Logical OR of 32
Interrupt Sources
VIC Hardware resolves
priority level
ISR reads VIC
To determine interrupt
source
To read vector address
for jump to service code
STR910 Branch Cache
Minimizes Interrupt
Latency
Eliminates first memory
access required by
traditional ARM
Architectures
VIC 0
0xFFFF.F000
(Reserved)
0xFC01.0000
VIC 1
0xFC00.0000
0x0000.001C
FIQ
0x0000.0018
IRQ
0x0000.0014
(Reserved)
0x0000.0010
Data Abort
0x0000.000C
Prefetch Abort
0x0000.0008
Software Interupt
0x0000.0004
Undefined Instruction
0x0000.0000
Reset
Decicated Branch Cache Entry
For Instruction to Read VIC
Vector Table
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
IRQ Response
ARM MCU with VIC
ARM MCU without VIC
CPU
CPU
CPU
CPU
Jumps to 0x18
jumps to common handler
analyses status
jumps to interrupt handler
0x18
CPU Jumps to 0x18
CPU jumps to interrupt handler
CPU Jumps to 0x18
CPU jumps to interrupt handler
Always in
Branch cache!
0x18
0x18
3 non
sequential
memory
accesses
2 nonsequential
memory
accesses
Common
handler
required to
determine
interrupt
source
No need
for
common
handler
SLOW
STR910F – Flash ARM9 MCU
STR910 with VIC & BC
2 nonsequential
memory
accesses –
but 0x18 is
always in
cache
No need
for
common
handler
FASTER
Technical Overview
Sept 2006, v1.0
FIQ Response
STR910
CPU Jumps to 0x1C
0x1C
1 nonsequential
memory
accesses
FIQ ISR
located at
0x1C
FASTEST
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
Clock Control Unit (CCU)
CCU generates Master System Clock (fMSTR) from one of three sources selected by
firmware
Main External Crystal or Oscillator fOSC (default)
RTC External Crystal or Oscillator fRTC
PLL Output fPLL
CCU generates system clocks from fMSTR:
CPU clock fCPUCLK
AHB high-speed peripheral bus clock fHCLK
AHB peripheral bus clock fPCLK
EMI external bus clock fBCLK
FMI flash memory clock fFMICLK
UART Baud Generators fBAUD
Standard Timerss fTIM01 and fTIM23
USB fUSB
USB Interface Clock fUSB comes from one of three sources
fMSTR at 48MHz
fMSTR at 96MHz with divide-by-two
External 48 MHz on pin P2.7
Ethernet MAC Clock comes from one of two sources
25 MHz from Main Oscillator (fOSC) output from P5.2
External 25MHz connected to external PHY.
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Clock Control Unit
Main
Oscillator
(fOSC)
PLL
Master
Clock Divider 1,2, 4, 8 16,
Clock
Peripheral
Control
APB
(1,2,4,8)
Clock
Peripheral
Control
APB Periph Clock
Clock
Peripheral
Control
CPU & PFQC Clock
1024
RTC (fRTC)
32kHz
Ethernet
PHY
AHB Periph Clock
AHB
(1,2,4)
Clock
Peripheral
Control
1/2
FMI Clock
Baud Rate Clock
1/2
STR910
16-bit
prescaler
Motor
Control
Clock
Clock
Peripheral
Control
16-bit
prescaler
16-bit
prescaler
External
Clock
1/2
Clock
48MHz Peripheral
Clock
Peripheral
Control
EFT1&2
Clock
EFT3&4
Clock
USB
Clock
Control
USB in
48MHz
STR910F – Flash ARM9 MCU
Clock
Peripheral
Control
Technical Overview
Sept 2006, v1.0
CCU Operational Example
STR910
Main Oscillator
(fOSC)
25 MHz external
XSTAL
PLL
Clock Output up
to 96 MHz
RTC (fRTC)
32kHz external
XSTAL
Master Clock FCPUCLK
96MHz
Source fMSTR
USB CLK
48MHz
1/2
RTC CLK
32kHz
Ethernet PHY
25MHz
CPU Runs at 96MHz, USB at 48MHz and Ethernet at
25 MHz. RTC runs at 32kHz and CPU can go into low
power mode by dynamically running from 32kHZ and
shutting off peripheral clocks and PLL as needed
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
PLL Specifics
Input frequency range
4MHz to 25MHz
Fractional output frequencies can be produced
Example: 25MHz in can produce 96MHz out
Fast Lock Time, 300 usec Typical
Low Jitter
2 ns maximum
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
RTC Specifics
Self-isolation Operation
RTC continues operation during power down
or main digital supplies drop out
Automatically switches to alternate voltage
source (e.g.battery) connected to VBATT
pin
Isolated 32KHz osc circuit continues to
operate from external crystal
Max current draw on VBATT pin for RTC is
less than 0.9 uA across all temp range
Real Time Clock
Complete Time of Day Clock
Time is in 24 hour mode
BCD format
Millisecond resolution
9999 year calendar (leap year support)
Programmable Alarm (1 month)
Periodic Interrupt Generation (1 –
512Hz)
Tamper Detection
Clock Calibration Output
Tamper Detect – if tamper event occurs
RTC time recorded in locations which are
backed-up by VBATT voltage
SRAM standby voltage source optionally cut
off to invalidate SRAM contents
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
JTAG Interface – Basic Connections
STR91xx
MAIN FLASH
SECONDARY FLASH
JTAG TAP CONTROLLER #3
TDO
TMS
TCK TRST
TDI
BURST FLASH
MEMORY DIE
JTAG
Instruction
register length
is 8 bits
JTDO
JTRSTn
JTCK
JTMS
JTDI
ARM966ES DIE
JRTCK
TDI
TMS
TCK
TRST
JTAG TAP CONTROLLER #1
BOUNDARY SCAN
STR910F – Flash ARM9 MCU
TDO
TDI
TRST
TCK
TMS
JTAG TAP CONTROLLER #2
TDO
JTAG
Instruction
register length:
5 bits for TAP #1
4 bits for TAP #2
CPU DEBUG
Technical Overview
Sept 2006, v1.0
JTAG Specifics
JTAG Interface
Boundary Scan
5 standard signals (JTDI, JTDO,
JTMS, JTCK, JTAG) complying with
IEEE-1149.1 specification
Additional JRTCK (return TCK)
Not required if ARM core clock is 10
times JTCK
Required to pace JTCK if ARM core
clock less than 10 times JTCK
All pins except JTAG, Oscillator
Inputs and TAMPER_IN
JTAG Debug using ARM
EmbeddedICE-RT logic
Halt or Monitor mode
2 breakpoints/watchpoints, run,
halt, single step
In-System Programming
Program and erase Main and
Second Flash through JTAG
Program OTP
Configure STR91xF selections,
such as LVD threshold, Flash boot
bank, etc.
STR910F – Flash ARM9 MCU
JTAG Security Bit
Technical Overview
When set disables all JTAG
operations except ‘Full Chip Erase’
Device fully usable again after ‘Full
Chip Erase’, but any OTP bytes
that were programmed will remain
unchanged.
Sept 2006, v1.0
Return to Tech Specs
Embedded Trace Module (ETM) Specifics
Embedded ETM9 adds
additional debug capability
Real-time instruction flow
Trace
Trace filtering and triggering
ETM interface can be reused as GPIO once
development is finished
External Trace Port Analyzer
connects to STR91xF
through ETM connector and
to host PC though USB2.0 or
Ethernet
ETM connector includes ETM
and JTAG signals
STR910F – Flash ARM9 MCU
USB
Dedicated 9-pin ETM
interface in conjunction with
JTAG interface
ARM996ES
Core
USB to
ETM Trace
Port
Analyzer
JTAG Debug
TAP
ETM9 Module
Compressed
Trace Stream
ETM Connector
IAR
Signum
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
11 Communication Interfaces
Ethernet MAC with DMA
USB 2.0 Full Speed Device
CAN 2.0B Interface
3 Independent UARTs
2 Independent I2C
2 Independent SSP (SPI, SSI and Microwire)
8/16 External Memory Interface (EMI) Bus
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Ethernet Specifics
IEEE-802.3-2002 compliant
Media Access Controller
Data encapsulation
Frame assembly before
transmission
Frame parsing and error correct
during transmission
MAC access control
Initiation of frame transmission
and recover from transmission
failure
Dedicated 32-bit burst DMA
channel
STR91xF Ethernet MAC
10 and 100 Mbps
Tagged MAC frame support (VLAN)
Half and full duplex
MAC control sulayer support
32-bit CRC generation and removal
Address filtering modes for physical and
multicast adress
32-bit status code for each frame
Internal FIFO to buffer frames
Transmit FIFO 4 (32-bit) words
Receive FIFO 16 (32-bit) words
MII
MII
STE100P
External PHY
Direct SRAM to MAC transfers of
transmit frames
Direct MAC to SRAM transfers of
receive frames
Descriptor chain management
MII = Media Independent Interface
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
DMA Speeds Ethernet Transfers
Ethernet Transfer Rate*
(MBits/sec)
STR910F CPU
Utilization
(%)
STR910F CPU Available for
Application (%)
94
20
80
91
10
90
87
6
94
68
4
96
59
2
98
33
1
99
* Equivalent Raw Ethernet data frames transferred between Ethernet MAC and SRAM
DMA Controller manages data transfer with little CPU intervention
Programmable TX and RX FIFO threshold – automatically triggers AHB transfers
DMA supports fixed address, auto-incrementing and circular buffers in CPU
memory
Support for chained descriptors – once DMA transfer completes it can either
interrupt CPU or fetch new DMA descriptor
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Excellent TCP/IP Throughput
TCP/IP Throughput*
STR910F CPU Utilization
(%)
STR910F CPU Available for
Application (%)
16.1 Mbits/sec
100%
0%
8.5 Mbits/sec
50%
50%
4.1 Mbits/sec
25%
75%
* CPU running at full speed, 96MHz, and using TCP/IP stack from Micrium
TCP/IP protocol requires significant processing power
When providing 8.5 Mbits/sec (OK for streaming video), the STR910 have
50% of it’s CPU bandwith available for other tasks
How does this compare with another embedded processor?
An ARM920T CPU running at 180MHz using the same TCP/IP stack managed 24
Mbits/sec TCP/IP throughput using 100% of CPU bandwidth
STR910F running at 96MHz managed 16.1 Mbits/sec using 100% CPU bandwidth.
By comparison of ratio, this is better than the ARM920T case.
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
USB Specifics
USB Device Interface
Low speed and full speed (12 Mbps)
operation, USB 2.0 compliant
Isochronous, bulk, control and
interrupt endpoints
Configurable up to 10 doublebuffered endpoints
USB suspend resume operation
Built-In PHY for direct connect
Control
Packet Buffer Interface (PBI)
D-
Dual port 2Kbyte SRAM
PBI manages buffers in SRAM
Special double buffer support for
Isochronous and Bulk transfers
USB
Transeiver
D+
Serial Interface
Control
Engine
Packet Buffer
Interface
Dual Port 2k Byte Packet
Buffer SRAM
Up to 20 monodirectional
single buffered or 10 double
buffered bidirectional
endpoints
DMA
Direct PB SRAM to System SRAM of
receive packets
Direct System SRAM to PB SRAM of
transmit packets
Linked list descriptor chain support
STR910F – Flash ARM9 MCU
Technical Overview
DMA
DMA
Control
Sept 2006, v1.0
AHB
DMA Acceleration for USB Transfer
USB Transfer Rate
MBits/Second
Without DMA
CPU Utilization (%)
With DMA
CPU Utilization (%)
(DMA Interrupt Service Time Only)
7.4
67
9.1
6.6
53
8.1
5.5
46
4.7
36
4.3
32
5.3
3.7
25
4.6
3.0
21
3.7
2.1
13
2.6
1.6
10
2.0
STR910F – Flash ARM9 MCU
CPU
OVER
LOAD
!!!!
Technical Overview
6.8
5.8
Sept 2006, v1.0
Return to Tech Specs
CAN 2.0B Interface
Standard Bosch CAN
interface
Message handler takes care
of low level CAN bus activity
Acceptance filtering
Transfer of messages
between CAN bus and
Message SRAM
Handling of transmission
requests
Interrupt handling
CAN2.0B Interface
Bit rates up to 1 Mbps
32 message objects
Each message object has its own
Identifier Mask
Disable Automatic Transmission mode
for time triggered applications
Programmable FIFO mode
Prograamable loopback mode for selftest
CAN_RX
CAN_TX
External CAN
Transeiver
CPU has access to Message
SRAM and Message Handler
through 38 control registers
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
Three UARTS w/DMA
UART0 supports full modem control signals
UART0, UART1, UART2
Similar to industry standard 16C550 UART
Maximum Baud Rate 1.5M bits per second
Separate 16-bit deep FIFO’s for transmit and receive
Programmable FIFO trigger levels
Programmable Baud Rate Generators based on CCU Master Clock or Master Clock
divided by 2
Programmable serial data lengths 5, 6, 7, or 8 bits with start bit and 1 or 2 stop
bits
Programmable selection of even, odd or no-parity bit bit generation and detection
False start bit detection
Line break detection and generation
Support of IrDA SIR ENDENC up to 115.2K bpps
Programmable DMA Channel can be assigned to service UART0 and UART1
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
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Two I2C with DMA
Each interface can be either Master or Slave
Programmable clocks with support for various rates up to
I2C Standard (100KHz) and Fast Rate (400KHz)
Multi-master capability while in slave mode
7-bit or 10-bit addressing
DMA Channel can be assigned to service each I2C Channel
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
Two Synchronous Serial Port (SSP) with
DMA
Each SSP interface supports
SPI and similar synchronous serial interfaces SSI and Microwire
Full duplex, three or four wire synchronous transfers
Master or Slave operation
Programmable clock bit rate up to 24MHz master, 6MHz slave
Separate transmit and receive FIFOs
Programmable data frame size
Programmable clock and phase polarity
Specifically for Microwire
Half-duplex transfers using 8-bit control
Specifically for SSI
Full duplex four wire synchronous transfers
Transmit pin tri-stateable when not transmitting
A DMA channel may be assigned to service each SSP channel
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
EMI Specifics (128 and 144 pin pkgs)
Supports static asynchronous memory cycles
16-bit Multiplexed
16-bit multiplexed data, 8-bit multiplexed data
and 8-bit non-multiplexed data modes
Configurable memory region each with Chip
Select
CS and control
A16-A23
STR910
16-bit
device
AD0-AD15
Programmable wait states per memory region
16-bit multiplexed data mode options
3 configurable memory regions each with up
24-bit address range
4 configurable memory regions each with up to
23-bit address range
8-bit Multiplexed
CS and control
8-bit multiplexed data mode options
Most efficient for 3 configurable memory regions
each with 8-bit address and 8-bit data
Can be configured with external latch for 3
configurable memory regions each with up to
24-bit address range
AD0-AD7
8-bit Non-Multiplexed
CS and control
8-bit non-multiplexed mode
3 configurable memory regions each with up to
16-bit address range
STR910F – Flash ARM9 MCU
Technical Overview
8-bit
device
STR910
STR910
A0-A15
8-bit
device
D0-D7
Sept 2006, v1.0
Burst Mode EMI Specifics (144 pin pkg)
Support for Asynchronous (burst) memories
BGA144 packaged STR91X devices will support:
Direct connection to Pseudo SRAM (PSRAM)
Connection to Burst Flash Memory
More info coming on connection details
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
STR9 Int vs. Ext Memory Performance: Instr
Assumptions:
32-bit Instructions, 1 cycle to execute each instruction
Memory wait states is set at 4 for asynchronous accesses
Code has 80% sequential addresses, 20% non-sequential (branches)
Ratio of performance, Int Code vs. Ext Code
External Memory Type
EMI Bus Freq = CPU Freq
(up to 66 MHz)
EMI Bus Freq = ½ CPU Freq
16-bit, Asynchronous,
Multiplexed
5.3*
9.3
16-bit, Synchronous (burst),
Multiplexed
1.4
2.3
9.3
17.3
2.0
3.5
8-bit Asynchronous,
Multiplexed
Non-
8-bit Synchronous (burst),
Non-Multiplexed
* This means the CPU can execute code 5.3 times faster when stored in internal Flash
memory compared to being stored in external Flash memory
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
STR9 Int vs. Ext Memory Performance: Data
Assumptions:
32-bit Data
Data access is 80% sequential addresses, 20% non-sequential (random)
Ratio of performance, Int Data vs. Ext Data
External Memory Type
EMI Bus Freq = CPU Freq
(up to 66 MHz)
EMI Bus Freq = ½ CPU Freq
16-bit, Asynchronous,
Multiplexed
13.3*
23.3
16-bit, Synchronous (burst),
Multiplexed
3.0
5.3
23.3
43.3
4.5
8.2
8-bit Asynchronous,
Multiplexed
Non-
8-bit Synchronous (burst),
Non-Multiplexed
* This means the CPU can access data 13.3 times faster when stored
in internal SRAM compared to being stored in external SRAM
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Timer Specifics
Four independent timer counters
featuring
16-bit free running timer/counter
Clock source from programmable
16-bit pre-scale of CPU Clk
Optional external clock
Two 16-bit capture registers for
measuring two input signals
Two 16-bit output compare
registers for generation of two
output signals
PWM Output with 16-bit
resolution on both frequency and
width
Pulse generation in response to
external event
Dedicated CPU interrupt with 5
flags
Ext
Clock
Presc
aler
CPU
Clock
16-bit Timer/Counter
CAP/COMP
Control
A
P
B
Interrupt
Input Capture
Register 1
CAPA
Input Capture
Register 2
CAPB
Output Comp
Register 1
Out_comp/
PWMA
Output Comp
Register 1
Out_comp/
PWMB
TIMER0
DMA Channel can assigned to
each of TIM0 and TIM1
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
GPIO
128-pin and 144-pin packages
80 GPIO (10 I/O ports)
80-pin package
40 GPIO (6 I/O ports)
16 GPIO have higher current (4mA source, 8mA sink)
All GPIO default to high impedance input mode, with some GPIO
additionally routed to certain peripheral inputs
CPU firmware initializes GPIO pin functionality through switch matrix
Bit masking available on each port, no Read-Modify-Write needed
12 MHz maximum GPIO pin toggling from firmware, CPU at 96 MHz
All GPIO 5V tolerant
There are no internal pull up or pull down resistors – recommended to
ground all unused GPIO pins
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
Voltage Sources
128 and 144 PIN
DEVICES
OPTIONAL 1.0V to AVDDQ
80 PIN DEVICES
AVREF_AVDD
AVREF
AVDD
OPTIONAL
SOURCE
AVSS
A/D
Converter
A/D
Converter
AVSS_VSS
Q
A
VDDQ
3.0 or
3.3V
VREG
VSSQ
D
I/O RING
and
FLASH
I/O RING
and
FLASH
VBATT
BATTERY or
SUPERCAP
RTC
RTC
SRAM
SRAM
D
3.0 or
3.3V
VREG
VSSQ
D
BATTERY or
SUPERCAP
OPTIONAL
VDD
VDD
VSS
VDDQ
VBATT
OPTIONAL
1.8V
VREG
D
ARM9E
CORE
ARM9E
CORE
STR910F – Flash ARM9 MCU
Technical Overview
1.8V
VREG
VSS
D
Sept 2006, v1.0
Return to Tech Specs
CAPS
- Configuration and Programming Software for PC
Assistance to select
individual pin functions
Configure clock
sources and
frequencies
CAPS generates report
to document your
design
CAPS generates a
header file which
reflects your choices
Header file is
compatible with ST
Firmware Library
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
CAPS Pin Configuration
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0
Return to Tech Specs
Thank You
STR910F – Flash ARM9 MCU
Technical Overview
Sept 2006, v1.0