Transcript Coarse Grain Reconfigurable Architectures

DASS ‘2003
und
SDA ‘2003
Dresden, May 8-9, 2003
Reiner Hartenstein
Kaiserslautern
University of
Technology
Data-Stream-based
Reconfigurable Computing
„new“ terms
Kaiserslautern
University of
Technology
(only the terms are „new“,
however, not their subject)
Software: you all know
Hardware: you all know
Morphware: structurally programmable „hardware“
Configware: sources for programming morphware
Flowware*: similar to software,
but data counter manipulation:
data streams instead
of instruction streams
*) no relations to „dataflow machine“ (dead area)
© 2003, [email protected]
2
clean terminology and
taxonomy needed for
comprehensibility
http://hartenstein.de
Kaiserslautern
University of
Technology
flowware history:
flowware
... which data item
at which time
time
at which port
1980: data streams
(Kung, Leiserson)
time
1995: super systolic
rDPA (Kress)
1996+: SCCC (LANL),
SCORE, ASPRC,
Bee (UCB), ...
x
x
x
DPA
|
|
port #
- - - x x x
time
- - - - x x x
x x x - -
- - - - - x x x
port #
|
|
|
|
|
|
|
|
|
|
|
x
x
x
3
input data streams
|
x x x
x x x -
(tutorials and courses available on all this)
© 2003, [email protected]
x
x
x
x
x
x
defines ....
time
x
x
x
port #
output data streams
|
x
x
x
http://hartenstein.de
Kaiserslautern
University of
Technology
programming: procedural vs. structural
data-stream-based
embedded systems:
domain
procedural
computing in ...
time only*
structural
space and time
hardwired
reconfigurable
currently emerging
program source software*
(hardware +) (hardware +) configware +
software** flowware
flowware
before fabrication at loading time
„instruction“ fetch
at runtime
data „fetch“
at run time
not programmable
fully hardwired:
algorithms fixed
resources fixed
*) only one
**) software „simulates“ flowware
source needed
reconfigurable:
CPU:
algorithms variable
algorithms variable
resources variable
resources fixed
© 2003, [email protected]
4
http://hartenstein.de
Digital System Platforms
clearly distinguished (1)
Kaiserslautern
University of
Technology
program source
running on it
platform
hardware
(not programmable)
fine grain rGA (FPGA)
configware
morphware coarse
rDPU, rDPA
grain
reconfigurable flowware &
data stream
configware
processor
data stream processor (hardwired)
flowware
instruction stream processor
software
© 2003, [email protected]
machine
paradigm
5
none
anti
machine
von
Neumann
machine
http://hartenstein.de
Crusty Computing Sciences
Kaiserslautern
University of
Technology
more and more
efforts yield
only marginal
improvements
areas fade away
dataflow
machines
are dead
shrinking
supercomputing
conferences
98.5% vN-only
this monopoly
is dangerous
© 2003, [email protected]
[David Padua,
John Hennessy]
6
http://hartenstein.de
Dead Supercomputer Society
Kaiserslautern
University of
Technology
•ACRI
•Alliant
•American
Supercomputer
•Ametek
•Applied Dynamics
•Astronautics
•BBN
•CDC
•Convex
•Cray Computer
•Cray Research
•Culler-Harris
•Culler Scientific
•Cydrome
•Dana/Ardent/
Stellar/Stardent
[Gordon Bell, keynote at ISCA 2000]
•DAPP
•Denelcor
•Elexsi
•ETA Systems
•Evans and Sutherland
•Computer
•Floating Point Systems
•Galaxy YH-1
•Goodyear Aerospace MPP
•Gould NPL
•Guiltech
•ICL
•Intel Scientific Computers
•International Parallel
Machines
•Kendall Square Research
•Key Computer Laboratories
© 2003, [email protected]
7
•MasPar
•Meiko
•Multiflow
•Myrias
•Numerix
•Prisma
•Tera
•Thinking Machines
•Saxpy
•Scientific Computer
•Systems (SCS)
•Soviet Supercomputers
•Supertek
•Supercomputer Systems
•Suprenum
•Vitesse Electronics
http://hartenstein.de
Stealthy CS Crisis
Kaiserslautern
University of
Technology
progress in CS stalled by qualification problems
in industry and academia
often hardware people needed to solve CS problems
communication barriers between disciplines
not only in embedded systems: comprehensibility
barrier between procedural and structural mind set
severe software quality problems
exploding design cost and implementation cost
80% of designers hate their tools...
... unusable for SW people
© 2003, [email protected]
8
http://hartenstein.de
Kaiserslautern
University of
Technology
What are the Challenges ? (1)
[ST microelectronics, MorphICs, Dataquest, eASIC]
factor
2
90% by 2010
4y
10y
1
0*) Department of Trade and Industry, London
© 2003, [email protected]
10
12
18
9
months
http://hartenstein.de
Kaiserslautern
University of
Technology
maturity of
a discipline
McKinsey Curve: dynamics of R&D disciplines
new discipline on top of it ....
new CS by innovation
CS discipline gets crusted
saturation: limitations met
consolidation
challenges ....
evangelists ....
innovation
challenges and motivation
evangelists create awareness
year
fundmental issues
© 2003, [email protected]
10
http://hartenstein.de
Kaiserslautern
University of
Technology
History of Computing
but awareness still missing ....
... still ignored by most CS curricula
maturity
it´s already existing ...
1967
1957
1977
1997
classical CS
mainframes
technology
issue and
business model
© 2003, [email protected]
2007
1987
11
new CS
PC
data streams ...
morphware
?
free rider
http://hartenstein.de
here?
Semiconductor Revolutions
Kaiserslautern
University of
Technology
“Mainstream Silicon Application
is switching every 10 Years”
standard
TTL
1967
1957
custom
mainframes
LSI,
MSI
µproc.
memory
1977
2007
1987
ASICs,
accel’s
1997
PC
data streams ...
technology
issue and
morphware
business model
Trittbrettfahrer
http://hartenstein.de
here?
12
?
© 2003, [email protected]
The next EDA Industry Revolution
Kaiserslautern
University of
Technology
time of Makimoto’s 3rd wave
EDA industry paradigm
switching every 7 years
courtesy
[Keutzer / Newton]
1999
1992
[Hartenstein]
(Co-) Compilation
Data-Stream-based DPU arrays
Synthesis: Cadence, Synopsys ...
1985
1978
2006
Schematics entry: Daisy, Mentor, Valid ...
Transistor entry: Applicon, Calma, CV ...
© 2003, [email protected]
13
http://hartenstein.de
it‘s time for a new CS
Kaiserslautern
University of
Technology
CS crisis:
urging us
qualification
opportunities
problems
next EDA wave:
embedded systems:
high level languages
hw/cw/sw co-design
flowware
configware
it‘s time for a new CS ...
.... a dichotomy of 2 machine paradigms
© 2003, [email protected]
14
http://hartenstein.de
Matter & Antimatter
Kaiserslautern
University of
Technology
-
+
The World of Matter
machine paradigm: the
© 2003, [email protected]
The World of Anti Matter
machine paradigm: Anti Atom
Atom
15
+
http://hartenstein.de
Kaiserslautern
University of
Technology
Matter & Antimatter of Informatics :
Anti Machine paradigm
CPU
-
+
nothing central !
DPU
+
© 2003, [email protected]
16
-
http://hartenstein.de
Drafting a Road Map
Kaiserslautern
University of
Technology
The talk gives a draft of a road map toward
a symbiosys of basic computing paradigms
What delays the break-through
of Reconfiguable Computing ?
© 2003, [email protected]
17
http://hartenstein.de
Kaiserslautern
University of
Technology
Legend:
download
von Neumann
instruction
M
stream
instruction machine
stream
I/O
Machine paradigms
(reconf.) data-stream machine
Flowware
(data sequencer)
I/O
DPU
CPU instruction
sequencer
M
Software
© 2003, [email protected]
Configware
18
memory
data address
generator
asM*
data stream
DPU or rDPU
http://hartenstein.de
heavy anti atoms: DPA = DPU array
flowware: data streams
spinning around
Kaiserslautern
University of
Technology
+
DPU
DPU
DPU
+
DPU
DPU
DPU
DPU
DPU
-
+
+
-
-
-
-
19
+
DPU
DPA
-
© 2003, [email protected]
+
+
-
DPA
+
-
+
http://hartenstein.de
Kaiserslautern
University of
Technology
Legend:
Machine paradigms
download
(reconf.) data-stream machine
von Neumann
instruction
M
stream
instruction machine
stream
I/O
Flowware
M
(data sequencer)
I/O
DPU
CPU instruction
sequencer
Software
M M M M
I/O
Configware
M
memory
data address
generator
M M M M
asM*
data stream
DPU or rDPU
M
memory
I/O
(r)DPA
(r)DPU
© 2003, [email protected]
20
http://hartenstein.de
rDPA example
Kaiserslautern
University of
Technology
SNN filter KressArray Mapping Example
rout thru only
array size:
10 x 16
= 160 rDPUs
Legend:
© 2003, [email protected]
rDPU not used
backbus connect
used for
routing only
backbus
connect
21
operator and routing
port location
not
used marker
http://hartenstein.de
Kaiserslautern
University of
Technology
PACT XPP: Reference Module: XPU128 Co-Processor
ALU - PAE
ALU
Ctrl
CFG
XPP128 ALU-Array
PAE
core
•
•
•
•
2 X PACs (Cluster)
128 X ALU-PAEs
32 X 1Kbyte RAM-PAEs
8X I/O Elements
[Jürgen Becker,
Univ. Karlsruhe]
•
•
•
•
Full 32 or 24 Bit Design
2 Configuration Hierarchies
Evaluation Board (2001)
XDS Development Tool with
Simulator
© 2003, [email protected]
• PAE Core is 32- or 24-Bit ALU with
DSP-Instruction Set and Controller
22
• Connecttions: Inputs + Outputs (Channels) + Events
http://hartenstein.de
Throughput vs. Efficiency
Kaiserslautern
University of
Technology
area used by
application
T. Claasen et al.: ISSCC 1999
*) R. Hartenstein: ISIS 1997
MOPS / mW
1000
L
100
L
L
L
S
1
L
S
L
L
resources
needed for
reconfigurability
0.01
0.001
L
1 Bit CLB
0.1
Wiring by abutment:
32 Bit example
S
S
10
L
2
© 2003, [email protected]
1
0.5
0.25
23
0.13 0.1 0,07 µ feature size
http://hartenstein.de
Throughput vs. Flexibilityy
Kaiserslautern
University of
Technology
coarse grain
goes far beyond
bridging the gap
T. Claasen et al.: ISSCC 1999
*) R. Hartenstein: ISIS 1997
MOPS / mW
1000
throughput
100
hardwired
10
1
coarse
grain
FPGAs
0.1
ment:
von
Neumann
0.01
0.001
flexibility
2
1
0.5
© 2003, [email protected]
0.25
0.13 0.1 0,07 µ feature size
24
http://hartenstein.de
Kaiserslautern
University of
Technology
Legend:
Machine paradigms
download
(reconf.) data-stream machine
von Neumann
instruction
M
stream
instruction machine
stream
I/O
Flowware
M
(data sequencer)
I/O
DPU
CPU instruction
sequencer
Software
memory
data address
generator
Configware
asM*
data stream
DPU or rDPU
embedded memory architecture*
M M M M
I/O
M
M M M M
M
memory
I/O
(r)DPA
(r)DPU
© 2003, [email protected]
*) new discipline: came just in time:
25
Herz et al.: Proc IEEE ICECS 2002
http://hartenstein.de
Configware / Flowware Compilation
Kaiserslautern
University of
Technology
M
M
M
M
high level source program
M
M
M
© 2003, [email protected]
M
M
M
r. Data
Path
Array
mapper
M
rDPA
wrapper
intermediate
configware
M
M
M
M
M
data
streams
scheduler
address
generator
26
flowware
data sequencer
http://hartenstein.de
Kaiserslautern
University of
Technology
Synthesizable Memory Communication
An example by
Nageldinger’s
KressArray
Xplorer
Efficient Memory
Communication
should be directly
supported by the
Mapper Tools
Legend:
Optimized
Parallel
memory ports Memory
Controller
sequencers
application
not used
http://kressarray.de
© 2003, [email protected]
27
http://hartenstein.de
Data-Stream-based Soft Machine
Kaiserslautern
University of
Technology
Memory
Compiler
“instructions”
Scheduler
(data memory)
rDPA
memory bank
memory bank
memory bank
...
memory bank
...
memory bank
Sequencers
(data stream
generator)
© 2003, [email protected]
28
http://hartenstein.de
Kaiserslautern
University of
Technology
The Disk Farm? or
a System On a Card?
The 500GB disc card
LOTS of bandwidth
A few disks replaced by
>10s Gbytes RAM
and a processor
[Gordon Bell,
Jim Gray,
ISCA2000]
14"
MicroDrive:
2006: 9 GB, 50 MB/s ?
(1.6X/yr capacity, 1.4X/yr BW)
Integrated IRAM processor
Connected via crossbar switch
growing like Moore’s law
16 Mbytes; ; 1.6 Gflops; 6.4 Gops
10,000+ nodes in one rack!
100/board = 1 TB; 0.16 Tflops
© 2003, [email protected]
29
http://hartenstein.de
Kaiserslautern
University of
Technology
computing paradigms and methodologies
1946: machine paradigm (von Neumann)
1980: data streams (Kung, Leiserson)
1989: anti machine paradigm introduced
1990: anti machine implementation methodology
1990: rDPU (Rabaey)
1994: anti machine high level programming language
1995: super systolic rDPA (Kress)
1996+: SCCC (LANL), SCORE, ASPRC, Bee (UCB), ...
1997: configware / software partitioning compiler (Becker)
2000: generator for rDPA with high memory bandwidth
(tutorials and courses available on all this)
© 2003, [email protected]
30
http://hartenstein.de
Digital System Platforms
clearly distinguished (2)
Kaiserslautern
University of
Technology
program source
running on it
platform
hardware
(not programmable)
fine grain rGA (FPGA)
configware
morphware coarse
rDPU, rDPA
grain
reconfigurable flowware &
data stream
configware
processor
data stream processor (hardwired)
flowware
instruction stream processor
software
© 2003, [email protected]
machine
paradigm
31
none
anti
machine
von
Neumann
machine
http://hartenstein.de
Software Industry
Kaiserslautern
University of
Technology
Software Industry’s
Secret of Success
Procedural
personalization
via RAM-based
Machine Paradigm
standard
µproc.,
memory
TTL
1967
1957
custom
LSI,
MSI
© 2003, [email protected]
2007
1987
1977
32
ASICs,
accel’s
1997
http://hartenstein.de
Configware Industry ?
Kaiserslautern
University of
Technology
Configware
Industry
Repeat Success Story by
new Machine Paradigm !
structural
personalization:
RAM-based
before run time
standard
µproc.,
memory
TTL
1967
1957
custom
LSI,
MSI
© 2003, [email protected]
2007
1987
1977
33
ASICs,
accel’s
1997
http://hartenstein.de
Kaiserslautern
University of
Technology
The Secret of Success:
not a niche market
Co-Compilation
supporting platform-based design
High level PL source
“vN" machine
paradigm
Partitioner
anti machine
paradigm
CW
SW
Analyzer
compiler / Profiler compiler
SW code
© 2003, [email protected]
CW Code
34
could provide
the platforms
supporting
different
platforms
Resource
Parameters
http://hartenstein.de
thank you
Kaiserslautern
University of
Technology
thank you for your patience
© 2003, [email protected]
35
http://hartenstein.de
>>> END
Kaiserslautern
University of
Technology
© 2003, [email protected]
36
http://hartenstein.de
>>> Appendix
Kaiserslautern
University of
Technology
Xputer Lab
University of Kaiserslautern
Appendix
for discussion
© 2003, [email protected]
© 2001, [email protected]
37
http://hartenstein.de
http://KressArray.de
Kaiserslautern
University of
Technology
The Secret of Success:
not a niche market
Co-Compilation
supporting platform-based design
High level PL source
“vN" machine
paradigm
Partitioner
anti machine
paradigm
CW
SW
Analyzer
compiler / Profiler compiler
SW code
© 2003, [email protected]
CW Code
38
should provide
the platforms
supporting
different
platforms
Resource
Parameters
http://hartenstein.de
Machine Paradigms
Kaiserslautern
University of
Technology
machine category
Computer (the Machine:
“v. Neumann”)
driven by:
Instruction streams
data streams (no “dataflow”)
engine principles
instruction sequencing
sequencing data streams
state register
single program counter
(multiple) data counter(s)
at run time
at load time
resource
DPU (e.g. single ALU)
DPU or DPA (DPU array) etc.
operation
sequential
parallel pipe network etc.
Communication path set-up
. fetch” )
( “instruction
data
path
*) e g. Bee project Prof. Broderson
© 2003, [email protected]
The Anti Machine
also hardwired implementations*
39
http://hartenstein.de
Kaiserslautern
University of
Technology
language category
both deterministic
operation
sequence
driven by:
state register
address
computation
Instruction fetch
parallel memory
bank access
© 2003, [email protected]
Programming Language Paradigms
Computer Languages
Languages f. Anti Machine
procedural sequencing: traceable, checkpointable
read next instruction,
read next data item,
goto (instr. addr.),
goto (data addr.),
jump (to instr. addr.),
jump (to data addr.),
instr. loop, loop nesting
data loop, loop nesting,
no parallel loops, escapes,
parallel loops, escapes,
instruction stream branching data stream branching
program counter
data counter(s)
massive memory
overhead avoided
cycle overhead
memory cycle overhead
overhead avoided
interleaving only
no restrictions
40
http://hartenstein.de
Kaiserslautern
University of
Technology
Xputer Lab
Jürgen Becker’s Co-DE-X Co-Compiler
supporting platform-based design
University of Kaiserslautern
X-C
Computer machine
paradigm
X-C is C language
extended by MoPL
Partitioner
Xputer machine
paradigm
X-C
GNU C Analyzer
compiler / Profiler compiler
Host KressArray
Software Configware
© 2003, [email protected]
© 2001, [email protected]
41
DPSS
supporting
different
platforms
Resource
Parameters
http://hartenstein.de
http://www.fpl.uni-kl.de
Kaiserslautern
University of
Technology
KressArray Family generic Fabrics:
a
few
examples
Select mode,
Select
number, width
of NNports
16
Function
Repertory
8
32
+
24
2
rDPU
4
select Nearest Neighbour (NN) Interconnect: an example
routthrough
only
more NNports:
rich Rout Resources
rout-through
and function
Examples of
2nd Level
Interconnect:
layouted over
rDPU cell no separate
routing areas !
http://kressarray.de
© 2003, [email protected]
42
http://hartenstein.de
Kaiserslautern
University of
Technology
Impact of Makimoto’s wave
Software Industry’s
Secret of Success
Personalization
(CAD) before
fabrication
standard
1967
1957
custom
Repeat Success Story by
new Machine Paradigm !
Procedural
personalization
via RAM-based
Machine Paradigm
µproc.,
memory
TTL
LSI,
MSI
© 2003, [email protected]
Configware
Industry
structural
personalization:
RAM-based
before run time
2007
1987
1977
43
ASICs,
accel’s
1997
http://hartenstein.de
Kaiserslautern
University of
Technology
(procedural)
The Dominance of the Submarine Model ...
structurally
disabled
Hardware
... indicates, that our CS education
system produces zillions of
mentally disabled Persons
It‘s time to attack the software
faculty dictatorship. Get involved!
© 2003, [email protected]
… completely disabled to cope with
solutions other than software only
44
http://hartenstein.de
Kaiserslautern
University of
Technology
CS Education
….
…However,
is basedcurrent
on the Submarine
Model
This model disables ...
Algorithm
procedural high level
Programming Language
Brain usage:
procedural-only
Assembly Language
Hardware invisible:
under the surface
Hardware
© 2003, [email protected]
45
http://hartenstein.de
Kaiserslautern
University of
Technology
Hardware and Software as Alternatives
procedural
structural
Algorithm
partitioning
Brain Usage:
both Hemispheres
Hardware,
Configware
Software
Hardw/Configw
Softwareonly
& Hardw/Configw
Software only
© 2003, [email protected]
46
http://hartenstein.de
Why Coarse Grain instead of FPGA ?
Kaiserslautern
University of
Technology
Sources: Proc ISSCC, ICSPAT, DAC, DSPWorld
physical
logical
100 000 000 000
FPGA
physical
Transistors / chip
10 000 000 000
1000 000 000
FPGA
routed
10 000 000
reduced reconfigurability
overhead by up to ~ 1000
1000 000
100 000
drastically
much
fastersmaller
loading
configuration memory
a lot of more benefits
10 000
© 2003, [email protected]
~ 10 000
FPGA
logical
100 000 000
1000
1980
~ 10
1990
2000
47
2010
http://hartenstein.de
Kaiserslautern
University of
Technology
Second Blossom of CS
progress in CS stalled by qualification
problems in industry and academia
Communication barriers between disciplines
Exploding design and implementation cost
Not only in embedded systems: comprehensibility
barrier between procedural and structural mind set
Severe software quality problems
Bad hardware / configware design tools: more than
80% of designers hate their tools
http://hartenstein.de
© 2003, [email protected]
48
Kaiserslautern
University of
Technology
Procedural vs. structural
progress in CS stalled by qualification
problems in industry and academia
like microprocessors also morphware is RAMbased – secret of sucsess of software industry
Could configware industry repeat this success
story ?
Configware will remain a niche market, unless it
Comes along with hardware / configware / software
co-design
© 2003, [email protected]
49
http://hartenstein.de
Kaiserslautern
University of
Technology
Algorithms and Data Structures People
... have to go beyond pointers,
queues, and stacks
#
© 2003, [email protected]
50
http://hartenstein.de
roadmap
Kaiserslautern
University of
Technology
old CS lab course philosophy:
given an application: implement it by a program -/-
new CS freshman lab course environment:
Given an application:
a) implement it by writing a program
b) implement it as a morphware prototype
c) Partition it into P and Q
c.1) implement P by software
c.2) implement Q by morphware
c.3) implement P / Q communication interface
© 2003, [email protected]
51
http://hartenstein.de
Kaiserslautern
University of
Technology
Algorithms and Data Structures
... have to go beyond pointers,
queues, and stacks
Extend by including
algorithmic issues in software /morphware/ hardware
migration
additional levels of parallelism: chaining, pipelining,
systolic, super-systolic, wavefront arrays
additional data structures and storage organization: the
new distributed memory discipline
© 2003, [email protected]
52
http://hartenstein.de
Kaiserslautern
University of
Technology
Computer Organization / Architecture
... have to go beyond von Neumann,
Extend by including
nested machines, address generators
the anti machine paradigm
Extended taxonomy of platforms: procedural, structural,
hardwired, reconfigurable, zhybrid systems
© 2003, [email protected]
53
http://hartenstein.de
Kaiserslautern
University of
Technology
Languages and Compilers
... have to go beyond von Neumann,
Extend by including
Configware / flowware compilers,
Procedural / structural co-compilers
(data-procedural) flowware languages
© 2003, [email protected]
54
http://hartenstein.de
Semiconductor Revolutions
Kaiserslautern
University of
Technology
“Mainstream Silicon Application
is switching every 10 Years”
software people
1957
custom
1967
µproc.,
memory
LSI,
MSI
hardware people
© 2003, [email protected]
1977
1st design crisis
TTL
new breed needed
2007
1987
ASICs,
accel’s
new breed (M&C)
55
1997
2nd design crisis
standard
http://hartenstein.de
Kaiserslautern
University of
Technology
© 2003, [email protected]
EDA the main bottleneck
56
http://hartenstein.de
Kaiserslautern
University of
Technology
guess it !
© 2003, [email protected]
Biggest Mistake of EDA
57
http://hartenstein.de
Kaiserslautern
University of
Technology
[Richard Newton]
Innovation Stalled ?
What is next after VHDL ?
© 2003, [email protected]
58
http://hartenstein.de
Kaiserslautern
University of
Technology
Flowware and Software
Software: instruction-stream-based – i. e.
based on program counter manipulation
Flowware: data-stream-based – i. e.based on data counter
manipulation
Software and lowware: like 2-eiige Zwillinge einführen
© 2003, [email protected]
59
http://hartenstein.de
Models (1)
Kaiserslautern
University of
Technology
1. There is a very wide variety of architectures
2. Most papers have bad organization: to show authors‘
creativeness often less relevant details are stressed
in a confusing mix of abstraction levels
3. Architectures are not described in terms of a
common model
4. a common model is existing – but it‘s usually ignored
5. We need a comprehensible taxonomy of architectures
© 2003, [email protected]
60
http://hartenstein.de
Models (2)
Kaiserslautern
University of
Technology
1. Reconfigurable instructions et extension
2. Reconfigurable co-processor
2a. FPGA
2b. Coarse grain
I omit 3: hardwired accelerators
I do not talk about reconfigurable instruction set processors
M&C structured VLSI design: max no. Of transistors within regular
strcutures – Craig Mudge: regularity factor
- structured Configware Design
© 2003, [email protected]
61
http://hartenstein.de
>> history & terminology
Kaiserslautern
University of
Technology
http://www.uni-kl.de
• history & terminology
• skyrocketing requirements
• destructive von Neumann monopoly
• high mask cost
• low battery capacity
• new compilation model
• conclusions
© 2003, [email protected]
62
http://hartenstein.de
Semiconductor Revolutions
Kaiserslautern
University of
Technology
“Mainstream Silicon Application
is switching every 10 Years”
software people
1957
custom
1967
µproc.,
memory
LSI,
MSI
hardware people
© 2003, [email protected]
1977
1st design crisis
TTL
new breed needed
2007
1987
ASICs,
accel’s
new breed (M&C)
63
1997
2nd design crisis
standard
http://hartenstein.de
Kaiserslautern
University of
Technology
•
•
•
•
•
•
Terminology: DPU versus CPU ...
DPU: data path unit
DPA: DPU array
GA: gate array
rDPU: reconfigurable DPU
rDPA: reconfigurable DPA
rGA: reconfigurable GA
(r)DPA
(r)DPU
• DPU is no CPU:
there is nothing central
CPU
- like in a DPA
© 2003, [email protected]
64
DPU
DPU
instruction
sequencer
http://hartenstein.de
flowware defines ....
Kaiserslautern
University of
Technology
time
x
x
x
DPA
... which data item
at which time
at which port
time
|
|
port #
- - - x x x
time
- - - - x x x
x x x - -
- - - - - x x x
port #
|
|
|
|
|
|
|
|
|
|
|
x
x
x
65
input data streams
|
x x x
x x x -
flowware manipulates the
data counter(s) ...
... software manipulates
the program counter
© 2003, [email protected]
x
x
x
x
x
x
time
x
x
x
port #
output data streams
|
x
x
x
http://hartenstein.de
History of data-streams
Kaiserslautern
University of
Technology
1980: data streams (Kung, Leiserson)
1995: super systolic rDPA (Kress)
1996+: SCCC (LANL), SCORE, ASPRC, Bee (UCB), ...
(tutorials and courses available on all this)
© 2003, [email protected]
66
http://hartenstein.de
>> skyrocketing requirements
Kaiserslautern
University of
Technology
http://www.uni-kl.de
• history & terminology
• skyrocketing requirements
• destructive von Neumann monopoly
• high mask cost
• low battery capacity
• new compilation model
• conclusions
© 2003, [email protected]
67
http://hartenstein.de
Kaiserslautern
University of
Technology
What are the Challenges ? (1)
[ST microelectronics, MorphICs, Dataquest, eASIC]
factor
2
4y
1
0
© 2003, [email protected]
10
12
68
18
months
http://hartenstein.de
Kaiserslautern
University of
Technology
Changing Models of Computing
software
design
Software
(procedural)
hardware/
software
co-design
hardware
Software spec
downloading
I/O
data path
RAM
instruction
sequencer
“von Neumann”
© 2003, [email protected]
downloading
RAM
CAD
hardwired
accelerator(s)
host
hardware
69
the problem
with typical CS
people:
-the dominance
of von Neumann
- they cannot
partition
- they cannot
migrate
hardware
people
needed
http://hartenstein.de
>> destructive von Neumann monopoly
Kaiserslautern
University of
Technology
http://www.uni-kl.de
• history & terminology
• skyrocketing requirements
• destructive von Neumann monopoly
• high mask cost
• low battery capacity
• new compilation model
• conclusions
© 2003, [email protected]
70
http://hartenstein.de
Kaiserslautern
University of
Technology
Which machine paradigm ?
von Neuman does not support morphware
© 2003, [email protected]
71
http://hartenstein.de
What about CS people ?
Kaiserslautern
University of
Technology
CS
people
TTL
1957
1967
µproc.,
memory
LSI,
MSI
© 2003, [email protected]
1987
ASICs,
procedural accel’s
programming
languages,
compiler
computer
architecture
1977
72
FPGAs
1997
2007
soft
CPUs
coarse
grain
http://hartenstein.de
Kaiserslautern
University of
Technology
Flag ship example: annual IEEE ISCA conference series
Statistics [David Padua, John Hennessy, et al.]
the Datenflow
Machine is dead
vN Parallelism:
Resignation?
Interconnect
Fabrics:
taken over by
the opposition:
Reconfigurable
Computing
© 2003, [email protected]
73
http://hartenstein.de
Kaiserslautern
University of
Technology
There are more Levels of Parallelism
Process level
Loop Level (data-stream-based, pipe nets, etc.)
Instruction Level (VLIW etc.)
RT Level (special architectures etc.)
Logic Level (FPGAs)
© 2003, [email protected]
74
http://hartenstein.de
Kaiserslautern
University of
Technology
What are the Challenges ? (2)
[ST microelectronics, MorphICs, Dataquest, eASIC]
factor
2
90% by 2010
4y
10y
1
0*) Department of Trade and Industry, London
© 2003, [email protected]
10
12
75
18
months
http://hartenstein.de
Kaiserslautern
University of
Technology
Changing Models of Computing
software
design
Software
(procedural)
configware
hardware/
/software Software
software
co-design
co-design
Configware
Software
(structural)
downloading
I/O
data path
RAM
instruction
sequencer
“von Neumann”
downloading
RAM
CAD
hardwired
accelerator(s)
host
RAM
host
reconf.
accelerator(s)
RAM
hardware/configware
/software co-design
Hardware
© 2003, [email protected]
downloading
76
Morphware
http://hartenstein.de
no von Neumann bottleneck ?
Kaiserslautern
University of
Technology
typical CS people:
• how to provide more performance to these people ?
• think in terms of machine models:
sequencing instruction by instruction
• cannot be turned into hardware people
• new machine paradigm needed which does not have
a von Neumann bottleneck
• the anti machine has no von Neumann bottleneck
• data streams instead of an instruction stream
• flowware instead of software
© 2003, [email protected]
77
http://hartenstein.de
Just in time
Kaiserslautern
University of
Technology
The new distributed memory discipline:
just in time to implement the anti machine.
[3] M. Herz et al. (invited): Memory Organization for
Data-Stream-based Reconfigurable Computing; Proc. ICECS 2002
© 2003, [email protected]
78
http://hartenstein.de
>> high mask cost
Kaiserslautern
University of
Technology
http://www.uni-kl.de
• history & terminology
• skyrocketing requirements
• destructive von Neumann monopoly
• high mask cost
• low battery capacity
• new compilation model
• conclusions
© 2003, [email protected]
79
http://hartenstein.de
What are the Challenges ? (3)
Kaiserslautern
University of
Technology
[ST microelectronics, MorphICs, Dataquest, eASIC]
factor
2
avoid
applicationspecific
silicon !
3y
4y
10y
30y
1
10
0
*) Department
12
18
months
of Trade and Industry, London
© 2003, [email protected]
80
http://hartenstein.de
Kaiserslautern
University of
Technology
Coarse grain vs. Fine grain
Reconfigurability:
fine grain (FPGAs, rGAs)
coarse grain (PACT AG, Munich)
multi grain (e. g. by slice bundling)
© 2003, [email protected]
81
http://hartenstein.de
>> low battery capacity
Kaiserslautern
University of
Technology
http://www.uni-kl.de
• history & terminology
• skyrocketing requirements
• destructive von Neumann monopoly
• high mask cost
• low battery capacity
• new compilation model
• conclusions
© 2003, [email protected]
82
http://hartenstein.de
What are the Challenges ? (4)
Kaiserslautern
University of
Technology
[ST microelectronics, MorphICs, Dataquest, eASIC]
factor
2
3y
4y
10y
30y
Battery capacity (1.03/year)
1
10
0
*) Department
12
18
months
of Trade and Industry, London
© 2003, [email protected]
83
http://hartenstein.de
Kaiserslautern
University of
Technology
Algorithmic cleverness
Very high throughput on low power slow
FPGAs may be obtained only by algorithmic
cleverness - not yet taught by CS & CSE at
Universities – an urgent educational problem.
© 2003, [email protected]
84
http://hartenstein.de
>> new compilation model
Kaiserslautern
University of
Technology
http://www.uni-kl.de
• history & terminology
• skyrocketing requirements
• destructive von Neumann monopoly
• high mask cost
• low battery capacity
• new compilation model
• conclusions
© 2003, [email protected]
85
http://hartenstein.de
What are the Challenges ? (5)
Kaiserslautern
University of
Technology
[ST microelectronics, MorphICs, Dataquest, eASIC]
factor
new
2
compilation
techniques
needed !
supported
by a new
machine
paradigm
2y
3y
4y
5y
10y
Battery capacity (1.03/year)
1
10
0
*) Department
12
18
30y
months
of Trade and Industry, London
© 2003, [email protected]
86
http://hartenstein.de
>> conclusions
Kaiserslautern
University of
Technology
http://www.uni-kl.de
• history & terminology
• skyrocketing requirements
• destructive von Neumann monopoly
• high mask cost
• low battery capacity
• new compilation model
• conclusions
© 2003, [email protected]
87
http://hartenstein.de
Conclusion
Kaiserslautern
University of
Technology
No, we are not ready for the break-through,
since our computing education is obsolete,
because of the von Neumann monopoly.
But all ingredients are available
to jazz up our CS & CSE curricula
© 2003, [email protected]
88
http://hartenstein.de
>>> thank you
Kaiserslautern
University of
Technology
thank you for your patience
© 2003, [email protected]
89
http://hartenstein.de
scalability
Kaiserslautern
University of
Technology
The Scalability Problem
The Routing congestion Problem
grows with the size of the FPGA
© 2003, [email protected]
90
http://hartenstein.de
Kaiserslautern
University of
Technology
SNN filter KressArray Mapping Example
http://kressarray.de
rout thru only
array size:
10 x 16
= 160 rDPUs
Legend:
© 2003, [email protected]
rDPU not used
backbus connect
used for
routing only
backbus
connect
91
operator and routing
port location
not
used marker
http://hartenstein.de
Kaiserslautern
University of
Technology
Xplorer Plot: SNN Filter Example
[13]
http://kressarray.de
2 hor. NNports, 32 bit
3 vert. NNports, 32 bit
route-thru-only rDPU
© 2003, [email protected]
+
result
operand
92
operator
operand
route thru
backbus connect
http://hartenstein.de
Kaiserslautern
University of
Technology
Conclusion: all knowledge needed is available
• machine paradigm
courses / embedded tutorials:
• languages
full day courses:
• compilation techniques
• anti architectural resources
• sequencing methodology: hw & sw
• hw / sw partitioning methodology
• parallel memory IP core and module generator vendors
• anything else needed
© 2003, [email protected]
93
http://hartenstein.de
... has a chance
Kaiserslautern
University of
Technology
Configware Industry has a Chance
© 2003, [email protected]
94
http://hartenstein.de
Conclusions
Kaiserslautern
University of
Technology
• the anti machine is the way to go for massive parallelism,
also data-intensive applications
• reconfigurable anti machine for high performance
with short product life cycles, unstable standards
• reconfigurable for low cost low volume production
• sparepart problem: needs new infrastructures
• Giga FPGAs highly promising - only by a new design flow:
configware could repeat the success of software industry
© 2003, [email protected]
95
http://hartenstein.de
Paradigm Shifts:
Nick Tredennick‘s view
Kaiserslautern
University of
Technology
why 2 program sources ?
reconfigurable
computing:
instruction-streambased computing:
algorithms variable
algorithms variable
resources fixed
resources variable
programmable
© 2003, [email protected]
96
http://hartenstein.de
Kaiserslautern
University of
Technology
Compilation for (r)DPA of anti machine
high level source program
(software notation)
parameters
wrapper
expression
morphware
tree
DPU library
configware
mapper
code
generators
scheduler
streamware
flowware
© 2003, [email protected]
97
http://hartenstein.de
Misleading predictors
Kaiserslautern
University of
Technology
Moore's Law is becoming a misleading
predictor of future developments.
© 2003, [email protected]
98
http://hartenstein.de
High mask cost
Kaiserslautern
University of
Technology
High mask cost may be avoided
completely by morphware use, or,
partly by GAs (ASICs).
© 2003, [email protected]
99
http://hartenstein.de
Fault tolerance
Kaiserslautern
University of
Technology
Morphware is the only way to
obtain fault-tolerant ICs.
© 2003, [email protected]
100
http://hartenstein.de
World-wide services
Kaiserslautern
University of
Technology
FPGAs may provide an important
benefit for world-wide services and
all other after sales consequences
© 2003, [email protected]
101
http://hartenstein.de
Kaiserslautern
University of
Technology
„Re-configurable Hardware“ ??
Terminology has been highly confusing
„Re-configurable Hardware“ ??
this „Hardware“ is not hard !
it‘s Morphware
We need a concise terminology:
a consensus is on the way
© 2003, [email protected]
102
http://hartenstein.de
Super Pipe Networks
Kaiserslautern
University of
Technology
array
systolic
array
applications
regular data
dependencies
only
supersystolic
rDPA
*
pipeline properties
shape
resources
linear
only
uniform
only
mapping
linear projection or
algebraic synthesis
simulated
annealing or
P&R algorithm
no restrictions
scheduling
(data stream
formation)
(e.g. force-directed)
scheduling
algorithm
*) KressArray [1995]
© 2003, [email protected]
103
http://hartenstein.de
Kaiserslautern
University of
Technology
Synthesizable Memory Communication
An example by
Nageldinger’s
KressArray
Xplorer
Efficient Memory
Communication
should be directly
supported by the
Mapper Tools
Legend:
Optimized
Parallel
memory ports Memory
Controller
sequencers
application
not used
http://kressarray.de
© 2003, [email protected]
104
http://hartenstein.de
Stream-based Soft Machine
Kaiserslautern
University of
Technology
Memory
Compiler
“instructions”
Scheduler
(data memory)
rDPA
memory bank
memory bank
memory bank
...
memory bank
...
memory bank
Sequencers
(data stream
generator)
© 2003, [email protected]
105
http://hartenstein.de
Kaiserslautern
*> Declarations
University of
Technology
4
EastScan is
step by [1,0]
end EastScan;
1
SouthScan is
step by [0,1]
endSouthScan;
JPEG zigzag scan pattern
goto PixMap[1,1]
HalfZigZag;
SouthWestScan
uturn (HalfZigZag)
NorthEastScan is
loop 8 times until [*,1]
step by [1,-1]
2 endloop
x
y
dataHalfZigZag
counter
data counter
data counter
data counter
end NorthEastScan;
SouthWestScan is
loop 8 times until [1,*]
step by [-1,1]
3 endloop
end SouthWestScan;
endloop
end HalfZigZag;
© 2003, [email protected]
106
HalfZigZag
HalfZigZag is
EastScan
loop 3 times
SouthWestScan
SouthScan
NorthEastScan
EastScan
http://hartenstein.de
Kaiserslautern
University of
Technology
Similar Programming Language Paradigms
language category
both deterministic
sequencing
driven by:
© 2003, [email protected]
Computer Languages
Xputer Languages
procedural sequencing: traceable, checkpointable
read next instruction,
read next data object,
goto (instruction addr.),
goto (data addr.),
jump (to instruction addr.),
jump (to data addr.),
instruction loop,
data loop,
instruction loop nesting
data loop nesting,
no parallel loops,
parallel data loops,
instruction loop escapes,
data loop escapes,
instruction stream branching data stream branching
107
http://hartenstein.de
Kaiserslautern
University of
Technology
GAG Scheme
GAG = Generic
Address
Generator
DA
B0
[|
L0
Limit
Stepper
GAG
© 2003, [email protected]
DA
|
L
|
]
limit
B0
Address
Stepper
|
Base
Stepper
A
108
http://hartenstein.de
GAG: Address Stepper
Kaiserslautern
University of
Technology
GAG: Address Stepper
]
[
Base
B0
Limit
GAG =
Generic
Address
Generator
[|
DA
|
|
stepVector
maxStepCount
init
tag
L
B0
|
DA
A
Step
Counter
+/–
=o
Escape
Clause
End
Detect
L
|
|
]
limit
A
Address
© 2003, [email protected]
109
endExec
http://hartenstein.de
Generic Sequence Examples
Kaiserslautern
University of
Technology
L0 DA B0
a)
Limit
Slider
b)
A
c)
d)
Address
Stepper
e)
© 2003, [email protected]
f)
Base
Slider
GAG
g)
110
http://hartenstein.de
Kaiserslautern
University of
Technology
Slider Operation Demo Example
address
floor
F
ceiling
B0
DA
DB
x
© 2003, [email protected]
y
DB
111
L0
C
DL
DL
http://hartenstein.de
What are the Challenges ?
Kaiserslautern
University of
Technology
[ST microelectronics, MorphICs, Dataquest, eASIC]
factor
2
3y
4y
10y
30y
Battery capacity (1.03/year)
1
10
0
*) Department
12
18
months
of Trade and Industry, London
© 2003, [email protected]
112
http://hartenstein.de
What are the Challenges ?
Kaiserslautern
University of
Technology
[ST microelectronics, MorphICs, Dataquest, eASIC]
factor
2
design complexity: +40%/year doub 2y
design productivity: +15%/year doub 5y
SIA roadmap]
3y
4y
10y
30y
Battery capacity (1.03/year)
1
10
0
*) Department
12
18
months
of Trade and Industry, London
© 2003, [email protected]
113
http://hartenstein.de
>> Outline
Kaiserslautern
University of
Technology
• Morphware
• Changing Models by SoC Development
• New Machine Paradigm needed
• The Dichotomy of Paradigms
• Outlook
http://www.uni-kl.de
© 2003, [email protected]
114
http://hartenstein.de
The Morphware Market
Kaiserslautern
University of
Technology
fine-grained:
coarse-grained:
rDPUs: configurable
functional blocks
cLBs, rLBs:
configurable
logic blocks
PACT AG, Munich, Germany
http://pactcorp.com
Lattice
15%
Altera
37%
Actel
6%
Xilinx
42%
total: $3.7 Bio
Top 4 PLD Manufacturers 2000
• [Dataquest] > $7 billion by 2003.
• fastest growing semiconductor
market segment
• PLD vendors’ and their alliances
provide libraries of “soft IPs”
Configware Market
© 2003, [email protected]
115
http://hartenstein.de
Kaiserslautern
University of
Technology
Coarse grain vs. Fine grain
Reconfigurability:
fine grain (FPGAs, rGAs)
coarse grain (PACT AG, Munich)
multi grain (e. g. by slice bundling)
© 2003, [email protected]
116
http://hartenstein.de
Kaiserslautern
University of
Technology
Xplorer Plot: SNN Filter Example
[13]
http://kressarray.de
2 hor. NNports, 32 bit
3 vert. NNports, 32 bit
route-thru-only rDPU
© 2003, [email protected]
+
result
operand
117
operator
operand
route thru
backbus connect
http://hartenstein.de
Kaiserslautern
University of
Technology
Morphware only: some soft CPU core examples
core
architecture
platform
MicroBlaze
125 MHz 70
D-MIPS
32 bit
standard RISC
32 reg. by 32
LUT RAMbased reg.
Xilinx up to
100 on one
FPGA
Nios
16-bit
instr. set
Nios
50 MHz
Nios
core
architecture
platform
Leon
25 Mhz
SPARC
ARM7 clone
ARM
uP1232 8-bit
CISC, 32 reg.
Altera
Mercury
200 XC4000E
CLBs
REGIS
32-bit
instr. set
Altera
22 D-MIPS
8 bits Instr. +
ext. ROM
2 XILINX
3020 LCA
Reliance-1
12 bit DSP
8 bit
Altera –
Mercury
Lattice
4 isp30256,
4 isp1016
1Popcorn-1
8 bit CISC
Altera, Lattice,
Xilinx
gr1040
16-bit
gr1050
32-bit
My80
i8080A
FLEX10K30
or EPF6016
YARD-1A
16-bit RISC,
2 opd. Instr.
old Xilinx FPGA
Board
DSPuva16
16 bit DSP
Spartan-II
xr16
RISC integer C
SpartanXL
© 2003, [email protected]
Acorn-1
118
1 Flex 10K20
http://hartenstein.de
Kaiserslautern
University of
Technology
soft CPUs in academic teaching
• UCSC: 1990!
•
•
•
•
•
•
Märaldalen University
Chalmers University
Cornell University
Gray Research
Georgia Tech
Hiroshima City Univ.
© 2003, [email protected]
•
•
•
•
•
•
•
119
Michigan State
Univ. de Valladolid
Virginia Tech
Washington U. St. Louis
New Mexico Tech
UC Riverside
Tokai University
http://hartenstein.de
>> New Machine Paradigm needed
Kaiserslautern
University of
Technology
• Morphware
• Changing Models by SoC Development
• New Machine Paradigm needed
• The Dichotomy of Paradigms
• Outlook
http://www.uni-kl.de
© 2003, [email protected]
120
http://hartenstein.de
>> The Dichotomy of Paradigms
Kaiserslautern
University of
Technology
• Morphware
• Changing Models by SoC Development
• New Machine Paradigm needed
• The Dichotomy of Paradigms
• Outlook
http://www.uni-kl.de
© 2003, [email protected]
121
http://hartenstein.de
>> Outlook
Kaiserslautern
University of
Technology
• Morphware
• Changing Models by SoC Development
• New Machine Paradigm needed
• The Dichotomy of Paradigms
• Outlook
http://www.uni-kl.de
© 2003, [email protected]
122
http://hartenstein.de
Why fine grain ?
Kaiserslautern
University of
Technology
• no specific silicon: low production volume
(aerospace, automotive, military, industrial
controllers, et al.)
• the spare part problem
• design flow
• coming Giga-FPGA
© 2003, [email protected]
123
http://hartenstein.de
Kaiserslautern
University of
Technology
Configware Industry vs. Software Industry
can configware industry repeat the success story?
• RAM-based
• Compatibility
• Scalability
• Education problems
© 2003, [email protected]
124
http://hartenstein.de
Kaiserslautern
University of
Technology
Problems of Parallelism
enormous speed-ups: factor of 3 to >10 000
Software to FPGA migration:
algorithmic cleverness missing, no education
no methodology for interconnect estimation
Software to rDPA migration
methodology only in special areas (DSP, wireless ....)
... far beyond
the area of parallel algorithms needs
traditional
a complete re-orientation of its scope ... platforms
© 2003, [email protected]
125
http://hartenstein.de
Evolution of FPGA and its design flow
Kaiserslautern
University of
Technology
HLL
[à la S. Guccione]
Compiler
HLL
Compiler
soft
rDPA
rDPA
core
Schematics/
HDL
Netlister
Netlist
Place
and
Route
.
.
FPGA
core
soft
FPGA core
CPU
inter
face
s
CPU Memory
core
core
as soon as Giga
FPGA is available
inter
face
s
CPU Memory
core
core
Bitstream
User
Code
HLL
Compiler Executable
©
© 2003,
2002, [email protected]
[email protected]
126
Compiler
http://hartenstein.de
http://KressArray.de
ASIC emulation
Kaiserslautern
University of
Technology
• ASIC emulation / Rapid Prototyping: to replace simulation
• Quickturn (Cadence), IKOS (Synopsys), Celaro (Mentor)
• hours of compilation run: inefficient since netlist-based: ...
• ... ASIC emulators will become obsolete soon
• by RTR: in-circuit execution debugging instead of emulation
• new business model: upgradable morphware is the product
• emulation for solving the spare part problem in many areas
© 2003, [email protected]
127
http://hartenstein.de
Kaiserslautern
University of
Technology
the wrong
Nasty Matter
machine paradigm
extremely
power hungry
and area
inefficient
CPU
+
Data
Path
instruction
sequencer
© 2003, [email protected]
reconfigurable?
central
von Neumann
bottleneck
RAM
Instruction Fetch Overhead
Address Computation Overhead
128
http://hartenstein.de
Matter vs. Antimatter: CPU vs. DPU
DPU
+
129
stream
data
data streams
instruction
sequencer
© 2003, [email protected]
-
+
Data
Path
+
Kaiserslautern
University of
Technology
DPU
Data
Path
Unit
http://hartenstein.de
Kaiserslautern
University of
Technology
CPU
+
Data
Path
CPU: RAM-based
+ simple machine paradigm
+ scalability
+ relocatability
+ compatibility
= secret of success
of software industry
RAM
instruction
sequencer
© 2003, [email protected]
130
http://hartenstein.de
Kaiserslautern
University of
Technology
• for configware industry is missing:
– FPGA compatibility,
– fully scalable FPGA,
– relocatable configuration code
property
instruction
stream
based
Success Factors
• rDPUs and rDPAs do
much better than FPGAs
data stream based
reconfigurable
fine grain
(FPGA)
coarse
grain
hardwired
RAM-based
yes
yes
yes
(hardwired)
machine paradigm
yes
available**
no
available
available
compatibility
yes
feasible**
limited
feasible
feasible
scalability
yes
good**
no
good*
(hardwired)
code relocatability
yes
good**
no
good*
(hardwired)
success of
software
industry
© 2003, [email protected]
**) mapping coarse
grain onto
FPGA
131
*) if KressArray
used
http://hartenstein.de
Kaiserslautern
University of
Technology
>>> Problems with Concurrency
• The Computer Architecture Crisis
• The Impact of Reconfigurable Platforms
• The Dichotomy of Models
• Parallelism
• Conclusions
http://www.uni-kl.de
© 2003, [email protected]
132
http://hartenstein.de
Parallelism by Concurrency
Kaiserslautern
University of
Technology
+
-
+
-
independent instruction streams
+
+
+
-
+
-
© 2003, [email protected]
+
-
difficult coordination
Data
Path
Data
Path
Data
Path
instruction
sequencer
instruction
sequencer
instruction
sequencer
....
Data
Path
instruction
sequencer
Bus(es) or switch box
massive run time overhead
133
http://hartenstein.de
Kaiserslautern
University of
Technology
>> The Dominance of Embedded Systems
• The Computer Architecture Crisis
• The Impact of Reconfigurable Platforms
• The Dichotomy of Models
• Parallelism
• Conclusions
http://www.uni-kl.de
© 2003, [email protected]
134
http://hartenstein.de
Kaiserslautern
University of
Technology
Summary of the Anti Machine Paradigm
• anti language primitives are
almost the same (slightly extended)
• anti machine execution potential
is dramatically more powerful
• provides drastically more flexibility
• not always replacing von Neumann
© 2003, [email protected]
135
http://hartenstein.de
Kaiserslautern
*> Declarations
University of
Technology
4
EastScan is
step by [1,0]
end EastScan;
2
SouthScan is
step by [0,1]
endSouthScan;
JPEG zigzag scan pattern
goto PixMap[1,1]
HalfZigZag;
SouthWestScan
uturn (HalfZigZag)
NorthEastScan is
loop 8 times until [*,1]
step by [1,-1]
3 endloop
x
y
dataHalfZigZag
counter
data counter
data counter
data counter
end NorthEastScan;
SouthWestScan is
loop 8 times until [1,*]
step by [-1,1]
1 endloop
end SouthWestScan;
endloop
end HalfZigZag;
© 2003, [email protected]
136
HalfZigZag
HalfZigZag is
EastScan
loop 3 times
SouthWestScan
SouthScan
NorthEastScan
EastScan
http://hartenstein.de
Kaiserslautern
University of
Technology
>> Address Generators for Data Streams
(data streams introduced earlier in this session)
• Introduction
• Smart Address Generators
• Address Generators for Data Streams
• Customized Memory Organization
• Conclusions
http://www.uni-kl.de
© 2003, [email protected]
137
http://hartenstein.de
2-D Generic Data Sequence Examples
Kaiserslautern
University of
Technology
a)
b)
c)
d)
© 2003, [email protected]
e)
f)
138
g)
http://hartenstein.de
Kaiserslautern
University of
Technology
GAU generic address unit Scheme
GAG = Generic
Address
Generatorc
DA
B0
[|
L0
Limit
Slider
GAU
© 2003, [email protected]
DA
139
|
|
]
limit
B0
Address
Stepper
A
|
L
Base
Slider
all 3 are copies
of the same BSU
stepper circuit
http://hartenstein.de
GAG: Address Stepper
Kaiserslautern
University of
Technology
GAG: Address Stepper
]
[
Base
B0
Limit
GAG =
Generic
Address
Generator
[|
DA
|
|
stepVector
maxStepCount
init
tag
L
B0
|
DA
A
Step
Counter
+/–
=o
Escape
Clause
End
Detect
L
|
|
]
limit
A
Address
© 2003, [email protected]
140
endExec
http://hartenstein.de
Kaiserslautern
University of
Technology
GAG Slider Model
floor
DA
L0
Limit
Stepper
B0
Address
Stepper
DA
[
B0
Generic
Address
Generator
L0
]
DA
L0
[
© 2003, [email protected]
Base
Stepper
GAG
A
B0
ceiling
sliders
]
141
http://hartenstein.de
GAG Complex Sequencer Implementation
Kaiserslautern
University of
Technology
GAU
GAU
L0 DA B0
Limit
Slider
Address
Stepper
A
VLIW
stack
L0 DA B0
Base
Slider
Limit
Slider
Address
Stepper
GAU
A
L0 DA B0
Limit
Slider
GAG
Address
Stepper
A
GAU
GAG
SDS
Base
Slider
GAU
Generic Address Generator
© 2003, [email protected]
Base
Slider
142
all `been
published
in 1990
http://hartenstein.de
Kaiserslautern
University of
Technology
GAG Slider Operation Demo Example
address
floor
F
ceiling
B0
DA
DB
x
© 2003, [email protected]
y
DB
143
L0
C
DL
DL
http://hartenstein.de
Kaiserslautern
University of
Technology
The microelectronics spare part problem
•Demand: several
decades of availability
[Hartenstein 2002]
• e. g. car price: ~25% electronics
•ICs do not survive
storage time
•Original fab line is no
more existing
2
1
0.5
© 2003, [email protected]
0.25
0.13 0.1 0,07µ feature size
144
http://hartenstein.de
Kaiserslautern
University of
Technology
The microelectronics spare part problem
[Hartenstein 2002]
key problem in many
application areas:
medical, aerospace,
automotive,
other transportation,
military, industrial
equipment controllers,
et al.
2
1
0.5
© 2003, [email protected]
0.25
0.13 0.1 0,07µ feature size
145
http://hartenstein.de
Dead Supercomputer Society
Kaiserslautern
University of
Technology
•ACRI
•Alliant
•American
Supercomputer
•Ametek
•Applied Dynamics
•Astronautics
•BBN
•CDC
•Convex
•Cray Computer
•Cray Research
•Culler-Harris
•Culler Scientific
•Cydrome
•Dana/Ardent/
Stellar/Stardent
[Gordon Bell, keynote at ISCA 2000].
•DAPP
•Denelcor
•Elexsi
•ETA Systems
•Evans and Sutherland
•Computer
•Floating Point Systems
•Galaxy YH-1
•Goodyear Aerospace MPP
•Gould NPL
•Guiltech
•ICL
•Intel Scientific Computers
•International Parallel
Machines
•Kendall Square Research
•Key Computer Laboratories
© 2003, [email protected]
146
•MasPar
•Meiko
•Multiflow
•Myrias
•Numerix
•Prisma
•Tera
•Thinking Machines
•Saxpy
•Scientific Computer
•Systems (SCS)
•Soviet Supercomputers
•Supertek
•Supercomputer Systems
•Suprenum
•Vitesse Electronics
http://hartenstein.de
CS: young ? dynamic?
Kaiserslautern
University of
Technology
.. but the von Neumann
Paradigm is still the
dominant doctrine ...
after >10 technology generations ...
•
•
•
... still pushing he basic
models from the times of •
•
mainframe dinosaurs
•
•
Microelectronics is
•
•
ignored (except falling cost
•
of computational effort)
•
•
© 2003, [email protected]
1th
2nd
3rd
4th
5th
6th
7th
8th
9th
10th
11th
.......
4004
... the vN Microprocessor
8008
is a methusela, the steam
8086
engine of the silicon age.
80286
80386
80486
P5 (Pentium)
P6 (Pentium Pro / Pentium II)
Pentium III
....
147
http://hartenstein.de
Kaiserslautern
University of
Technology
better to go for reconfigurable platforms
• [Dataquest] PLD market > $7 billion by 2003.
• fastest growing segment of semiconductor market
• IP reuse and silicon reuse
• FPGAs are going into every type of application
© 2003, [email protected]
148
http://hartenstein.de
Throughput vs. Flexibility
Kaiserslautern
University of
Technology
the anti machine
goes far beyond
bridging the gap
T. Claasen et al.: ISSCC 1999
*) R. Hartenstein: ISIS 1997
MOPS / mW
1000
throughput
100
hardwired
anti
machine
10
FPGAs
1
von
0.1
Neumann
flexibility
0.01
0.001
2
1
0.5
© 2003, [email protected]
0.25
0.13 0.1 0,07 µ feature size
149
http://hartenstein.de
Kaiserslautern
University of
Technology
Why coarse grain ?
© 2003, [email protected]
150
http://hartenstein.de
Kaiserslautern
University of
Technology
consensus
is near
digital system platforms:
platform
DPU data path unit
category
rDPU reconfigurable DPU
DPA data path array (DPU array)
hardware
rDPA reconfigurable DPA
RA reconfigurable array
set
processor ISP
ISPinstruction
instruction set
processor
AM anti machine
AMP data stream processor*
• morphware
rAMP reconfigurable AMP
*) no “dataflow machine” data stream
FPGA field-programmable gate array
FPL field-programmable logic
processor (AMP)
PLD programmable logic device
reconfigurable
CPLD complex PLD
AMP (rAMP)
categories of morphware:
morphware use
programming
source
(not programmable)
software
configware
streamware &
configware
• fine grain (~1 bit)
coarse grain (e.g. 32 bits)
reconfigurable computing
multi granular: by slice bundling
© 2003, [email protected]
151
machine
paradigm
none
von Neumann
FPGA: none
streamware
granularity (path width)
reconfigurable logic
Terminology
anti machine
(re)configurable blocks
CLBs
rDPUs (e.g. ALU-like)
rDPU slices (e.g. 4 bits)
http://hartenstein.de
>> Problems to be solved
Kaiserslautern
University of
Technology
© 2003, [email protected]
•
Configware Market
•
FPGA Market
•
Embedded Systems (Co-Design)
•
Hardwired IP Cores on Board
•
Run-Time Reconfiguration (RTR)
•
Rapid Prototyping & ASIC Emulation
•
Evolvable Hardware (EH)
•
Academic Expertise
•
ASICs dead
•
Soft CPU
•
HLLs
•
Problems to be solved
152
http://hartenstein.de
Kaiserslautern
University of
Technology
EDA industry shift into CS mentality
[Wojciech Maly]
• patches instead of engineering
• innovation stalled many years ago
• 85% users hate their tools
• netlist-based: do not care about efficiency, ...
• ... do not care about transistor density
© 2003, [email protected]
153
http://hartenstein.de
[Jonathan Rose] FPGAs Give You
Kaiserslautern
University of
Technology
• Instant Fabrication
– Get to Market Fast
– Fix ‘em quick
• Zero NRE Charges
– Low Risk
– Low Cost at good volume
© 2003, [email protected]
154
http://hartenstein.de
Kaiserslautern
University of
Technology
The Crisis of Computing Sciences
• Computing Sciences are in a severe crisis
• Computing curricula are obsolete because of strictly
enforced „procedural-only“ blinders
• Computer Architecture and related areas have
lost leadership in digital system implementation
• CS ignores > 90% µprocessors in embedded systems:
10 times more programmers will write embedded
applications than computer software by 2010
• A disruptive promising therapy introduced by new
approaches coming with Reconfigurable Computing
© 2003, [email protected]
155
http://hartenstein.de
Kaiserslautern
University of
Technology
Ubiquitous embedded systems
Embedded systems means:
20 billion µprocessors (2001)
• hardware / software
co-design
> 90% in embedded systems
10 times more programmers will
write embedded applications
than computer software by 2010
That’s where our graduates will go
© 2003, [email protected]
156
• configware / software
co-design
• hardware / configware /
software co-design
http://hartenstein.de
Kaiserslautern
University of
Technology
The Situation in Computing Sciences
• Computing Sciences are in a severe crisis
• New fundamentals and R&D directions are inevitable
• my mission: getting you involved
• All knowledge needed is readily available ...
• ... even from Computing Sciences
• Silicon application and EDA provide useful concepts
• Reconfigurable Computing has the remedy
© 2003, [email protected]
157
http://hartenstein.de
Kaiserslautern
University of
Technology
the edu gap has dramatic consequences
• Key R&D scenes are drying out or dying
• because of a lack of qualified researchers
• the embedded system design crisis gets worse
• because of a lack of qualified designers
• many innovative products cannot be sold
• because of a lack of qualified customers
• the edu gap is widening dramatically
• because of a lack of qualified educators
© 2003, [email protected]
158
http://hartenstein.de
Super Pipe Networks
Kaiserslautern
University of
Technology
array
systolic
array
supersystolic
DPA
applications
regular data
dependencies
only
pipeline properties
shape
resources
linear
only
uniform
only
mapping
linear projection or
algebraic synthesis
simulated
annealing or
P&R algorithm
no restrictions
scheduling
(data stream
formation)
(e.g. force-directed)
scheduling
algorithm
*) KressArray [ASP-DAC-1995]
© 2003, [email protected]
159
http://hartenstein.de
Kaiserslautern
University of
Technology
.... it‘s an alternative culture ....
• now the area is going mainstream: a rapidly widening
audience of non-specialists gets interested ...
• severe communication gaps due to educational deficits
• not only to users: still many hardware and EDA experts
ask: isn’t it just logic design on a strange platform ?
• it is time to clarify and popularize fundamental aspects
and to explain, that it is a fundamentally different culture
© 2003, [email protected]
160
http://hartenstein.de
“von Neumann” Computer:
the wrong Machine Paradigm
Kaiserslautern
University of
Technology
Xputer
Xputer
LabLab
University
Kaiserslautern
University
of of
Kaiserslautern
Computer
RAM
tightly coupled
by compact
instruction code
Compiler
instructions
Sequencer
Datapath
Datapath
program hardwired
counter:
loosely coupled
by decision
data bits only
“von
Neumann”
does not support
soft data paths
Xputer:
Compiler
Scheduler
“instructions”
(multiple)
sequencer
The Soft
Machine
Paradigm data
Datapath
Array
reconfigurable
counter s
also for hardwired
state register
© 2003, [email protected]
© 2001, [email protected]
RAM
Xputer
161
(anti machine)
http://hartenstein.de
Semiconductor Revolutions
Kaiserslautern
University of
Technology
“Mainstream Silicon Application
is switching every 10 Years”
standard
TTL
1957
custom
“The Programmable System-on-a-Chip
is the next wave“
hardwired
1967
procedural programming
µproc.,
memory
LSI,
MSI
1977
structural programming
2007
1987
ASICs,
accel’s
1997
algorithm: fixed
algorithm: variable
algorithm: variable
resources: fixed
resources: fixed
resources: variable
vN machine
Tredennick’s
paradigm
Paradigm Shifts
© 2003, [email protected]
162
anti machine
paradigm
http://hartenstein.de
Kaiserslautern
University of
Technology
Impact of Data-stream-based Embedded
... Hardware/
Repeat Success Story by
new Machine Paradigm !
standard
structural
personalization:
hardwired
before fabrication
µproc.,
memory
TTL
1967
1957
custom
Configware
Industry
LSI,
MSI
© 2003, [email protected]
2007
1987
1977
163
ASICs,
accel’s
1997
http://hartenstein.de
Kaiserslautern
University of
Technology
Rapidly growing CS education gap
• Our computing curricula are obsolete
• introduction is strictly „procedural-only“
• vN-only use of terms like „computer organisation“,
„ computer structures“, „ computer architecture
• graduates are not prepared to the real world
– most applications for embedded systems (>90% by 2010)
• our graduates are unable to compete with EE graduates
• only a few % curricula need to be changed
• my mission: getting
© 2003, [email protected]
you involved
164
http://hartenstein.de
Kaiserslautern
University of
Technology
Binding Time vs. Computing Domain
Binding time: (Set-up of
Communication Channels)
at run time
microprocessor
parallel computer
array processor
at loading time
Reconfigurable
Computing
at compile time
later fabrication step
supersystolic
arrays
systolic
arrays
before fabrication
programming domain:
© 2003, [email protected]
time domain
(procedural)
165
time & space
(hybrid)
ASICs
full custom
ICs
space domain
(structural)
http://hartenstein.de
Why Coarse Grain instead of FPGA ?
Kaiserslautern
University of
Technology
Sources: Proc ISSCC, ICSPAT, DAC, DSPWorld
physical
logical
100 000 000 000
FPGA
physical
Transistors / chip
10 000 000 000
1000 000 000
FPGA
routed
10 000 000
reduced reconfigurability
overhead by up to ~ 1000
1000 000
100 000
drastically
much
fastersmaller
loading
configuration memory
a lot of more benefits
10 000
© 2003, [email protected]
~ 10 000
FPGA
logical
100 000 000
1000
1980
~ 10
1990
2000
166
2010
http://hartenstein.de
Kaiserslautern
University of
Technology
What are the differences ?
vN* computing:
Reconfigurable Computing:
• computing in time
• computing in space and time
• instruction fetch
at run time
• procedural programming
• instruction scheduling
• “instruction” fetch at compile time
• structural programming
• data scheduling
• i. e. Data-stream-based
• also hardwired implementations**
*) vN stands for “von Neumann”
**) e g. Bee project Prof. Broderson
© 2003, [email protected]
• “instruction” fetch before fabrication
167
http://hartenstein.de
Basics of Binding Time
Kaiserslautern
University of
Technology
“Instruction”
generalized:
including
complex
expressions
and other
datapaths
time of “Instruction Fetch”
run time
parallel computer
loading time
strong impact on the
machine paradigm !
compile time
© 2003, [email protected]
microprocessor
168
Reconfigurable
Computing
http://hartenstein.de
Data-stream-based Parallelism
Kaiserslautern
University of
Technology
See my other talk
ICECS 2002
IEEE 9th International Conference
on Electronics, Circuits and Systems
Dubrovnik, Croatia
September 15-18, 2002
(invited paper)
Michael Herz,
Agilent
Technologies
Reiner
Hartenstein,
University of
Kaiserslautern
Memory Organisation for
Datastream-based
Reconfigurable Computing
Miguel Miranda,
Erik Brockmeyer,
Francky Catthoor,
IMEC, Leuven
© 2003, [email protected]
169
http://hartenstein.de
Machine paradigms
Kaiserslautern
University of
Technology
von Neumann
M
instruction
stream
instruction
stream
machine
data-stream machine
Flowware
data
path
I/O
M
I/O
(ALU)
memory
data address
generator
(data sequencer)
data asM*
stream
data
path
unit
CPU instruction
sequencer
Software
Configware
DPU or
rDPU
embedded memory architecture*
M M M M
I/O
M
M M M M
M
memory
I/O
(r)DPA
(r)DPU
© 2003, [email protected]
170
http://hartenstein.de
Kaiserslautern
University of
Technology
Synthesizable Memory Communication
An example by
Nageldinger’s
KressArray
Xplorer
Efficient Memory
Communication
should be directly
supported by the
Mapper Tools
Legend:
Optimized
Parallel
memory ports Memory
Controller
sequencers
application
not used
http://kressarray.de
© 2003, [email protected]
171
http://hartenstein.de
Kaiserslautern
University of Terminology has been
Technology
highly confusing
###############
factor
4y
2
30y
Battery capacity (1.03/year)
1
0
*) Department
10
12
of Trade and Industry, London
© 2003, [email protected]
18
24
172
36
months
10y
48
http://hartenstein.de
Semiconductor Revolutions
Kaiserslautern
University of
Technology
“Mainstream Silicon Application
is switching every 10 Years”
standard
TTL
1957
custom
“The Programmable System-on-a-Chip
is the next wave“
hardwired
1967
procedural programming
µproc.,
memory
LSI,
MSI
1977
structural programming
2007
1987
ASICs,
accel’s
1997
algorithm: fixed
algorithm: variable
algorithm: variable
resources: fixed
resources: fixed
resources: variable
vN machine
Tredennick’s
paradigm
Paradigm Shifts
© 2003, [email protected]
173
anti machine
paradigm
http://hartenstein.de
No vN bottleneck
Kaiserslautern
University of
Technology
The anti machine has no von
Neumann bottleneck.
© 2003, [email protected]
174
http://hartenstein.de
3 different mind sets
Kaiserslautern
University of
Technology
hardware people
TTL
1957
1967
CS
people
µproc.,
memory
LSI,
MSI
1977
new breed needed
1987
ASICs,
accel’s
FPGAs
1997
2007
soft
CPUs
coarse
grain
Common terminology needed
© 2003, [email protected]
175
http://hartenstein.de
Throughput vs. Flexibility
Kaiserslautern
University of
Technology
the anti machine
goes far beyond
bridging the gap
T. Claasen et al.: ISSCC 1999
*) R. Hartenstein: ISIS 1997
MOPS / mW
1000
throughput
100
hardwired
anti
machine
10
FPGAs
1
von
0.1
Neumann
flexibility
0.01
0.001
2
1
0.5
© 2003, [email protected]
0.25
0.13 0.1 0,07 µ feature size
176
http://hartenstein.de
Programming sources
Kaiserslautern
University of
Technology
von Neumann
instruction stream
machine
hardware
resources fixed
algorithms variable
software
hardwired only
Anti machine
data stream machine
morphware
resources variable
configware
algorithms variable
streamware
flowware
© 2003, [email protected]
177
reconfigurable
or hardwired
http://hartenstein.de
Some soft CPU core examples
Kaiserslautern
University of
Technology
core
architecture
platform
MicroBlaze
125 MHz 70
D-MIPS
32 bit
standard RISC
32 reg. by 32
LUT RAMbased reg.
Xilinx up to
100 on one
FPGA
Nios
16-bit
instr. set
Nios
50 MHz
Nios
core
architecture
platform
Leon
25 Mhz
SPARC
ARM7 clone
ARM
uP1232 8-bit
CISC, 32 reg.
Altera
Mercury
200 XC4000E
CLBs
REGIS
32-bit
instr. set
Altera
22 D-MIPS
8 bits Instr. +
ext. ROM
2 XILINX
3020 LCA
Reliance-1
12 bit DSP
8 bit
Altera –
Mercury
Lattice
4 isp30256,
4 isp1016
1Popcorn-1
8 bit CISC
Altera, Lattice,
Xilinx
gr1040
16-bit
gr1050
32-bit
My80
i8080A
FLEX10K30
or EPF6016
YARD-1A
16-bit RISC,
2 opd. Instr.
old Xilinx FPGA
Board
DSPuva16
16 bit DSP
Spartan-II
xr16
RISC integer C
SpartanXL
© 2003, [email protected]
Acorn-1
178
1 Flex 10K20
http://hartenstein.de
Kaiserslautern
University of
Technology
FPGA CPUs in teaching and
academic research
• Michigan State
• Universidad de
Valladolid, Spain
• Virginia Tech
• Washington
University, St. Louis
• New Mexico Tech
• UC Riverside
• Tokai University,
Japan
• UCSC: 1990!
• Märaldalen University,
Eskilstuna, Sweden
• Chalmers University,
Göteborg, Sweden
• Cornell University
• Gray Research
• Georgia Tech
• Hiroshima City
University, Japan
© 2003, [email protected]
179
http://hartenstein.de
Loop Transformation Examples
Kaiserslautern
University of
Technology
sequential processes:
loop 1-16
body
endloop
resource parameter driven
Co-Compilation
host:
loop 1-8
trigger
endloop
loop 1-8
fork
body
body
loop 1-8 loop 9-16
endloop body
body
endloop endloop
loop
unrolling
loop 1-4
trigger
endloop
loop 1-2
trigger
endloop
join
strip mining
© 2003, [email protected]
reconf.array:
180
http://hartenstein.de
Kaiserslautern
University of
Technology
CS Education
….
…However,
is basedcurrent
on the Submarine
Model
This model disables ...
Algorithm
procedural high level
Programming Language
Brain usage:
procedural-only
Assembly Language
Hardware invisible:
under the surface
Hardware
© 2003, [email protected]
181
http://hartenstein.de
Kaiserslautern
University of
Technology
Hardware and Software as Alternatives
procedural
structural
Algorithm
partitioning
Brain Usage:
both Hemispheres
Hardware,
Configware
Software
Hardw/Configw
Softwareonly
& Hardw/Configw
Software only
© 2003, [email protected]
182
http://hartenstein.de
Kaiserslautern
University of
Technology
(procedural)
The Dominance of the Submarine Model
structurally
disabled
Hardware
.. indicates, that our CS Education
System produces Zillions of
Mentally Disabled Persons
… completely disabled to cope with
Solutions other than Software only
© 2003, [email protected]
183
http://hartenstein.de
Kaiserslautern
University of
Technology
Design Space Exploration Systems
interactive
status evaluation
status generation
[66]
no
abstract models
rule-based
1992
[67]
yes
prediction models
device generator
DIA
1998
[68]
yes
prediction from library
rule-based
DSE for RAW
1998
[49]
no
analytical models
analytical
ICOS
1998
[76]
no
fuzzy logic
greedy search
DSE for Multimedia 1999
[77]
no
simulation
branch and bound
yes
fuzzy rule-based
simulated annealing
Explorer System
year source
DPE
1991
Clio
Xplorer
1999 [11] [50]
© 2003, [email protected]
184
http://hartenstein.de
History of Computing
Kaiserslautern
University of
Technology
Makimoto’s Wave
TTL
1957
1967
µproc.
memory
1977
1997
classical CS
mainframes
2007
1987
new CS
PC
?
© 2003, [email protected]
185
http://hartenstein.de
… Wintel Business Model
Kaiserslautern
University of
Technology
Billion US-$ US Market [forrester]
Million Devices delivered in the U.S.
20
20
[IDC]
15
1500 $
1000 $
1997 1998
10
1999
2000
2001
2002
© 2003, [email protected]
186
http://hartenstein.de
Tredennick’s Paradigm Shifts
Kaiserslautern
University of
Technology
standard
TTL
1957
custom
hardwired
1967
procedural programming
µproc.,
memory
LSI,
MSI
1977
structural programming
2007
1987
ASICs,
accel’s
1997
2 sources
algorithm: fixed
algorithm: variable
algorithm: variable
resources: fixed
resources: fixed
resources: variable
© 2003, [email protected]
vN machine
paradigm
187
new machine
paradigm needed
http://hartenstein.de