Transcript Porting Strategy

Advanced Porting The
Framework
Intel Corporation
Software and Services Group
1
Agenda
• Create a New Platform Build
• Minimal porting job to run EFI Shell
• Platform specific porting features
®
UEFI / Framework Training 2008
Copyright © 2006-2008 Intel Corporation
•Other trademarks and brands are the property of their respective owners
Slide 2
New Platform Build
Create a New Project Directory
•
•
•
•
•
®
Identify the Platform that this Project is a part of,
PROJECT_PLATFORM. Platforms are usually closely
tied to a processor/north bridge/south bridge
combination.
Choose a Project name, PROJECT_NAME. This is
often defined in the PlatformTools.env. Currently we
are describing Bearlake as an example project name.
Choose a Project family, PROJECT_FAMILY. This is
often defined in the PlatformTools.env.
The Platform\PROJECT_FAMILY\
PROJECT_PLATFORM directory to
Platform\PROJECT_FAMILY \PROJECT_NAME. In
the case of the Bearlake example platform, the source
directory to copy is
Platform\IntelDpg\PROJECT_PLATFORM.
UEFI / Framework Training 2008
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Slide 3
\ Framework
\ Application
\ Bus
\ Chipset
\
\
\
\
\
\
\
\
\
\
\
The Framework Directory Tree
8.x code base
Lakeport
Bearlake - MemoryInit
Blackford - MemoryInit
ESB2
IntelIch - ICHX
ICHX - SmBus
SMC
CPU
CSM
GUID
Include
Library
Platform
Bearlake
\ IntelDpg – Lakeport
\ IntelEsg – StarLake
\ IntelSSG
\ Lakeport
Bearlake
Pei – Dxe - Platform
Pei – Dxe - Platform
- Build
\ Ppi
\ Protocol
\ Tools
®
UEFI / Framework Training 2008
Copyright © 2006-2008 Intel Corporation
•Other trademarks and brands are the property of their respective owners
Slide 4
Agenda
• Create a New Platform Build
• Minimal porting job to run EFI Shell
• Platform specific porting features
• \$(PLATFORM_SOUTH_PATH) for LAKEPORT
is \IntelDpg\Lakeport
®
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Slide 5
General Overview
PWR ON
SEC
SECurity
PEI
Pre-Efi Initialization
DXE
Driver Xecution Environment
BDS
Boot Device Selection
OS
®
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Slide 6
Boot Flow
Exposed
Platform
Interface
verify
Pre
Verifier
CPU
Init
Chipset
Init
Transient OS
Environment
Device,
Bus, or
Service
Driver
Board
Init
EFI Driver
Dispatche
r
Transient OS
Boot Loader
Security
Pre EFI
(SEC) Initialization
(PEI)
®
Driver
Execution
Environment
(DXE)
[ . . Platform initialization . . ]
OS-Present
App
Boot
Manager
Intrinsic
Services
security
Power on
OS-Absent
App
Boot Dev
Select
(BDS)
Final OS
Boot Loader
Final OS
Environment
?
Transient
System Load
(TSL)
Run Time
(RT)
After
Life
(AL)
[ . . . . OS boot . . . . ]
Shutdown
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Slide 7
System Block Diagram
legacy Option
ROMs
legacy OS
Loader
EFI
EFI OS Loader
®
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Slide 8
Pre-EFI Initiialization (PEI)
Hardware
Driver Execution Environment
Architectural
HardwareModules
Specific
Protocols
Pre-EFI
Compatibility
Support Module
EFI
Drivers
Platform
Platform
Drivers
Drivers
Framework Drivers
Foundations
DXE
Foundation
PEI
Foundation
\ Framework
\ Application
\ Bus
\ Chipset
\
\
\
\
\
\
\
\
\
\
\
The Framework Directory Tree
8.x code base
BearLake - MemoryInit
Blackford - MemoryInit
ESB2
IntelIch - ICHX
- SmBus
SMC
CPU
CSM
GUID
Include
Library
Platform
\ IntelDpg – Bearlake
\ IntelEsg – StarLake
Pei – Dxe - Platform
Pei – Dxe - Platform
\ IntelSSG
\
\
Bearlake
StarLake
- Build
- Build
\ Ppi
\ Protocol
\ Tools
®
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•Other trademarks and brands are the property of their respective owners
Slide 9
Minimal porting job to run EFI Shell
Porting SEC
• Reset Fetches Code from FLASH
– Enables Flat Protected Mode Execution
• SEC Enables Temp Memory
– Data and Stack Cached
– Enables Execution of C Code
– Transfers Control to PEI Foundation
®
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Slide 10
Minimal porting job to run EFI Shell
Temporary Memory
0xFFFF_FFFF
0xFFF8_0000
0xFF00_0000
0xFEF0_0000
System
SystemFLASH
ROM
(512
(16 MB)
KB)
Framework Code
and Data Stored Here
Temp Memory
SEC Maps Unused
Region as Temporary
Memory
Local APIC
0xFEE0_0000
0xFED0_0000
0xFEC0_0000
0xZZZ0_0000
I/O APIC
PCI Resources
0xYYY0_0000
Low Top Of Memory
System Memory
0x0000_0000
®
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Slide 11
Minimal porting job to run EFI Shell
SEC phase
• Currently SEC phase is where the Reset vector
will start
• \Platform\$(PLATFORM_SOUTH_PATH)\Comm
on\Sec\Ia32\ResetVec.asm
• \Platform\$(PLATFORM_SOUTH_PATH)\Comm
on\Sec\Ia32\Flat32.asm
®
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Slide 12
Minimal porting job to run EFI Shell
PEI Phase
• The PEI phase’s purpose is to:
–
–
–
–
–
®
Determine the boot mode
Perform low-level initialization of the platform
Discover and initialization main memory
Invoke recovery if desired
Transfer control to DXE or S3 waking vector
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Slide 13
Minimal porting job to run EFI Shell
PEI Phase Overall Initialization
• Two PEIMs contain the majority of the platform’s
initialization code :
Platform\$(SOUTH_PLATFORM_PATH)\Pei\Platform\Stage1
Platform\$(SOUTH_PLATFORM_PATH)\Pei\Platform\Stage2
• The Platform Stage1 PEIM module does the platform
initialization according to platform policy or board layout.
Stage1 focuses on ICH related platform initialization,
such as ICH GPIO initialize, since GPIO usage and
initialize value is according to board layout design.
• The Platform Stage2 PEIM module does the platform
initialization according to platform policy or board layout.
Platform Stage2 focuses on MCH related platform
initialization, such as onboard Graphics enable/disable.
®
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Slide 14
Minimal porting job to run EFI Shell
Platform Specifics in Platform.h
\Platform\$(PLATFORM_SOUTH_PATH)\Common\Pei\Plat
form\Platform.h
• Memory DIMM SMBUS address
• Firmware Hub GPIO base address and recovery jumper
number
• ICH ACPI base address, ICH GPIO base address, SIO
base address, ICH RCBA base address
• Early resource address such as AC97 audio memory
mapped IO base address, ICH SMBUS base address,
ICH IDE base address.
• ICH GPIO mappings
• PEI memory usage
• ICH ACPI timer related settings such as resolution,
address, and max value.
®
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Slide 15
Minimal porting job to run EFI Shell
GPIO Initialization
• PEIM for ICH GPIO initialization
• Table - mIchGpioInitTable
Register
OFFSET
GPIO_USE_SEL
GPIO_IO_SEL
GPIO_INV
GPIO_IO_SEL2
®
Value
0x1F3DF7C1
0xE6FFFFFF
0x0000A000
0x000000FF
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Slide 16
Minimal porting job to run EFI Shell
Code Example
FILE: Platform\ \$(PLATFORM_SOUTH_PATH)\
Common\Pei\Platform\Stage1\IchInit.c
static const ICH_GPIO_DEV mIchGpioInitTable [] = {
//
Register OFFSET,Value
// 0/1 - Native function/GPIO
GPIO_USE_SEL, GPIO_USE_SEL_VAL,
GPIO_USE_SEL2, GPIO_USE_SEL2_VAL,
// 0/1 - Output/Input
GPIO_IO_SEL, GPIO_IO_SEL_VAL,
GPIO_IO_SEL2, GPIO_IO_SEL2_VAL,
// 0/1 - Active High/Low
GPIO_INV,
GPIO_INV_VAL
};
®
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Slide 17
Minimal porting job to run EFI Shell
GPIO Values
The table allows you to define the register offset and value
that is needed to program the GPIO’s. You can set them
up for input/output/tri-state and set the high/low values
using the following defines:
GPIO_USE_SEL – which GPIO’s to program
GPIO_IO_SEL – which direction
GPIO_INV – switch High/Low state(setting)
These values – GPIO_USE_SEL, GPIO_IO_SEL, and
GPIO_INV are defined in the file:
\Platform\$(PLATFORM_SOUTH_PATH)\Common\Pei\P
latform\Platform.h
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Slide 18
Minimal porting job to run EFI Shell
ICH Initialization
• Power-on ICH initialization is performed in PEI to:
–
–
–
–
Initialize the system buses (LPC, PCI, SMBUS)
Turn-off the watchdog timer
Program the interrupt pins
Other miscellaneous chipset initialization needed prior to
memory detection
• This initialization is performed in the file:
Platform\ $(PLATFORM_SOUTH_PATH)\Pei\Platform\Stage1\IchInit.c
• ICH address constants and additional ICH constants are
declared in the file:
Platform\ $(PLATFORM_SOUTH_PATH)\Pei\Platform\Platform.h
• Platform component initialization based on user setup
preferences is performed later in the DXE ICH
initialization.
• Resetting of the ICH is performed in the file:
Chipset\IntelIch\IchX\IchInit\Pei\IchReset.c
®
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Slide 19
Minimal porting job to run EFI Shell
Super I/O Initialization
• Power-on Super I/O initialization is performed in
the file:
– Platform\($(PLATFORM_SOURCE_PATH)\Pei\Platform\Stage1\
SioInit.c
• Devices connected to the LPC bus (e.g. fans,
floppy) component initialization is performed
later in the DXE Super I/O initialization
®
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Slide 20
Minimal porting job to run EFI Shell
PCI Routing
• PCI IRQ routing table is required by
some legacy OSes
• DXE driver that perform PCI devices
routing
– Platform\$(PLATFORM_SOUTH_PATH)\
Common\Dxe\LegacyBios\platform.c
• Table – PirqTableHead
Pin 1
Bus
Dev
Reg
0x00
0x08
0x02
0x10
®
Map
Pin 2
Reg
Map
Pin 3
Pin 4
Reg
Map
Reg
Map
Slot
0x60 0xDEB8 0x61 0xDEB8
0x00
0x0000
0x00
0x0000
0x00
0x0000
0x61 0xDEB8 0x62 0xDEB8
0x63 0xDEB8
0x60 0xDEB8 0x03
0x0000
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Slide 21
PIRQ Table Code
Example in File:
Platform\$(PLATFORM_SOUTH_PATH)\Common\Dxe
\LegacyBios\platform.c
EFI_LEGACY_PIRQ_TABLE PirqTableHead = {
{0x52495024,00,01,0000,00,00,0000,0x8086,
0x122e,00000000,00,00,00,00,00,00,00,
00,00,00,00,00},
{
// Memory Controller devices
//
DEFINE_PCI_ROUTINE (0, 1, PIRQA, PIRQB, PIRQC, PIRQD, 0, 0),
//
PEG graphics port
DEFINE_PCI_ROUTINE (1, 0, PIRQA, PIRQB, PIRQC, PIRQD, 0x7, 0xFF),
// PEG slot
DEFINE_PCI_ROUTINE (0, 2, PIRQA, 0, 0, 0, 0, 0),
// On-board
graphics
DEFINE_PCI_ROUTINE (0, 3, PIRQA, PIRQB, PIRQC, 0, 0, 0),
//
HECI
...
®
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Slide 22
PCI IRQ routing in the ACPI Tables
Example in File:
Platform\$(PLATFORM_SOUTH_PATH)\Common\
Dxe\AcpiTables\asl\OnBoardPrt.asi
It contains the internal PCI devices and onboard
PCI devices IRQ routing information. Generally,
all internal PCI devices with ICH or MCH should
be listed. For example, USB, IDE, SATA and
AC97 controllers in ICH and graphics controller
in MCH
®
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Slide 23
Minimal porting job to run EFI Shell
Flash ROM
• Implement EFI_FIRMWARE_VOLUME_
BLOCK_PROTOCOL
• Enables Variable Write Services
• Initializes platform specific flash device
– Platform\Generic\RuntimeDxe\FvbServices\<Pla
tform>
– FWBlockService.c
• Possible functions for FWH or SPI access
–
–
–
–
®
EnableFvbWrites ( )
EnablePlatformFvb ( )
PlatformGetFvbWriteBase ( )
SetPlatformFvbLock ( )
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Slide 24
Minimal porting job to run EFI Shell
SMBus
SM Bus
• PEIM for ICH SMBus initialize
– Chipset\IntelIch\IchX\Smbus IchSmbus.c
• Functions to provide a standard way to access
SMBus
– SmbusExecute ( )
– SmbusIoRead ( )
– SmbusIoWrite ( )
®
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Slide 25
Minimal porting job to run EFI Shell
DXE IPL
• Shadow DXE IPL in permanent memory
– To allow sharing of decompression algorithm with
DXE
• Allocate 128KB stack for DXE
• Create HOBs
– Decompression protocol passed as HOB
• Firmware Volumes
– Passed in HOB
• Handle S3 transition
• Switch Stacks to call DXE Main
®
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Slide 26
Minimal porting job to run EFI Shell
Initialize System Memory
• PEIM that performs system memory
initialization
SM Bus
– Chipset\<Chipset>
• Memory detection
– PEI_DUAL_CHANNEL_DDR_MEMORY_CONTROLLER_PPI
•
•
•
•
•
Reset
RowInfo
GetMemoryMap
DetectMemory
ConfigureMemory
• Memory clock control
– PEI_DUAL_CHANNEL_DDR_CLOCK_GENERATOR_PPI
• Capabilities
• GetFrequency
• SetFrequency
®
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Slide 27
Minimal porting job to run EFI Shell
Integrating Memory Init Code
• MRC directory Chipset\<Chipset>\MemoryInit
• The file MemoryInit.Inf describes the Memory Reference
code contained within its description (.dsc) file.
• After calling the entry to this memory init routine and
successfully exiting, the memory should be ready to use.
It builds HOBs to describe the memory address space
and their attributes.
• Some of the HOB information that is produced by the
MRC:
• S3 Memory
• SMRAM Descriptor HOB
• Memory Descriptor HOB
• T-size configuration setup option (variable)
®
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Slide 28
Minimal porting job to run EFI Shell
PEI Modules
SM Bus
CPU PEIM
DXE IPL PEIM
PCI Configuration PEIM
Stall PEIM
Status Code PEIM
SMBus PEIM
Memory Controller PEIMs
Motherboard PEIM
®
Platform
Generic
PCAT
PCAT
Platform
South Bridge
North Bridge
Platform
Init and CPU I/O
Starts DXE Foundation
Uses I/O 0xCF8, 0xCFC
Uses 8254 Timer
Debug Messages
SMBus Transactions
Read SPD, Init Memory
FLASH Map, Boot Policy
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Slide 29
Minimal porting job to run EFI Shell
PPI Example
typedef
EFI_STATUS
(EFIAPI *PEI_SMBUS_PPI_EXECUTE_OPERATION) (
IN
EFI_PEI_SERVICE
**PeiServices,
IN
struct EFI_PEI_SMBUS_PPI *This,
IN
EFI_SMBUS_DEVICE_ADDRESS SlaveAddress,
IN
EFI_SMBUS_DEVICE_COMMAND Command,
IN
EFI_SMBUS_OPERATION
Operation,
IN
BOOLEAN
PecCheck,
IN OUT UINTN
*Length,
IN OUT VOID
*Buffer
);
typedef struct {
PEI_SMBUS_PPI_EXECUTE_OPERATION
PEI_SMBUS_PPI_ARP_DEVICE
} EFI_PEI_SMBUS_PPI;
®
Execute;
ArpDevice;
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Slide 30
Minimal porting job to run EFI Shell
PEIM Pseudo Code
#define SMBUS_R_HD0
#define SMBUS_R_HBD
0xEFA5
0xEFA7
EFI_PEI_SERVICES
SMBUS_PRIVATE_DATA
UINT8 Index, BlockCount
UINT8
*PeiServices;
*Private;
*Length;
*Buffer;
BlockCount = Private->CpuIo.IoRead8 (
*PeiServices,Private->CpuIo,SMBUS_R_HD0);
if (*Length < BlockCount) {
return EFI_BUFFER_TOO_SMALL;
} else {
for (Index = 0; Index < BlockCount; Index++) {
Buffer[Index] = Private->CpuIo.IoRead8 (
*PeiServices,Private->CpuIo,SMBUS_R_HBD);
}
}
®
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Slide 31
Minimal porting job to run EFI Shell
What Are Architectural
Protocols
• Typically functions that isolate platform specific
hardware (e.g. real-time clock)
• Provide support for boot services and runtime
services
• Low level protocols that support DXE APIs (e.g.
Boot and Runtime services)
• Directly called by DXE core
®
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Slide 32
Minimal porting job to run EFI Shell
DXE Architectural
Protocols
Watchdog
Monotonic Counter
Runtime
CPU
BDS
Timer
Metronome
Reset
Real Time Clock
Security
Status Code
Variable
®
Generic
Generic
Generic
Platform
Platform
PCAT
PCAT
PCAT
PCAT
Platform
Platform
Platform
Uses Timer-based Events
Uses Variable Services
Platform Independent
Processor DXE Driver
Platform Policy and TSL phase
Uses 8254 Timer
Uses 8254 Timer
I/O 0xCF9
I/O 0x70-0x71
Platform Specific Authentication
Debug Messages
Depends on FLASH Map
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Slide 33
Minimal porting job to run EFI Shell
DXE Drivers Consuming
Architectural Protocols
• Host bridge driver
– Chipset\PcatCompatible\SimplePciHostBridge\Dxe
• ICH initialize driver
– Chipset\IntelIch\IchX\IchxInit\Dxe
• IDE controller driver
– Chipset\IntelIch\IchX\IdeController\Dxe
• SMBus DXE driver
– Chipset\IntelIch\IchX\Smbus\Dxe
• Super I/O
– Chipset\<SuperIO Vendor>\Dxe
®
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Slide 34
Minimal porting job to run EFI Shell
NT Emulation Timer Arch Protocol
EFI_STATUS
TimerDriverSetTimerPeriod (
IN EFI_TIMER_ARCH_PROTOCOL *This,
IN UINT64
TimerPeriod
)
{
. . .
gWinNt->EnterCriticalSection (&mNtCriticalSection);
mTimerPeriod = TimerPeriod;
mCancelTimerThread = FALSE;
gWinNt->LeaveCriticalSection (&mNtCriticalSection);
mNtLastTick = gWinNt->GetTickCount ();
mNtTimerThreadHandle = gWinNt->CreateThread (
NULL,
0,
NtTimerThread,
&mTimer,
0,
&NtThreadId);
. . .
}
®
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Slide 35
Minimal porting job to run EFI Shell
Itanium Timer Arch Protocol
EFI_STATUS
TimerDriverSetTimerPeriod (
IN EFI_TIMER_ARCH_PROTOCOL *This,
IN UINT64
TimerPeriod
)
{
. . .
mTimerCount = (mCpuFrequency * TimerPeriod) / NUMBER_OF_100NS_IN_A_SECOND;
SetupItm (mTimerCount);
//
//
//
//
mov
loc2 = ar.itc;;
add
loc2 = loc2, in0;;
mov
cr.itm = loc2
srlz.d;;
ItcInterruptControl (TRUE, TIMER_VECTOR_NUMBER);
//
mov
loc2 = in1
//
mov
loc3 = 0x1
//
mov
loc4 = pr
//
cmp.eq p6,p7 = in0,r0;;
//
// (p7) dep
loc2 = r0,loc2,16,1;;
// (p6) dep
loc2 = loc3,loc2,16,1;;
//
//
mov
cr.itv = loc2;;
//
srlz.d;;
//
mov
pr = loc4,0x1ffff
// Clear mask to enable intr
// Set mask to disable intr
. . .
}
®
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Slide 36
Minimal porting job to run EFI Shell
XScale Timer Arch Protocol
EFI_STATUS
TimerDriverSetTimerPeriod (
IN EFI_TIMER_ARCH_PROTOCOL *This,
IN UINT64
TimerPeriod
)
{
UINT64 Count;
UINT32 Data;
. . .
Count = DivU64x32 (MultU64x32 (TimerPeriod, OST_CRYSTAL_FREQ) + 5000000,
10000000, NULL);
mCpuIo->Mem.Read (mCpuIo,EfiWidthUint32,OSCR_BASE_PHYSICAL,1,&Data);
Data += (UINT32)Count;
mCpuIo->Mem.Write (mCpuIo,EfiWidthUint32,OSMR0_BASE_PHYSICAL,1,&Data);
mCpuIo->Mem.Read (mCpuIo,EfiWidthUint32,OIER_BASE_PHYSICAL,1,&Data);
Data |= (UINT32)1;
mCpuIo->Mem.Write (mCpuIo,EfiWidthUint32,OIER_BASE_PHYSICAL,1,&Data);
mCpuIo->Mem.Read (mCpuIo,EfiWidthUint32,ICMR_PHYSICAL,1,&Data);
Data |= (UINT32)(1 << SA_OST0_IRQ_No);
mCpuIo->Mem.Write (mCpuIo,EfiWidthUint32,ICMR_PHYSICAL,1,&Data);
. . .
}
®
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Slide 37
Minimal porting job to run EFI Shell
8254 Based Timer Arch Protocol
EFI_STATUS
TimerDriverSetTimerPeriod (
IN EFI_TIMER_ARCH_PROTOCOL *This,
IN UINT64
TimerPeriod
)
{
UINT64 Count;
UINT8
Data;
. . .
Count = DivU64x32 (MultU64x32(119318, (UINTN) TimerPeriod) + 500000,
1000000, NULL);
Data = 0x36;
mCpuIo->Io.Write(mCpuIo,EfiCpuIoWidthUint8,TIMER_CONTROL_PORT, 1, &Data);
mCpuIo->Io.Write(mCpuIo,EfiCpuIoWidthFifoUint8,TIMER0_COUNT_PORT,2,&Count);
mLegacy8259->EnableIrq (mLegacy8259, Efi8259Irq0, FALSE);
. . .
}
Different Implementations
Same Protocol Interface
®
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Slide 38
Minimal porting job to run EFI Shell
Serial Terminal Console
Services
BDS / EFI Shell
Simple Input
Protocol
Simple Text
Output Protocol
Virtual
Console
Simple Input
Protocol
Simple Text
Output Protocol
Physical
Console
Serial I/O Protocol
ISA I/O Protocol
Super I/O
PCI I/O Protocol
PCI Root Bridge
I/O Protocol
®
PCI Host Bridge Resource
Allocation Protocol
ISA ACPI Protocol
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Slide 39
Minimal porting job to run EFI Shell
Serial Terminal Console Drivers
BDS / EFI Shell
Console Splitter
Terminal
ISA Serial
ISA Bus
PCI Bus
Console Platform
PCI Root Bridge
PCI Host Bridge
ISA ACPI
®
Generic
Generic
Generic
PCAT
Generic
Generic
Platform
North Bridge
North Bridge
Super I/O
Super I/O
Platform Specific Policy
Work with Chipset Vendor
Work with Chipset Vendor
Work with Super I/O Vendor
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Copyright © 2006-2008 Intel Corporation
•Other trademarks and brands are the property of their respective owners
Slide 40
Minimal porting job to run EFI Shell
DXE Driver for Console
Services
• Console Splitter Driver
– Edk\Sample\Universal\Console\ConSplitter\Dxe
• Graphics Console Driver
– Edk\Sample\Universal\Console\GraphicsConsole\
Dxe
• Terminal Driver
– Edk\Sample\Universal\Console\Terminal\Dxe
• UGA Driver (optional)
– Chipset\<Vendor>\Uga\Dxe
®
UEFI / Framework Training 2008
Copyright © 2006-2008 Intel Corporation
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Slide 41
Minimal porting job to run EFI Shell
Porting Summary
Do Minimum to Run EFI Shell
Status Code
Memory Controller
SMBUS
Motherboard
Security
Status Code
Variable
Console Platform
PCI Root Bridge
PCI Host Bridge
ISA ACPI
®
PEI
PEI
PEI
PEI
DXE
DXE
DXE
DXE
DXE
DXE
DXE
Platform
North Bridge
South Bridge
Platform
Platform
Platform
Platform
Platform
North Bridge
North Bridge
Super I/O
SM Bus
UEFI / Framework Training 2008
Copyright © 2006-2008 Intel Corporation
•Other trademarks and brands are the property of their respective owners
Slide 42
Further Information
• Documents Directory on CD
– Framework Mini PortingGuide
– FrameworkTechPortingRef
– FrameworkPortingList
®
UEFI / Framework Training 2008
Copyright © 2006-2008 Intel Corporation
•Other trademarks and brands are the property of their respective owners
Slide 43
Q&A
®
UEFI / Framework Training 2008
Copyright © 2006-2008 Intel Corporation
•Other trademarks and brands are the property of their respective owners
Slide 44
®
UEFI / Framework Training 2008
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•Other trademarks and brands are the property of their respective owners
Slide 45
Back up
®
UEFI / Framework Training 2008
Copyright © 2006-2008 Intel Corporation
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Slide 46
2009 release Centrino Mobile
Technology platform
• Porting example
• New form footprint no longer North / South Bridge
template
• Core / Uncore part of the Processor
• Platform Control Hub (PCH) integrated successor to
MCH + ICH instead of South Bridge
• Power management considerations on mobile
• Silicon released as Separate UEFI reference modules
–
–
–
–
–
®
PCH Reference code
Core / Uncore CPU Reference code
ACPI
Power Management
Memory Reference code
UEFI / Framework Training 2008
Copyright © 2006-2008 Intel Corporation
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Slide 47
Platform
\ Platform
\ IntelDpg – Bearlake Pei – Dxe - Platform
\ IntelEsg – StarLake Pei – Dxe - Platform
\ IntelMpg – MobilePlatform
\ AcpiTables
\ Dsdt
\ SsdtPtid
\ VaAcpiTables
\
\
\
\
\
\
\
®
ACPI Module Package
Build
Include
LegacyBiosPlatform
Library
PciPlatform
PlatformSetup
SmbiosMisc
UEFI / Framework Training 2008
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Slide 48
Platform Control Hub - Chipset
\ Chipset
\ IntelIch
\ IntelPch – Mobile Chipset (IbexPeak)
\
\
\
\
\
\
\
\
\
\
\
\
®
ActiveBios
Include
IoTrap
LegacyInterrup
Library
PchInit
PchSmiDispatcher
PciExpress
Ppi
Protocol
RaidRom
Reset
\
\
\
\
\
\
\
\
\
\
S3Support
SampleCOde
SataController
SerialGpio
SmartTimer
SmBus
SmmControl
Spi
Uhci
Veci
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Slide 49
Core/Uncore IIO Elements\ CPU
\ UncoreCommon
\
\
\
\
\
\
\
\
AcpiTables
Guid
Include
LegacyRegion
Library
PciHostBridge
SmbiosMemory
SmmAccess
\ FieldUncore
\ Iio (Integrated I/O )
\
\
\
\
®
IioInit
IioInitLib
Include
Protocol
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Slide 50
Power Management\ Platform
\ IntelDpg – Bearlake Pei – Dxe - Platform
\ IntelEsg – StarLake Pei – Dxe - Platform
\ IntelMpg – MobilePlatform
\ ...
\ Common
\ PowerManagement
\ AcpiTables
\ Guid
\ Include
\ Library
\ Protocol
\ Smm
®
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Slide 51
Memory Init
\ CPU
\ UncoreCommon
\ ...
\ FieldUncore
\ Iio (Integrated I/O )
\ ...
\ CsiMemoryInit
\
\
\
\
®
CSI
PPI
PEI
Memory
UEFI / Framework Training 2008
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Slide 52
Others
\ Microcode updates
\ CSM
®
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Slide 53
Agenda
• Create a New Platform Build
• Minimal porting job to run EFI Shell
• Platform specific porting features
®
UEFI / Framework Training 2008
Copyright © 2006-2008 Intel Corporation
•Other trademarks and brands are the property of their respective owners
Slide 54
Platform specific porting features
Add Platform Features - IDE
BDS / EFI Shell
File Sys Protocol
File Sys Protocol
Disk I/O Protocol
Disk I/O Protocol
SM Bus
Block I/O Protocol Block I/O Protocol Partition
Disk I/O Protocol
Disk I/O Protocol
Block I/O Protocol Block I/O Protocol Physical Disk
PCI I/O Protocol
PCI Root Bridge
I/O Protocol
®
PCI Host Bridge Resource
Allocation Protocol
IDE Controller Init
UEFI / Framework Training 2008
Copyright © 2006-2008 Intel Corporation
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Slide 55
Platform specific porting features
Add Platform Features - IDE
BDS / EFI Shell
FAT
Partition
Disk I/O
IDE Bus
PCI Bus
PCI Root Bridge
PCI Host Bridge
IDE Controller Init
®
Generic
Generic
Generic
Generic
PCAT
Generic
North Bridge
North Bridge
South Bridge
SM Bus
IDE Channel Attributes
UEFI / Framework Training 2008
Copyright © 2006-2008 Intel Corporation
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Slide 56
Platform specific porting features
Add Platform Features
• Integrated USB
– Work with Chipset Vendor
– USB Host Controller Protocol
• Integrated Video
– Work with Chipset Vendor
– UGA Draw and UGA I/O Protocol
• Integrated LAN
– Work with Chipset Vendor
– UNDI Driver
• AGP and PCI Slots
– Work with IHVs to Provide EFI Drivers
®
UEFI / Framework Training 2008
Copyright © 2006-2008 Intel Corporation
•Other trademarks and brands are the property of their respective owners
Slide 57
Platform specific porting features
Compatibility Support Module
• Implement Platform and Chipset Specific
Protocols
– Legacy BIOS Platform
– Legacy Region
– Legacy Interrupt
• Enables POST of Legacy Option ROMs
– Video Controllers
– Disk Controllers
– Network Interface Controllers
• Enables Legacy OS Boot
– Linux, Windows XP, Windows 2000
®
UEFI / Framework Training 2008
Copyright © 2006-2008 Intel Corporation
•Other trademarks and brands are the property of their respective owners
Slide 58
Platform specific porting features
CSM drivers
• LegacyBios driver
– Csm\LegacyBios\Dxe
• BiosThunk drivers – BIOS drivers for Legacy
OS boot
–
–
–
–
®
Csm\BiosThunk\VgaMiniPort\Dxe
Csm\BiosThunk\Keyboard\Dxe
Csm\BiosThunk\Snp16\Dxe
Csm\BiosThunk\BlockIo\Dxe
UEFI / Framework Training 2008
Copyright © 2006-2008 Intel Corporation
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Slide 59
Platform specific porting features
CSM Drivers Cont’d
• Legacy Interrupt (PIRQ registers)
– Chipset\IntelIch\LegacyInterrupt\Dxe\LegacyInterru
pt.c
• Legacy Region (shadow regions)
– Chipset\<Vendor>\LegacyRegion\Dxe\LegacyRegi
on.c
• Legacy BIOS Platform
– Platform\<Vendor>\<Platform>\Dxe\LegacyBiosPla
tform\
LegacyBiosPlatform.c
– Functions to prepare different tables (Option ROM
services, etc.)
®
UEFI / Framework Training 2008
Copyright © 2006-2008 Intel Corporation
•Other trademarks and brands are the property of their respective owners
Slide 60
Platform specific porting features
Add SMM support to DXE
• Base Protocol
– Responsible for Processor state (in SMM)
initialization and allocates SMM Memory
– Cpu\<Processor>Base\Smm\SmmBase.inf
• Access Protocol
– Controls the visibility of the SMRAM on the platform
– Chipset\<Vendor>\SmmAccess\Dxe\SmmAccess.inf
• Control Protocol
– Initiate SMI/PMI activations
– Chipset\IntelIch\IchX\SmmControl\Dxe\SmmControl.i
nf
®
UEFI / Framework Training 2008
Copyright © 2006-2008 Intel Corporation
•Other trademarks and brands are the property of their respective owners
Slide 61
Platform specific porting features
ACPI Support
• Provides ACPI support for a platform
– Builds FADT table from built AML tables
– Allows platform customization (APIC, GV3, OEMID)
– Updates EFI System Table with ACPI table pointers
• Composed of two drivers:
– ACPI Support Driver (generic)
– ACPI Platform Driver (platform specific)
• Platform Driver runs during DXE phase (before BDS)
• ScriptSave driver
– DXE drivers call ScriptSave protocol to save the chipset and
CPU configuration at normal boot path
– The boot script engine in PEIM restores the chipset and CPU
configuration done in previous DXE in S3 resume boot path
– Universal\Acpi\BootScriptSave\Dxe\ScriptSave.inf
®
UEFI / Framework Training 2008
Copyright © 2006-2008 Intel Corporation
•Other trademarks and brands are the property of their respective owners
Slide 62
Platform specific porting features
Add ACPI support to DXE
• ACPI tables
– Platform\<Vendor>\Dxe\AcpiTables
• ASL code
– Platform\<Vendor>\Dxe\AcpiTables\Asl\*.asi
• Update Platform Driver for platform specifics
– Platform\<Vendor>\<Platform>\Dxe\AcpiPlatform\Acpi
Platform.c
®
UEFI / Framework Training 2008
Copyright © 2006-2008 Intel Corporation
•Other trademarks and brands are the property of their respective owners
Slide 63
Platform specific porting features
EFI S3 path
Normal Boot
SEC
PEI
DXE
BDS
OS Boot
Save
Non-volatile
Storage (NVS)
S3 Resume
®
SEC
Resume Script
Table in ACPI
NVS
Retrieve
Execute
S3 aware
PEIMs restore
PEI Phase
configuration
Boot Script
PEIM restores
DXE phase
configuration
S3 Waking Vector
UEFI / Framework Training 2008
Copyright © 2006-2008 Intel Corporation
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Slide 64
Platform specific porting features
Add S3 Support to DXE
• Architectural Protocol
– Universal\Acpi\AcpiS3Save\Dxe
– Universal\Acpi\S3Resume\Pei
• Platform dependent Protocol
– Platform\<Vendor>\Smm\IchS3
Save
®
UEFI / Framework Training 2008
Copyright © 2006-2008 Intel Corporation
•Other trademarks and brands are the property of their respective owners
Slide 65
Platform specific porting features
BDS Driver
• BDS driver
– Edk\Sample\Platform\Generic\Dxe\PlatformBds
• Connecting Consoles/Changing Platform
Policy
– Platform\<Vendor>\<Platform>\PlatformBds\Dxe\Bd
sPlatform.c
• Language
– Platform\Generic\Dxe\Bds\*.uni
• Memory Test
Framework Designed to be Ported
®
UEFI / Framework Training 2008
Copyright © 2006-2008 Intel Corporation
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Slide 66
Summary
• Minimal porting effort for running EFI Shell.
• Incrementally add platform specific
features.
• Modularity of drivers allows easy
integration.
• Legacy BIOS experience is still useful with
the Framework.
• Framework knowledge easily transfers to
other architectures.
®
UEFI / Framework Training 2008
Copyright © 2006-2008 Intel Corporation
•Other trademarks and brands are the property of their respective owners
Slide 67
Further Information
• Documents Directory on CD
– Framework Mini PortingGuide
– FrameworkTechPortingRef
– FrameworkPortingList
®
UEFI / Framework Training 2008
Copyright © 2006-2008 Intel Corporation
•Other trademarks and brands are the property of their respective owners
Slide 68