Transcript DSP Implementation on FPGA

DSP Implementation on FPGA
Ahmed Elhossini
ENGG*6090 : Reconfigurable Computing
Systems
Winter 2006
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References
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Reconfigurable Computing for Digital Signal Processing: A Survey ,
RUSSELL TESSIER AND WAYNE BURLESON, Journal of VLSI Signal
Processing 28, 7–27, 2001
FPGA implementations of fast Fourier transforms for real-time
signal and image processing, I.S. Uzun, A. Amira and A. Bouridane ,
IEE Proc.-Vis. Image Signal Process., Vol. 152, No. 3, June 2005.
Image Processing Algorithms on Reconfigurable Architecture
using HandelC, V Muthukumar and Daggu Venkateshwar Rao,
Proceedings of the EUROMICRO Systems on Digital System Design
(DSD’04).
Experiences on developing computer vision hardware algorithms
using Xilinx system generator, Ana Toledo Moreo, Pedro Navarro
Lorente, F. Soto Valles, Juan Suardı´az Muro*, Carlos Ferna´ndez
Andre´s , Microprocessors and Microsystems 29 (2005) 411–419
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Introduction
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The application domain of digital signal processing over the past decade
expanded because of the advance in VLSI technology.
ASIC and programmable DSP processors was the implementation
mechanisms of choice for many DSP applications.
In the last few decades new system implementations based on
reconfigurable computing are being considered.
They offer the functional efficiency of hardware and the programmability
of software.
These flexible platforms are quickly maturing in logic capacity of
programmable devices and the availability of embedded modules
(Multipliers and Hard Cores).
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Architectural Requirements for DSP
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Data path configured for DSP
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Multiple memory banks and buses
Specialized addressing modes
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Fixed-point arithmetic
MAC- Multiply-accumulate
Bit-reversed addressing
Circular buffers
Specialized execution control
Specialized peripherals for DSP
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Choice Measures
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Performance.
Cost
Power
Flexibility
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DSP Implementation
DSP
Implementation
Pure HW
Implementation
ASIC
Hybrid HW/SW
Implementation
(HW/SW Codesign)
Reconfigurable
Devices
Soft or Hard core
Processor on
Reconfigurable
Device/Hardware
Accelerator
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Pure SW
Implementation
General Purpos
Processor
DSP processor/
Hardware
accelerator on
Reconfigurable
Device
DSP Processor
MicroBlaze
DSP Implementation on FPGA
Hard/Soft Core on
Reconfigurable
Device
PowerPC
Nios
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Topics Covered
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FFT Implementation of FPGA.
Image Processing Algorithms on Reconfigurable
Architecture using Handel-C.
Experiences on developing computer vision
hardware algorithms using Xilinx system
generator.
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Handle C
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Handel-C is essentially an extended
subset of the standard ANSI-C
language, specifically designed for use
in a hardware environment.
Unlike other C to FPGA tools Handel-C
allows hardware to be directly targeted
fromsoftware, allowing a more efficient
implementation to be created.
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Xilinx System Generator
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System Generator is a tool box added to
MATLAB simulink.
It allow a graphical representation of
the algorithm.
Includes many blocks that are
commonly used by DSP algorithms.
Allow converting directly to HDLs.
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FPGA implementations of fast
Fourier transforms for
real-time signal and image
processing
I.S. Uzun, A. Amira
A. Bouridane
IEE Proc.-Vis. Image Signal
Process., Vol. 152, No. 3, June
2005
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Target
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The design and implementation of a parametrisable architecture, which
provides a framework for the implementation of different types of 1-D FFT
algorithms.
The development of an FPGA-based FFT library by implementing radix-2,
radix-4, split-radix and FHT algorithms in order to provide system designers
and engineers with the flexibility to meet different system requirements (such
as chip area, memory etc.) with given hardware resources.
The evaluation and comparison of hardware implementations of
aforementioned FFT algorithms. The performance measures to be considered
in comparisons are the computation speed, maximum system frequency, chip
area and memory usage.
The design and implementation of a generic parallel 2-D FFT architecture for
real-time image processing applications for use to enhance large medical and
astronomical images using frequency-domain filtering techniques.
The development of an FPGA-based parametrisable system for frequencydomain filtering of large images.
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FFT Implementation on FPGA
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Implementing 4 Different Transforms
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Radix 2 FFT
Radix 4 FFT
Split Radix FFT
Fast Hartley transform
Introduce a parallel version of the 2D parallel FFT
transform based on Radix 2 and Radix 4.
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Make use of more FFT processing elements to perform
computation.
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Proposed system for FFT
implementation
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Butter-Fly Used With Different
Architectures
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Functional block diagram of 1-D
FFT processor architecture
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Block diagram of radix-2 butterfly
used in FPGA FFT processor
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Architectural block diagram of AGU
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Computation time (us) of different
algorithms for 1024 point FFT
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Functional block diagram of parallel
2-D FFT processor architecture
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Computation time and Device utilization
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2-D FFT performance comparison
with existing FPGA-based designs
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Conclusion
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This work introduces an implementation
platform for FFT Transforms.
Handle-C is used as the description
language.
A comparison of this implementation
shows a lower execution time with a
reasonable resource utilization.
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Image Processing Algorithms
on Reconfigurable Architecture
using HandelC
V Muthukumar and Daggu
Venkateshwar Rao
Proceedings of the EUROMICRO Systems on Digital
System Design (DSD’04)
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Target
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In this work the canny edge detection architecture for 2D
images has been developed using reconfigurable
architecture and hardware modeled using Handle-C.
The algorithm involve the implementation of different
image processing algorithms such as:
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First the image is smoothed by Gaussian Convolution which is 5x5
convolution operation.
Morphological Operation, which is 3x3 operator on the image.
2D convolution.
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Implementation
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The algorithm is modeled using Handle-C.
It is implemented using the EDK2 and
RC1000-PP XilinxVertex-E FPGA. This chip
doesn’t have any embedded multiplier.
The hardware implementation is compared to
a software implementation using a PC with
pentium processor at 1300MHz Frequancy.
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Architecture of 3x3 moving
window
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Edge Detection Architecture
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Results
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Results
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Conclusion
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Handle C is used to implement 2D
convolution which is used to implement
edge detection.
The implementation is compared to
VC++ implementation on P3 1300MHz
processer, and shows a better
performance.
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Experiences on developing computer vision
hardware algorithms using Xilinx system
generator
Ana Toledo Moreo, Pedro Navarro Lorente, F.
Soto Valles,
Juan Suardı´az Muro*, Carlos Ferna´ndez
Andre´s
Microprocessors and Microsystems 29 (2005)
411–419
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Target
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This paper shows how the Xilinx system
generator (XSG) environment can be
used to develop hardware-based
computer vision algorithms from a
system level approach, which makes it
suitable for developing co-design
environments.
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Application Examples
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Binarization algorithm
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Converting a gray scale image into a black and
white binary image.
Xilinx System Generator is used to implement this
unit.
Compared with a VHDL implementation.
Generalized convolution blocks
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Convolution is one of the basic image processing
algorithms.
Xilinx System Generator is used to implement
different type of algorithms.
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Modular-blockset-based
hardware binarization block
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VHDL-based hardware
binarization block
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Hardware convolution block
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Hardware binarization block
implementation results
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Generalized hardware convolution
implementation results
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Results
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Conclusion
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This work demonstrate the use of Xilinx
System Generator to implement Image
processing algorithm.
A comparison is made to the VHDL
implementation and show a competitive
results.
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Results
System
FPGA
Tool
Alternative
Implementation
Main
Algorithn
FPGA implementations of fast
Fourier transforms for real-time
signal and image processing
Xilinx
XCV2000E
RC1000-PP
Board
Handle C with
EDK2
Comparison with
Different
implementations
4 FFT
algorithms
Image Processing Algorithms on
Reconfigurable Architecture
using HandelC
Xilinx
XCV2000E
RC1000-PP
Board
Handle C with
EDK2
VC++ Program
on P3 1300 MHZ
processor
2D
Convulsion
and Edge
Detection
Experiences on developing
computer vision hardware
algorithms using Xilinx system
generator
Xilinx
XCV800
Xilinx System
Generator
VHDL
Binarization
and 2D
convulsion
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Conclusion
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In this review 3 different papers on implementing
DSP algorithms on FPGA are demonstrated.
Handle C is an efficient tool to implement DSP
algorithms and provide a competitive result to those
of current HDLs.
Xilinx System Generator , which is tool based on
MathWorks MATLAB, is an good tool to implement
DSP systems.
Modern tools for implementing DSP algorithms could
be used to replace the current HDLs.
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Thank You
Questions ?
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