Transcript Sistem Digital A - Gunadarma University

Kuliah Rangkaian Digital
Kuliah 6: Blok Pembangun Logika
Kombinasional
Teknik Komputer
Universitas Gunadarma
Topic #6 – Combinational Logic Building
Blocks
Tri-state buffers
XOR & XNOR
Decoders
Encoders
Multiplexers
Demultiplexers
Tri/Three-state buffers
Outputs: 0, 1, or Hi-Z (high impedance)
CMOS transmission gate

Hi-Z  Don’t care
Can tie multiple outputs together  one at a time is driven
EN
A
A·EN’+B·EN
B
2-input XOR gates
True if and only if the two inputs are different
XNOR: complement of XOR
May be used as comparator
XOR and XNOR symbols
Why are they equivalent?
Gate-level XOR circuits
Can we make it using only NAND gates?
CMOS XOR with transmission gates
IF B==1 THEN Z = !A;
ELSE Z = A;
Multi-input XOR?



What is X  Y  Z = ?
X’ · Y · Z + X · Y’ · Z + X · Y · Z’ + X’ · Y’ · Z’
 TRUE if odd number of inputs are TRUE
Associativity for XOR, just like AND & OR?
Parity computation – to detect single bit error
Parity tree
Faster with balanced tree structure
Decoders
Convert m-bit coded inputs into n-bit outputs


Typically m<n
E.g., n-to-2n, BCD decoders
Enable: prevent changes in output due to undesired
changes in input
BCD decoder
4-bit input indicates the
number to display, and thus
control the on/off of the 7
segments.
Recall K-map minimization
with Don’t cares …
a
f
e
b
g
d
c
EN D
0
x
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
x
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B
x
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
a
0
1
0
1
1
0
1
0
1
1
1
x
x
x
x
x
x
b
0
1
1
1
1
1
0
0
1
1
1
x
x
x
x
x
x
c
0
1
1
0
1
1
1
1
1
1
1
x
x
x
x
x
x
d
0
1
0
1
1
0
1
1
0
1
0
x
x
x
x
x
x
e
0
1
0
1
0
0
0
1
0
1
0
x
x
x
x
x
x
f g
0 0
1 0
0 0
0 1
0 1
1 1
1 1
1 1
0 0
1 1
1 1
x x
x x
x x
x x
x x
x x
Binary n-to-2n decoders
The kth output is 1 if the n-bit input has binary value of k
Ex: 2-to-4 decoder
2-to-4-decoder logic diagram
3-to-8 binary decoders
x
0
0
0
0
1
1
1
1
y
0
0
1
1
0
0
1
1
z F0
0 1
1 0
0 0
1 0
0 0
1 0
0 0
1 0
F1
0
1
0
0
0
0
0
0
F2
0
0
1
0
0
0
0
0
F3
0
0
0
1
0
0
0
0
F4
0
0
0
0
1
0
0
0
F5
0
0
0
0
0
1
0
0
F6
0
0
0
0
0
0
1
0
F0 = x'y'z'
F7
0
0
0
0
0
0
0
1
F1 = x'y'z
F2 = x'yz'
F3 = x'yz
F4 = xy'z'
F5 = xy'z
F0
X
Y
Z
F6 = xyz'
F1
3-to-8
Decoder
F2
F7 = xyz
F3
F4
F5
F6
F7
x
y
z
Realizing digital logic using decoders
Idea:

Canonical sum (of minterms) = decoder outputs connect to OR gate
Good and simple implementation when the circuit has many outputs
each has few minterms
Example: Full adder


S(Cin, A, B) = S (1,2,4,7)
C(Cin, A, B) = S (3,5,6,7)
3-to-8 0
Decoder 1
Cin
S2
A
S1
B
S0
2
3
4
5
6
7
S
C
Cin A
B
C
S
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
1
1
0
0
1
1
Encoders (vs. decoders)
m inputs, n outputs, m>n
Ex: 2n–to-n binary
encoder
Decoder
Encoder
8-to-3 encoder example
Inputs
I0
1
0
0
0
0
0
0
0
I1
0
1
0
0
0
0
0
0
I2
0
0
1
0
0
0
0
0
I3
0
0
0
1
0
0
0
0
I4
0
0
0
0
1
0
0
0
Outputs
I5
0
0
0
0
0
1
0
0
I6
0
0
0
0
0
0
1
0
I7
0
0
0
0
0
0
0
1
y2
0
0
0
0
1
1
1
1
y1
0
0
1
1
0
0
1
1
y2
0
1
0
1
0
1
0
1
I0
I1
Y2 = I4 + I5 + I6 + I7
I2
I3
y 1 = I2 + I 3 + I6 + I7
I4
I5
I6
I7
Y0 = I1 + I3 + I5 + I7
What if all Ik=0?
Multiplexers
Digital switches that select
one of the n b-bit data as
the output
2-input multiplexer using CMOS
transmission gates
4-to-1 multiplexer
I0
d0
d0
d0
d0
I1
d1
d1
d1
d1
I2
d2
d2
d2
d2
I3
d3
d3
d3
d3
S1
0
0
1
1
S0
0
1
0
1
Y
d0
d1
d2
d3
Inputs
I0
I1
I2
I3
S1
0
0
1
1
S0
0
1
0
1
Y
I0
I1
I2
I3
Inputs
0
4:1
1
MUX
Y
2
3
S1 S0
I0
I1
Output
I2
mux
I3
S1 S0
select
select
Y
4-to-1 Mux circuit diagram
I0
I0
I1
I1
Y
I2
Y
I2
I3
I3
0 1 2 3
2-to-4
Decoder
S1 S0
S1
S0
Larger multiplexers
Can be constructed using smaller ones …
Ex: 8=to-1 Mux
I0
I1
I2
I3
4:1
MUX
S1 S0
I4
I5
I6
I7
4:1
MUX
S1 S0
2:1
MUX
S2
Y
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Y
I0
I1
I2
I3
I4
I5
I6
I7
16-to-1 multiplexer
MSI multiplexer example
74151A 8-to-1 multiplexer
Demultiplexers
Digital switches that connect the input to one of n outputs
Typically n = 2s
b bits
Inputs
Data
Input
Output
Mux
Select
Demux
s bits
Select
.
.
b bits
n outputs
b bits
1-to-4 demultiplexer
Outputs
Y0 = D·S1'·S0'
Y1 = D·S1'·S0
Data D
Demux
Y2 = D.S1·S0'
Y3 = D.S1·S0
S1 So
0 0
0 1
1 0
1 1
Y0
D
0
0
0
Y1
0
D
0
0
Y2
0
0
D
0
Y3
0
0
0
D
S1 S0
select
Implementing n-output
b-bit Demux using b noutput Decoders


Connecting data bits to
enables
Can we do it for Mux
using Encoder?
Y0 = D·S1'·S0'
S1
2x4
Decoder
S0
Y1 = D·S1'·S0
Y2 = D·S1·S0'
E
D
Y3 = D·S1·S0
Mux-Demux application example
Enables number of sources and destinations sharing a
single communication channel
Implementing n-variable func. using 2n-to-1
Mux
Methodology:



Express function in canonical sum form
Connect the n input variables to the Mux select lines,
For each Mux data input line Ii ( 0  i 2n – 1 ):
Connect 1 to Ii if i is a minterm of the function,
Otherwise, connect 0 to Ii.
Ex: F(X,Y,Z) = S(1,3,5,6)
0
1
0
Mux Data 1
Input Lines 0
1
1
0
0
1
2
3
mux
4
5
6
7
X Y Z
F
Mux Select Lines
Implementing n-variable func. using 2n-1-to1 Mux
Idea:


Use only n-1 variables at the select lines
Connect the last one and its inverse to the input lines
Ex: F(X,Y,Z) = S(0,1,3,6)
Value
of X·Y
0
1
2
3
X
Y
Z
F
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
1
0
Mux
Output
Mux Data
Input Lines
1
1
Z
Z
0
Z’
0
1
0
2
Mux
3
F
Mux Select Lines
X Y
Another example
F(x1,x2,x3,x4) = (0,1,2,3,4,9,13,14,15) using a 8-to-1
Mux (74151A) and an inverter.
Implementing n-variable func. using 2n-1-to1 Mux
1. Express function F in canonical sum form
2. Choose n-1 variables connecting to mux select lines
3. Construct the truth table via grouping inputs based
on select line values
4. Determine multiplexer input line i values by
comparing the last input variable X and F:

Four possible mux input line i values:
0 if F=0 regardless of the value of X
1 if F=1 regardless of the value of X
F=X
F=X’