Transcript EECT 7327 – Data Converters – University of Texas at

Data Converters
EECT 7327
Flash ADC
Flash ADC
–1–
Professor Y. Chiu
Fall 2014
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Flash ADC Architecture
Vi
VFS
Vi
Strobe
VFS
•
Reference ladder
consists of 2N equal
size resistors
•
Input is compared
to 2N-1 reference
voltages
•
Massive parallelism
•
Very fast ADC
architecture
•
Throughput = fs
•
Latency = 1 T = 1/fs
•
Complexity = 2N
fs
7
7Δ
6
…
5Δ
…
…
…
…
5
Encoder
6Δ
2Δ
Dout
1
Δ
0
Do
0
N
2 -1
comparators
–2–
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Thermometer Code
VFS
Vi
Thermometer code
Strobe
b2
b1
b0
0
110
…
1
1
1
1
…
1
111
…
1
…
0
…
…
…
fs
010
001
000
N
2 -1
comparators
1-of-n code
ROM encoder
–3–
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Flash ADC Challenges
1mV
1V
σ
•
VDD = 1.8 V
•
10-bit
→ 1023 comparators
•
VFS = 1 V
→ 1 LSB = 1 mV
•
DNL < 0.5 LSB
→ Vos < 0.5 LSB
•
0.5 mV = 3-5 σ
→ σ = 0.1-0.2 mV
•
2N-1 very large comparators
•
Large area, large power consumption
•
Very sensitive design
•
Limited to resolutions of 4-8 bits
–4–
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Flash ADC Challenges
128
Vos, max [mV]
32
VFS = 2V
8
VFS = 1V
2
0.5
4
6
8
N [bits]
10
–5–
•
DNL < 0.5 LSB
•
Large VFS relaxes
offset tolerance
•
Small VFS benefits
conversion speed
(settling, linearity of
building blocks)
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
A Typical CMOS Comparator
VDD
Vos derives from:
M3 M4
M5
M6
Φ
Vos
M1 M2
Vo
+
Vi
V oM9
M7
M8
VSS
Preamp
Latch
–6–
•
Preamp input pair
mismatch (Vth,W,L)
•
PMOS loads and
current mirror
•
Latch mismatch
•
CI / CF imbalance
of M9
•
Clock routing
•
Parasitics
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Latch Regeneration
VDD
M5
Vo
M6
Φ
+
Φ
M7
VDD
Vo-
M9
CL
PA tracking
Latch
Latch reseting regenrating
Vo+
CL
Vo
M8
VoVSS
VSS
Exponential regeneration due to positive feedback of M7 and M8
–7–
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Regeneration Speed – Linear Model
Vo+
Vo+
Vo-
CL
CL
M7

CL
-1
gmVo-
M8



 Vo   Vo
 


V


g

V
m
o /sCL
 o
Vo-
1  Vo  
1
    0
 


1 gm /sCL  Vo 
Δs  gm/sCL 1  0  sp  gm/CL , single RHP pole
Vo t  0  Vo t  0 expt  gm /CL 
–8–
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Reg. Speed – Linear Model
Vo+
Vo-
CL
CL
M7
Vo(t=0)
M8
Vo
Vo(t=0)
t/(CL/gm)
1V
100mV
2.3
1V
10mV
4.6
1V
1mV
6.9
1V
100μV
9.2
t
–9–
t
Vo = 1V
CL  Vo t  
 ln

gm  Vo t  0  
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Reg. Speed – Linear Model
Vm+
M3 M4
Vm+
M5
V mM1 M2
x
Vo
+
Vi
Vm-
M6
Φ=1
Vo-
gm5Vm+

Vo+
M9
gm1
gm3
M8
A V2 
R9
2
R9
2
Vo-
X
M7
A V1 
gm5Vm-
-1
gm7
-1
gm7
gm5R9
R9
1
,

to be amplifier.
2  gm7R9
2 gm7
Vo 0  Vi 0 A V  Vi 0 A V1A V2
Vo t   Vi 0 A V1A V2  expt  gm/CL 
– 10 –
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Comparator Metastability
T/2
Φ
Vo t   Vi 0 A V1A V2  expt  gm/CL 
Curve
AV1AV2
Vi(t=0)

10
10 mV
Vo+

10
1 mV
Vo-

10
100 μV

10
10 μV
1 2 3 4
Comparator fails to produce valid logic outputs within T/2 when input falls
into a region that is sufficiently close to the comparator threshold
– 11 –
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Comparator Metastability
Do
Δ
Assuming that the input is uniformly
distributed over VFS, then
j+1
Vi
j
Δ
BER 
1LSB
Vo t   Vi 0 A V1A V2  expt  gm/CL 
Vos
•
Cascade preamp stages (typical flash comparator has 2-3 PA stages)
•
Use pipelined multi-stage latches; PA can be pipelined too
•
Avoid branching off comparator logic outputs
– 12 –
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Comparator Metastability
Vi
1
1
1
0
x
0
1
0
100
011
Logic levels can be misinterpreted by digital gates (branching off, diff. outputs)
– even a wrong decision is better than no decision!
– 13 –
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
CI and CF in Latch
M5
Vo+
Φ
Cgs
Φ
M6
Cgd
Vo-
M9
CL
M7
CL
CM
jump
M8
Vo+
Vo-
•
Charge injection and clock feedthrough introduce CM jump in Vo+ and Vo-
•
Dynamic latches are more susceptible to CI and CF errors
– 14 –
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Dynamic Offset of Latch
Dynamic offset derives from:
Φ
Vo
+
Vo-
•
Imbalanced CI and CF
•
Imbalanced load capacitance
•
Mismatch b/t M7 and M8
•
Mismatch b/t M5 and M6
•
Clock routing
0.5V CM jump 
  50mV offset
10% imbalance 
Dynamic offset is usually the dominant offset error in latches
– 15 –
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Typical CMOS Comparator
VDD
M3 M4
M5
M1 M2
Vo
+
Vi
Input-referred latch
offset gets divided by
the gain of PA
•
Preamp introduces
its own offset (mostly
static due to Vth, W,
and L mismatches)
•
PA also reduces
kickback noise
M6
Φ
Vos
•
V oM9
M7
M8
VSS
Preamp
Latch
Kickback noise disturbs reference voltages, must settle before next sample
– 16 –
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Comparator Offset
VDD
M3 M4
M5
Differential pair mismatch:
M6
Φ
Vos
M1 M2
Vo
+
Vi
Vo
Vos  ΔVth 
2
-
2
M9
M7
M8
A V1 
VSS
Preamp
Total input-referred
comparator offset:
2
2

1
 ΔL  
2  ΔW 
 Vov 
 
 
4
W
L



 

gm1
gm3
A V2 
gm5R9
2  gm7R9
Latch
Vos,34  Vos,56
2
Vos  Vos,12 
2
2
– 17 –
A
2
V1
2

Vos,78
A
2
V1
2
A V2
2

Vos, dyn
2
2
A V1 A V2
2
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Matching Properties
Suppose parameter P of two rectangular devices has a mismatch error of ΔP.
The variance of parameter ΔP b/t the two devices is
2
A
2
σ ΔP  P  SP D2 ,
WL
2
1st term dominates
for small devices
where, W and L are the effective width and length, D is the distance
A Vth2
Threshold : σ  Vth  =
+ SVth2D2
WL
σ 2 β  Aβ2
Current factor :

 Sβ2D2
2
β
WL
2
Ref: M. J. M. Pelgrom, et al., “Matching properties of MOS transistors,” IEEE Journal
of Solid-State Circuits, vol. 24, pp. 1433-1439, issue 5, 1989.
– 18 –
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Why Large Devices Match Better?
R1
W
X
R2
X
X
X
X
L
R1  RS 
L
with std σR1
W
X
…
X
X
10 identical resistors
 L 
R2  RS 10    10R1 with std σR2 ,
W
10
σR2   σR j 2  10σR12  σR2  10σR1
2
j1
σR2
10σR1
σR
1  σR1 
1
1







R2
10R1
R
10  R1 
A
WL
– 19 –
“Spatial
averaging”
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
ADC Input Capacitance
A Vth2
σ  Vth  
WL
Cg  10 fF / μm2
2
•
N = 6 bits
→ 63 comparators
•
VFS = 1 V
→ 1 LSB = 16 mV
•
σ = LSB/4
→ σ = 4 mV
•
AVT0 = 10 mV·μm
→ L = 0.24 μm,
W = 26 μm
N (bits)
# of comp.
Cin (pF)
6
63
3.9
8
255
250
10
1023
??!
•
Small Vos leads to large device sizes, hence large area and power
•
Large comparator leads to large input capacitance, difficult to drive and
difficult to maintain tracking bandwidth
– 20 –
Data Converters
EECT 7327
Flash ADC
Flash ADC Errors
– 21 –
Professor Y. Chiu
Fall 2014
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Distributed Parallel Processing
Vi
VFS
Vi
Strobe
VFS
• SHA-less
fs
• Signal and
clock propagation delay
7
7Δ
6
…
…
5Δ
…
…
…
…
5
2Δ
Dout
• 2N-1 PAs +
latches must
be matched
• Synchronized
strobe signal
is critical
1
Δ
0
Do
Encoder
6Δ
0
2N-1
PA + Latch
Going parallel is fast, but also gives rise to inherent problems…
– 22 –
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Preamp Input Common Mode
PA 1
…
PA j
…
S1
Vi
VR1
PA j+1
…
Sj
…
…
VRj
VR  VR
1
j
Input CM difference creates systematic mismatch (offset, gain, Cin,
tracking BW, and CMRR) among preamps
– 23 –
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Sampling Aperture Error
M3
M4
Cgd1
RS
Cgs1
VR
M2
V o+
Cgs2
CS
M6
Φ
Cgd2
M1
Vin
M5
M7
Vo-
M9
Φ
Mode
“high”
Track
“low”
Regen
M8
•
Preamp delay and Vth of sampling switch (M9) are both signal-dependent
→ signal-dependent sampling point (aperture error)
•
A major challenge of distributing clock signals across 2N-1 comparators in
flash ADC with minimum clock skew (routing, Vth mismatch of M9, etc.)
– 24 –
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Nonlinear Input Capacitance
RS
Vout
Vin
Vin,
Vout
Cin(Vout)
t
Signal-dependent input bandwidth (1/RSCin) introduces distortion
– 25 –
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Input Signal Feedthrough
…
Vi
Vin
M3
M4
M1
M2
VRj
RS
Cgs2
…
Cgs1
Feedthrough of Vin to the reference ladder through the serial connection of
Cgs1 and Cgs2 disturbs the reference voltages
– 26 –
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Fully-Differential Architecture
Vi+ Vi-
– 27 –
Encoder
…
Latch
…
…
…
…
…
…
PA
…
VR+ VR-
•
VFS doubled
•
3-dB gain in SNR
•
Better CMRR
•
Noise immunity
•
Input feedthrough
cancelled
•
Cin nonlinearity
partially removed
•
Effect of Vcmi diff.
mitigated
Dout
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Fully-Differential Comparator
M5 M6
M7
M1 M2
Vi+
Φ
M8
M3 M4
VR+ VR-
Φ
Vo+
Vi-
Fully-diff. PA
M9
Vo-
Latch
•
Double-balanced, fully-differential preamp
•
Switches (M7, M8) added to stop input propagation during regeneration
•
Active pull-up PMOS added to the latch
– 28 –
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
AC-Coupled Preamp
Vi
Φ
Φ
C
VR
Latch
X
PA
Φ
•
PA input node X sees constant bias throughout all preamps
•
Autozeroing eliminates PA offsets (stored in C)
Ref: A. G. F. Dingwall, “Monolithic expandable 6 bit 20 MHz CMOS/SOS A/D converter,”
IEEE Journal of Solid-State Circuits, vol. 14, pp. 926-932, issue 6, 1979.
– 29 –
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Bubbles (Sparkles)
1
1
0
0
1
0
0
1
1
0
100
011
010
…
…
Vi
Static/dynamic comparator errors cause bubbles in thermometer code
– 30 –
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Bubbles (Sparkles)
…
Vi
Vj+1
0
VRj+1
VRj+1
1
1 LSB
j+1
Vj
0
VRj
j
1
t
…
VR
j
Δt
Comparator offset
Timing error
– 31 –
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Bubble-Tolerant Boundary Detector
…
Vi
0
1
0
1
…
1
1
1
0
1
•
3-input NAND
•
Detect “011” instead
of “01” only
•
“Single” bubble
correction
•
Biased correction
1
Ref: J. G. Peterson, “A monolithic video A/D converter,” IEEE Journal of Solid-State
Circuits, vol. 14, pp. 932-937, issue 6, 1979.
– 32 –
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Built-In Bias
1
2
3
A
B
C
D
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
1
1
0
1
1
0
0
1
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
Case
“011”
Det.
“001”
Det.
A


B
Fail

C

Fail
D
Fail
Fail
Inspecting more neighboring comparator outputs improves performance
– 33 –
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Majority Voting
C j  C j1C j  C jC j1  C j1C j1
*
A
1
2
3
0
0
0
0
1
0
1
1
1
1
B
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
0
1
1
C
0
0
0
0
0
1
1
1
1
1
0
0
1
0
0
1
1
1
1
1
D
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
0
0
1
1
0
0
1
1
1
Case
“011”
Det.
Majority
voting
A


B
Fail

C


D
Fail
Fail
Ref: C. W. Mangelsdorf, “A 400-MHz input flash converter with error correction,” IEEE
Journal of Solid-State Circuits, vol. 25, pp. 184-191, issue 1, 1990.
– 34 –
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Gray Encoding
G1  T1 T3  T5 T7
G2  T2 T6
G3  T4
Only one transition
b/t adjacent codes
Thermometer
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
Gray
0
0
0
0
0
0
0
1
T1 T2 T3 T4 T5 T6 T7
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
Binary
0
1
1
0
0
1
1
0
G3 G2 G1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
B3 B2 B1
•
One comparator output is ONLY used once → No branching!
•
Gray encoding fails benignly in the presence of bubbles
•
Codes are also robust over metastability errors
– 35 –
Data Converters
EECT 7327
Flash ADC
Professor Y. Chiu
Fall 2014
Gray Encoding
Thermometer
Gray
1 1 1 1 1 1 1 1 1 1 1 1 1 0 0
1 1 1 1 1 1 1 1 1 1 1 1 0 1 0
1 1 1 1 1 1 1 1 1 1 1 1 0 0 1
G1  T1 T3  T5 T7
G2  T2 T6
G3  T4
1 0 1 1
1 0 0 0
1 0 1 0
Decimal
13
15
12
Conversion of Gray code to binary code is quite
time-consuming → “quasi” Gray code
Ref: Y. Akazawa, et al., “A 400MSPS 8b flash AD conversion LSI,” in IEEE
International Solid-State Circuits Conference, Dig. Tech. Papers, 1987, pp. 98-99.
– 36 –