Transcript Chapter #6: Sequential Logic Design Contemporary Logic

Course: Logic Design
Topic: Sequential Circuit
Chapter #6:
Sequential Logic Design
Slide no. 1
Course: Logic Design
Topic: Sequential Circuit
Chapter Overview
• Sequential Networks
Simple Circuits with Feedback
R-S Latch
J-K Flipflop
Edge-Triggered Flipflops
• Realizing Circuits with Flipflops
Choosing a FF Type
Characteristic Equations
Conversion Among Types
• Metastability and Asynchronous Inputs
Slide no. 2
Course: Logic Design
Topic: Sequential Circuit
Sequential Switching Networks
Definition of Terms
Tsu
Th
Input
Cloc k
There is a timing
"window" around the
clocking event
during which the input
must remain stable
and unchanged
in order
to be recognized
Clock:
Periodic Event, causes state of memory
element to change
rising edge, falling edge, high level, low level
Setup Time (Tsu)
Minimum time before the clocking event by
which the input must be stable
Hold Time (Th)
Minimum time after the clocking event during
which the input must remain stable
Slide no. 3
Course: Logic Design
Topic: Sequential Circuit
Sequential Switching Networks
Cross-Coupled NOR Gates
R
Q
R
S
S
\Q
Timing Waveform
Reset
Hold
Set
Reset
Set
100
R
S
Q
\Q
Forbidden
State
Slide no. 4
Forbidden
State
Race
Course: Logic Design
Topic: Sequential Circuit
Sequential Switching Networks
State Behavior of R-S Latch
S R
Q
0 0
hold
0 1
0
1 0
1
1 1 uns table
Truth Table Summary
of R-S Latch Behavior
Slide no. 5
Course: Logic Design
Topic: Sequential Circuit
Sequential Switching Elements
R-S Latch
Truth Table:
Next State = F(S, R, Current State)
Derived K-Map:
S
SR
S(t) R(t) Q(t)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Q(t+)
00
01
11
10
0
0
0
X
1
1
1
0
X
1
Q( t )
0 (hold)
1 (Hold)
0 (reset)
0 (reset)
1 (set)
1 (set)
Not allowed
Not allowed
R
Characteristic Equation:
Q+ = S + R Q t
S
R
R-S
Latch
Q+
Q
Slide no. 6
Course: Logic Design
Topic: Sequential Circuit
Sequential Switching Networks
J-K Latch
J, K both one yields toggle
J(t) K(t) Q(t)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Q(t+)
J
Q
K
\Q
J-K Latch
0 (hold)
1 (Hold)
0 (reset)
0 (reset)
1 (set)
1 (set)
1 (toggle)
0 (toggle)
Characteristic Equation:
Q+ = Q K + Q J
Slide no. 7
Course: Logic Design
Topic: Sequential Circuit
Sequential Switching Networks
J-K Latch: Race Condition
Set
Reset
100
Toggle
J
K
Q
\Q
Race Condition
Slide no. 8
Course: Logic Design
Topic: Sequential Circuit
Sequential Switching Networks
D-FlipFlop
Edge triggered device sample inputs on the event
edge
7474
D
Q
Clk
Positive edge-triggered
flip-flop
Bubble here
for negative
edge triggered
device
Slide no. 9
Course: Logic Design
Topic: Sequential Circuit
Sequential Switching Networks
Positive vs. Negative Edge Triggered Devices
100
D
Clk
Qpos
Pos iti ve edgetri ggered FF
\ Qpos
Qneg
Negative edgetri ggered FF
\ Qneg
Positive Edge Triggered
Negative Edge Triggered
Inputs sampled on rising edge
Outputs change after rising edge
Inputs sampled on falling edge
Outputs change after falling edge
Toggle Flipflop
Formed from J-K with both inputs wired together
Slide no. 10
Course: Logic Design
Topic: Sequential Circuit
Timing Methodologies
Cascaded Flipflops and Setup/Hold/Propagation Delays
Shift Register
S,R are preset, preclear
New value to first stage
while second stage
obtains current value
of first stage
IN
D
Q
C Q
Q0
D
C Q
CLK
100
In
Correct Operation,
assuming positive
edge triggered FF
Q0
Q1
Clk
Slide no. 11
Q
Q1
Course: Logic Design
Topic: Sequential Circuit
D-latch and D-Flipflop
D
Q
Clk
Pos itive edge-tri ggered
fl ip-flop
D
Q
C
Transparent latches sample
inputs as long as the clock
is asserted
Clk
Level-s ensi tive
latc h
Example: to be done during the class
Slide no. 12
Course: Logic Design
Topic: Sequential Circuit
Realizing Circuits with Different Kinds of FFs
Choosing a Flipflop
R-S Clocked Latch:
used as storage element in narrow width clocked systems
its use is not recommended!
however, fundamental building block of other flipflop types
J-K Flipflop:
versatile building block
can be used to implement D and T FFs
usually requires least amount of logic to implement ƒ(In,Q,Q+)
but has two inputs with increased wiring complexity
D Flipflop:
minimizes wires, much preferred in VLSI technologies
simplest design technique
best choice for storage registers
T Flipflops:
don't really exist, constructed from J-K FFs
usually best choice for implementing counters
Preset and Clear inputs highly desirable!!
Slide no. 13
Course: Logic Design
Topic: Sequential Circuit
Realizing Circuits with Different Kinds of Flipflops
Characteristic Equations
R-S:
Q+ = S + R Q
D:
Q+ = D
J-K:
Q+ = J Q + K Q
T:
Q+ = T Q + T Q
Derived from the K-maps
for Q+ = ƒ(Inputs, Q)
E.g., J=K=0, then Q+ = Q
J=1, K=0, then Q+ = 1
J=0, K=1, then Q+ = 0
J=1, K=1, then Q+ = Q
Implementing One FF in Terms of Another
D
J
C
K
Q
Q
Q
D implemented with J-K
Slide no. 14
Course: Logic Design
Topic: Sequential Circuit
Realizing Circuits with Different Kinds of Flipflops
Design Procedure
Excitation Tables: What are the necessary inputs to cause a
particular kind of change in state?
Q Q+
0 0
0 1
1 0
1 1
R
X
0
1
0
S
0
1
0
X
J
0
1
X
X
K
X
X
1
0
Slide no. 15
T
0
1
1
0
D
0
1
0
1
Course: Logic Design
Topic: Sequential Circuit
Metastability and Asynchronous Inputs
Terms and Definitions
Clocked synchronous circuits
• common reference signal called the clock
• state of the circuit changes in relation to this clock signal
Asynchronous circuits
• inputs, state, and outputs sampled or changed independent
of a common reference signal
R-S latch is asynchronous, J-K FF is synchronous
Synchronous inputs
• active only when the clock edge or level is active
Asynchronous inputs
• take effect immediately, without consideration of the clock
Slide no. 16
Course: Logic Design
Topic: Sequential Circuit
Metastability and Asynchronous Inputs
Asynchronous Inputs Are Dangerous!
Since they take effect immediately, glitches can be disastrous
Synchronous inputs are greatly preferred!
But sometimes, asynchronous inputs cannot be avoided
e.g., reset signal
Slide no. 17
Course: Logic Design
Topic: Sequential Circuit
Chapter Summary
• Fundamental Building Block of Circuits with State: latch and flipflop
• R-S Latch, J-K Flipflop, Edge-triggered D Flipflop
Slide no. 18