Transcript 슬라이드 1 - Yonsei

A 1.25-Gb/s Digitally-Controlled
Dual-Loop Clock and Data Recovery Circuit
with Improved Effective Phase Resolution
Chang-Kyung Seong1), Seung-Woo Lee2), and Woo-Young Choi1)
1)Department
of Electronic and Electrical Engineering
Yonsei University
2)Switching
Technology Team
Electronics and Telecommunications Research Institute
Contents



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

Introduction
Conventional Dual-Loop CDR and Problems
Proposed Dual-Loop CDR
Simulation and Experimental Results
Chip summary
Conclusion
High-Speed Circuits and Systems Lab. Yonsei Univ.
Introduction (1)

Multi-channel application (e.g. Switch)
 Dozens ~ Hundreds of CDRs integrated in single die

Requirements for CDR
 Small die area
 Low power consumption
 Robustness to noise coupled from adjacent blocks
SwitchCore
CoreLogics
Logics
Switch
Tx / Rx for each channel
High-Speed Circuits and Systems Lab. Yonsei Univ.
Introduction (2)

Dual-loop CDR
 Shared Reference PLL
 Each CDR cores using phase interpolator
• No jitter accumulation
• Digital control - no loop filter, robustness to noise
Data#3
Data#2
Data#1
CDR #2
CDR #1
Retimed Data #4
Recovered Clock #4
CDR #4
Data#4
CDR #3
Retimed Data #3
Recovered Clock #3
Retimed Data #2
Recovered Clock #2
Retimed Data #1
Recovered Clock #1
Synthesized Reference Clock
Pad
external reference clock
Ref. PLL
High-Speed Circuits and Systems Lab. Yonsei Univ.
Conventional Digitally-Controlled Dual-Loop Structure
External Reference Clock
PFD
CP
LF
VCO
/M
CDR core
Ref. PLL
Multi-Phase Reference Clock from PLL
Phase Selection
Two Selected Phases
Data in.
Bang-Bang
Phase Detector
Phase
Controller
Phase Interpolator
High-Speed Circuits and Systems Lab. Yonsei Univ.
Conventional Digitally-Controlled Dual-Loop Structure
External Reference Clock
PFD
CP
LF
VCO
/M
CDR core
Ref. PLL
Reference Clock from PLL
Phase Selection
Phase Selection
Two Selected Phases
Data in.
Bang-Bang
Phase
PhaseInterpolator
Detector
Phase
Controller
Phase Interpolator
Phase
Interpolated
High-Speed Circuits and Systems Lab. Yonsei Univ.
Conventional Digitally-Controlled Dual-Loop Structure
External Reference Clock
PFD
CP
/M
LF
Ref. PLL
VCO
Bang-Bang
Phase Detector
Reference Clock from PLL
CDR core
UP
DN
Phase Selection
Retimed
Data
Two Selected Phases
Data in.
Bang-Bang
Phase Detector
UP/DN
Phase
Controller
Phase Interpolator
Recovered
Clock
High-Speed Circuits and Systems Lab. Yonsei Univ.
Effect of Phase Resolution

Jitter Generation
 Quantization error
• Digitally-Controlled CDR generates “discontinuous phase”
 Jitter generation ∝ 1 / Phase Resolution
Quantization error
< Behavioral Simulation using CPPSIM* >
* M. H. Perrott, “Fast and accurate behavioral simulation of fractional-N synthesizers and other PLL/DLL circuits,” Design
Automation Conference, pp.498-503, Jun. 2002.
High-Speed Circuits and Systems Lab. Yonsei Univ.
Effect of Phase Resolution

Jitter Suppression and Frequency Offset Tracking
 Higher (more fine) phase resolution
• Smaller phase steps
• Narrower Loop Bandwidth
• More jitter rejection and Slower offset tracking
Jitter generation
∴
Phase resolution
Jitter suppression
Frequency offset tolerance
High-Speed Circuits and Systems Lab. Yonsei Univ.
Limit of Phase Resolution in Phase Interpolator

Two control methods
 Binary-weighted code
• 2N levels, Simple but Phase overshoot
,where N = bit width of control word
< Phase overshoot when large current sources are instantly turned on>
 Thermometer code
• N+1 levels, Complex but no Phase overshoot
∴
Difficult to increase phase resolution of PI higher than 16-level, or 4-bit.
High-Speed Circuits and Systems Lab. Yonsei Univ.
Design Goals

Achieving sufficiently high phase resolution with
little additional power consumption and die area

By using only 4-phase reference clocks and 16level thermometer coded PI
High-Speed Circuits and Systems Lab. Yonsei Univ.
Proposed Structure

Digitally-Controlled Delay Buffer (DCDB) is inserted for
higher phase resolution
4-Phase Reference Clock from PLL
Retimed
Data
2:1 MUX
2:1 MUX
Data in.
Bang-Bang
Phase Detector
Up/Down
Filter
Phase
Controller
Phase Interpolator
Digitally-Controlled
Delay Buffer
Recovered
Clock
High-Speed Circuits and Systems Lab. Yonsei Univ.
Digitally-Controlled Delay Buffer


Current-starved inverter, or buffer
Linearly variable delay for control codes
Input
Clock
Digitally-Controlled
Delay Buffer
Delayed
Clock
Control Code (2-bit)
Adjacent interpolated phases
Input Clock
Delayed Clock
High-Speed Circuits and Systems Lab. Yonsei Univ.
Digitally-Controlled Delay Buffer


Current-starved inverter, or buffer
Linearly variable delay for control codes
Input
Clock
Digitally-Controlled
Delay Buffer
Delayed
Clock
Control Code (2-bit)
Adjacent interpolated phases
Input Clock
Delayed Clock
High-Speed Circuits and Systems Lab. Yonsei Univ.
Enhancement of Phase Resolution

4X higher phase resolution by combining PI and DCDB
Interpolated phases
Interpolated
phase
Delayed
phase
Ntotal phase = Nreference phase × NPI resolution × NDCDB resolution
= 4-level × 16-level × 4-level
= 256-level (8-bit)
High-Speed Circuits and Systems Lab. Yonsei Univ.
Enhancement of Phase Resolution

4X higher phase resolution by combining PI and DCDB
Interpolated phases
Interpolated
phase
Delayed
phase
Ntotal phase = Nreference phase × NPI resolution × NDCDB resolution
= 4-level × 16-level × 4-level
= 256-level (8-bit)
High-Speed Circuits and Systems Lab. Yonsei Univ.
Delay Error of DCDB
 Negative error (shorter delay than desired one)
Interpolated
phase
Delayed
phase
 Positive error (longer delay than desired one)
Interpolated
phase
Delayed
phase
High-Speed Circuits and Systems Lab. Yonsei Univ.
Delay Error of DCDB
 Negative error (shorter delay than desired one)
Interpolated
phase
Delayed
phase
 Positive error (longer delay than desired one)
Interpolated
phase
Delayed
phase
High-Speed Circuits and Systems Lab. Yonsei Univ.
Delay Error of DCDB
 Negative error (Shorter delay than desired one)
Interpolated
phase
Delayed
phase
 Positive error (Longer delay than desired one)
Interpolated
phase
Delayed
phase
High-Speed Circuits and Systems Lab. Yonsei Univ.
Sensitivity - Jitter Generation vs. Delay Error of DCDB
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

Behavioral simulation - CPPSIM, Circuit-level simulation - HSPICE
Relatively flat jitter generation for wide range of DCDB error
Why?
 Effect of enhanced phase resolution > Effect of locally wrong phase
movements
High-Speed Circuits and Systems Lab. Yonsei Univ.
Die Photo
165㎛
255㎛
< Die Photo >
High-Speed Circuits and Systems Lab. Yonsei Univ.
Experiment – Jitter vs. Delay error of DCDB

Measured waveform of recovered clock at 200ppm frequency offset
DCDB error = -50%
DCDB error = 0%
(-50%)
DCDB error = +50%
(0%) (+50%)
High-Speed Circuits and Systems Lab. Yonsei Univ.
Experiment - Jitter Suppression
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
27-1 PRBS transmitted through 2m PCB trace and 3.5m cable.
In 200ppm frequency offset
< Transmitted eye pattern >
114.3psP-P
424psRMS
< Retimed data of CDR >
38.89 psP-P
212 psRMS
High-Speed Circuits and Systems Lab. Yonsei Univ.
Summary of Prototype Chip
Process
0.18㎛ CMOS
Supply
2.0V
Data Rate
1.25-Gb/s
Offset Tolerance
±400ppm
Power Consumption
17.8mW (CDR core)
Die Area (CDR core)
255×165 ㎛2
High-Speed Circuits and Systems Lab. Yonsei Univ.
Conclusion

A novel method to enhance phase resolution is proposed.

By combining PI and DCDB, phase resolution can be
enhanced with little additional power consumption and
die area.

In both simulations and chip measurement, jitter
performance is not sensitive to delay error of DCDB.
High-Speed Circuits and Systems Lab. Yonsei Univ.
Thank You !!
High-Speed Circuits and Systems Lab. Yonsei Univ.