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Surface Micromachining
Dr. Marc Madou,
Fall 2012, UCI
Class 10
Surface Micromachining
n+
Basic Process Sequence (poly-Si)
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Blanket n+ diffusion of Si substrate
(ground plane)
Passivation layer (e.g. SiO2 , Si3N4 ,
LPCVD Si3N4 on top of SiO2)
Opening up the passivation layer for
contacts (observe color change or
hydrophobic/hydrophilic behavior):
– wet (BHF)
– dry (SF6)
Strip resist in piranha (adds some oxide
in the window)
Short BHF etch to remove thin oxide
n
n+
n
Lm
Photoresist
tSiO2
Lm + 2tSiO2
Si3N4
Surface Micromachining
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Deposition of a base, spacer or
sacrificial layer-phosphosilicate
glass (PSG)-CVD
Densification at 950 °C for
30-60 min in wet oxygen
Base window etching in BHF
for anchors
Structural material deposition
e.g. poly-Si (doped or undoped)
from (CVD at about 600°C ,
73 Pa and 125 sccm (standard
PSG
nitride
centimeter cube per SiH4  Si + 2H2
minute); at about 100Å/min)

e.g.
Anneal of the poly-Si at
1050°C for 1 hour to reduce
stress in the structure
Basic Process Sequence (poly-Si).
Structural layer
Surface Micromachining
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Doping of poly-Si: in-situ, PSG
sandwich and ion implantation
Patterning of structural material
e.g. RIE in , say, CF4-O2
Release step, selective etching of
spacer layer e.g. in diluted HF
Ri
nitride
Rm
RS
RS(m /min) Rm (m /min) Ri (m min)
Basic Process Sequence (poly-Si)
Surface Micromachining
Etchants-Spacer and Microstructural Layer
Etchant
Buffer/Isolation
Spacer
Microstructure
Buffered HF
(5:1, NH4 F:conc. HF)
LPCVD Si3N4/thermal
SiO2
PSG
Poly-Si
RIE usi ng CHF 3
BHF (6:1)
LPCVD
Si3N4
LP CVD
SiO2
CVD Tungsten
KOH
LPCVD
Si3N4/thermal SiO2
Poly-Si
Si3N4
Ferri c Chl ori de
Thermal SiO2
Cu
Polyimide
HF
LPCVD
Si3N4/thermal SiO2
Thermal SiO2
PSG
Polyimide
Al
PE CVD Si3N4
Nickel
Au
Ti
Poly-Si
SiO2
Phosphori c/ Aceti c
Aci d/ Ni tri c Aci d(PAN or
5:8:1:1
water:phosphori c:
aceti c:ni tri c)
Ammoni um Iodi de
Thermal SiO2
/ Iodi ne Al cohol
EDP
Thermal SiO2
Generic principle of surface micromachining
Al
Sacrificial layer definition
Si
Etch access
Polyimide diaphragm
Si
deposition
Releasing diaphragm:
phosphoric/acetic acid/nitric acidSi
(PAN)
Surface Micromachining
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Hot wall, horizontal reactor
Reaction rate controlled--at lower
pressures and well controlled
temperatures (100 to 200 wafers)
Poly-Si deposits everywhere
requiring periodic cleaning (e.g.
every 20 runs if each run deposits
0.5 µm)
Visit:
http://mems.eeap.cwru.edu/shortcou
rse/partII_2.html and http://wwwmtl.mit.edu:800/htdocs/tutorial.html
LPCVD of poly-Si
Surface Micromachining
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Stiction during release:
Stiction
– Surface tension during drying pulls movable
members together (See also room temperature
bonding of Si to Si and glass to Si)
– Solutions:
» Stand-off bumps
» Sacrificial polymer
» Sacrificial poly-Si links to stiffen the
structures
» HF vapor
» Freeze-drying water/methanol mixtures
» Super critical cleaning
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Stiction after release:
– Hydrophobic monolayers
– Rough surfaces
– Bumps
Surface Micromachining
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With L=150 µm and W=t=2 µm,
fo=10 to 100 kHz.
Annealing at high temperature
(900-1150°C)
Fine-grained tensile vs large
grained compressive
Doping elements
Sandwich doping and annealing.
Vary material composition e.g Si
rich Si3N4
In PECVD: change the RF power
and frequency
In sputtering: gas pressure and
substrate bias
Control of film stress
1 4EtW3 24 r t W
fo 
3 
2 ML
5ML
Surface Micromachining
Control of film stress
Folding flexures makes the resonant
frequency independent of the residual stress
but warpage becomes an issue
 Corrugated structural members (see
above)
Y

k y  k x (force constant)
1
2
k x 
fx   
M
X
Surface Micromachining
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Sealing processes
Microshells a wafer level
packaging strategy
Thin gaps (e.g. 100 nm) are etched
out and then sealed:
– Reactive sealing by oxidation
– LPCVD deposition
COMPOSITE SI3 N4 /POLYSILICON
POLYSILICON PIEZORESISTOR
Surface Micromachining
Comparison of CMOS and Surface Micromachining
CMOS
Common Features
Proces s flow
Vertical dimens ion
Lateral dimens ion
Complexity (# mas ks )
Standard
~ 1 µm
<1 µm
>10
S urface
Micromachining
Silicon based processes
Same materials
Same etching principles
Application specific
~1-5 µm
2-10 µm
2-6
Critical Process Temperatures for Microstructures
LP CVD Depos ition
"
"
"
Annealing
IC compatibility
"
"
"
Temperature (°C)
450
610
650
800
950
1050
Material
Low Temperature Oxide
(LTO)/PSG
Low stress poly Si
Doped poly Si
Nitride
PSG densification
Poly Si stress annealing
- Junction migration at 800 to 950°C
- Al interconnect suffers at 400-450 °C
- Topography
Surface Micromachining
Poly-Si surface micromachining modifications: porous poly-Si
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Just like we can make porous Si from
single crystal Si we can do the same
CVD Si3N4
with poly-Si (low currents densities in
highly concentrated HF)
Applications:
– Channels parallel to a flat surface
(switch from porous to polishing and
back--chambers with porous plugs)
– Enclosed chambers (blisters of free
poly-Si)
– Hollow resonators (higher Q)
CVD Si3N4
CVD poly-Si
Surface Micromachining
Poly-Si surface micromachining
modifications: hinged poly-Si
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Make structures horizontally and erect
them on a poly-Si hinge (probe
station)---rigid structures (Prof. Pister,
UCB)
Polyimide hinges also have been made
( butterfly wing)---movable structures
polyimide hinge (E= 3 GPa)
poly-Si hinge (E= 140 GPa)
Surface Micromachining
Poly-Si surface micromachining modifications:hinged poly-Si
Micromachined integrated optics for free space interconnections
Pister et al., UCB
Surface Micromachining
Poly-Si surface micromachining
modifications: thick poly-Si and HEXSIL
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Thick poly-Si--10 µm in 20 ‘ with
SiH2Cl2 at 1000°C has become
possible (low tensile stress)
HEXSIL (Dr. Keller, UCB):
– Deep dry etching of trenches in SCS
(e.g. 100 µm deep)-short isotropic etch
to smooth the walls
– Deposition of sacrificial and structural
materials (undoped, doped poly-Si and
metal e.g. Ni)
– Demolding by etching away the
sacrificial material
Surface Micromachining
Poly-Si surface micromachining modifications: HEXSIL
Membrane filter with stiffening rib
Dr. Keller, UCB
HEXSIL tweezers
Surface Micromachining
SIM OX substrate
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0.2 m epi-Si
Types of Silicon On Insulator
(SOI) processes:
0.4 m buried oxide
– SIMOX (Separated by IMplanted
OXygen)
– Si fusion bonded wafers
– Zone-melt recrystallized
polysilicon (ZMR)
Dry etch access hole
Sacrificial layer etching
Thicken up epi Si to
4 m
Hermetic sealing of etching hole by plasma CVD of
non stressed dielectric plug
Metallization and diaphragm definition
P
Poly-Si surface micromachining
modifications: SIMOX
P
Surface Micromachining
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Polyimide: e.g. SRI flat panel
display
UV depth lithography
– AZ-4000 (high viscosity, many
layers)
– SU-8 (IBM)
Non-poly-Si surface micromaching.
Capp Spindt