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4/30/2010
Iowa State University
EE492 – Senior Design II
International collaboration
Product conceptualization &
specification in addition to
design
Integrated circuit (IC) rather
than system design
Research-orientated
objectives
Design a test chip to support ISU
research on electromigration &
IC reliability
The chip must include test
structures composed of actual
metal interconnects in a modern
silicon process
Must be capable of interfacing
with a controller to allow
electrothermal conditions in the
chip to be varied and monitored.
Electromigration – a complex
physical phenomena that causes
mechanical stress in metal
interconnects
Important failure mechanism in ICs
Strong, non-linear dependence on
current-density and temperature
Need models for electromigration
that predict reliability under
practical conditions
Electromigration
in progress!
Subject interconnects to
variable electrothermal stresses
Measure time-to-failure of many
samples
Analyze statistics, develop
models, fit data, etc.
Use accelerated lifetime
technique
Very high temperatures and
current densities!
Proposed IC contains 8
identical metal test structures
Current-steering Digital-toAnalog Converter provides
0-25mA to test structure
On-die analog temperature
sensing circuits
Open-circuit detection
Control logic with serial
interface
Process technology:
0.18 µm standard CMOS
Temperature Sensor
TEMP_1
Temperature Sensor
TEMP_2
Temperature Sensor
TEMP_3
...
I_WR_EN
I_DATA
ADDR_WR_EN
ADDR_DATA
FAIL
Control Logic
VDD
I<1>
I<2>
DAC #1
DAC #2
FAIL<1>
Open-Circuit
Detect
I<4>
I<3>
DAC #3
FAIL<4>
FAIL<3>
FAIL<2>
Open-Circuit
Detect
DAC #4
Open-Circuit
Detect
Open-Circuit
Detect
...
Test
Structure
#1
Test
Structure
#2
Test
Structure
#3
Test
Structure
#4
GND
I_EN
Metal layer
M1
Width
0.23 µm
Equivalent length
Up to 11.5 mm
Thickness
210 nm
Material
Cu
Single-layer metal
interconnect with
serpentine pattern
Corners reinforced
to mitigate current
crowding
Current range of 0 to 25 mA
7 bit resolution
LSB Current – 200 µA
Current-Steering
Architecture
Binary-weighted sources
Constant power
Open Circuit Detection
Two inverters on the output
0010110
DAC
Compact, CMOS-based
sensor design
5 sensor distributed
throughout the floor plan
Serial interface
Simple protocol
Low pin-count
Needed standard cell
library for synthesis
Free, scalable library did
not meet design rules of our
process
Extensive work to
customize , re-verify
standard cells
Master current switch
Reference-distribution network
Floorplan symmetry to
prevent uncontrolled
experimental variables
Significant redundancy
and reinforcement of
non-test blocks for
reliability
Final design is 860 µm x
860 µm
Analog verification: relevant performance
parameters for each block tested over full PVT
range with 500-run statistical simulations
Digital verification: functional simulations,
timing analysis
System-level, mixed-signal verification:
several long transient simulations covering
typical operation sequence
#1 VDD rises
#2 Reference current starts
#3 <000> written to address reg.
#4 <0101010> written to address reg.
#5 master current switch enabled
#6 test current settles at predicted value
DAC
Temperature sensor
Top-level functional