Transcript Unit 1 Difference 8086_386_i7

Differences of 8086,80386,i7
Differences of 8086,80386,i7

Architecture and Pin Diagram
Parameter
8086
80386DX
i7
Year
June 1978
October 1985
November 2008
No of Cores
1
1
4
Architecture
16bit
32bit
64bit
Speed
5,8,10 MHz
16,20,25,33 MHz
2.66,2.80,2.93,3.06,3
.20 GHz
Address Bus
20bit
32bit
64/32bit
Data Bus
16bit
32bit
64bit
Operating Voltage
5V
5V
1.4V
Addressable
memory
1MB
4GB
64GB
Physical Memory
1MB
4GB
64GB
Virtual Memory
1MB
64TB
240 bytes
Differences of 8086,80386,i7

Architecture and Pin Diagram
Parameter
8086
80386
i7
Register Size
16 bit
32 bit
64 bit
Instruction Queue
Size
6 bytes
16 bytes
18 entries
Pins available
40 pin DIP package
132 pins
1366 pins
Technology
HMOS
CHMOS II
Bi-CMOS
Pipeline Capability
Yes
Yes
Yes
Instruction set
117 Instructions
129 Instructions
Supports 8086,386 and
SIMD instructions
On chip cache
--
--
3 level cache per
core L1(32KB),
L2(256KB),L3(8MB
)
Support for microarchitecture
--
--
Nehalem
Differences of 8086,80386,i7

Architecture and Pin Diagram
Parameter
8086
80386
i7
Operating
Modes
1) Maximum Mode
2) Minimum Mode
1) Real Mode
2) Protected Mode
3) Virtual 8086 Mode
1) Compatibility Mode
2) 64 bit Mode
Memory Models
1) Flat Memory
2) Real Address mode
1) Flat memory
2) Segmented Memory
3) Real Address Mode
1) Flat memory
2) Segmented Memory
3) Real Address Mode
On chip FPU
No
No
Yes
Superscalar
No
No
Yes
Branch
Prediction
No
No
Yes
Overclocking
Feature
No
No
Yes
Multiprocessor
Support
No
No
Yes
Latency
4
6
15
Differences of 8086,80386,i7
 Additional Features
80386
 Architectural support for memory management
 Virtual addressing
 Segmentation and Paging
 Protection Mechanism
 Multitasking
2. i7
 Intel Quick Path interconnect(QPI)
 Intel Turbo Boost Technology
 Smart Cache
 Intel virtualization Technology
 Hyper-threading support
 MMX instruction Set
1.
Differences of 8086,80386,i7

Register Set
Parameter
8086
80386DX
i7
General Purpose
Registers
8 GPRS of 16 bit
8 GPRS of 32 bit
16 GPRS of 64 bit
Instruction Pointer
IP of 16 bit
EIP of 32 bit
RIP of 64 bit
Segment Registers
4 of 16 bit
6 of 16 bit
6 of 16 bit
Stack Pointer
16 bit
32 bit
64 bit
Flag Register
Flag Register of
16 bit
EFlags Register of
32 bit
RFlags Register of 64 bit
Control Register
--
32 bit
64 bit
Debug Register
--
32 bit
64 bit
Descriptor Table
Register
--
GDTR : 48 bits
IDTR : 48 bits
LDTR : 16 bits
TR : 16 bits
Selector : 16 bits
GDTR : 80 bits
IDTR : 80 bits
LDTR : 16 bits
TR : 16 bits
Selector : 16 bits
Differences of 8086,80386,i7

Register Set
Parameter
8086
80386DX
i7
FPU Registers
--
--
8 Data Registers of 80 bits
Status Register of 16 bits
Control Register of 16 bits
Opcode register of 11 bits
IP register of 64 bits
Data pointer register of 64 bit
Tag register of 16 bits
MMX Register
--
--
8 MMX Register of 64 bits
16 XMM Register of 128 bits
MXCSR Register of 32 bits