Transcript Final Project Presentation Slides

Differential 2R Crosspoint
RRAM for Memory system
in Mobile Electronics with
Zero Standby Current
Pi-Feng Chiu, Pengpeng Lu, Zeying Xin
EECS, UC Berkeley
05/06/2013
Outline
• Introduction
o Memory Hierarchy
o RRAM switching mechanism
• Issues of Crosspoint Array
• Proposed Differential 2R cell
o Cell Characteristics
o Differential 2R cell and array design
• Circuit Implementation
o Divided WL and Sense-before
• Simulation Results
• Comparison
• Conclusion
Memory Hierarchy
Perfect Memory:
Nonvolatile
High speed
Small Area
Low power
High Endurance
Leakage issue
CPU
Register
Cache
L1
L2
Main Memory
(DRAM)
Permanent Storage
Hard Disk Drive, Solid State Drive
Slow
•
•
•
•
RRAM switching
mechanism
RRAM: Resistive Random Access Memory
Sandwiched cell structure
SET: Switching to Low Resistance State (LRS)
RESET: Switching to High Resistance State (HRS)
Crosspoint Issues
1T1R  Crosspoint structure
Leakage issues:
Write – write energy efficiency
Read – read margin
Write Disturbance
WLs (VSET)
WLs (VSET)
n-1
…
n-1
…
m-1
WLx (VSET/2)
…
…
BLs (0)
(a) HWHB
BLx (Floating)
m-1
…
m
…
WLx
(Floating)
m-1
(a)
n-1
…
BLx (VSET/2)
BLx (VSET/2)
n: BL number, m: WL number
WLs (VSET)
BLs (0)
(b) FWHB
m-1
…
WLx
(Floating)
BLs (0)
(c) FWFB
(c)
VSET n -1 m -1
I leakage =
´(
+
)
2
RL
RL
VSET n -1
(b) I leakage =
×
2
RL
(n -1)(m -1)
I leakage = VSET ×
(n + m -1)× RL
Cell Characteristics
• Tradeoffs
o
o
o
o
o
RLow vs. write energy
Write time vs. Write voltage
Write energy vs. Write voltage
Read margin vs. Rlow
Sensitivity to Write time
Differential 2R cell
1 cell
WLa[1]
BL0
BL1
BL2
+
In read operation,
WLa=Vread, WLb=0
Voltage-sensing VBL
+
VBL=Vread*Rb/(Ra+Rb)
Ra
Rb
WLb[1]
WLa[0]
WLb[0]
Write-1
Write-0
Ra
SET
RESET
Rb
RESET
SET
WL
Vwrite
0
BL
0
Vwrite
Assumption:
VSET=VRESET=Vwrite
Divided WL
• To constrain overall write current to 100~200uA, WL length
need to be set to 4-cell wide
VSET (n -1) 1
1
×( + )
2
RH RL
Divided WL: decouple local WLs and connect to global WL by
switches.
Tradeoff between leakage current and area penalty
I leakage =
•
•
GWLb
GWLa
BEOL process enables
stack ability
…
Ra
Rb
LWLa
LWLb
BL
SWa
SWb
Sense-before-Write
• Resistance value drops if a SET pulse repeatedly
access to the cell.
Lowest resistance value
Targeted resistance value
I(cell)
• Solution:
Write
?
DIN
Read
DOUT
If
DIN=
DOUT
?
No
Write
Yes
Pass
Block diagram
WE
RE
DIN[7:0]
A[7:0]
CLK
Control
circuit
GWL
Block [63]
...
Block [62]
Block [2]
Block [1]
LWL
Block [0]
Vwrite
Vhalf
Vread
WL multiplexer and driver
I/O[7:0]
SAENb
VBL
VREF
SAENb
VOUT
SAENb
BL multiplexer and driver
SAEN
StrongARM Sense Amplifier
DOUT[7:0]
Vref
SAENb
Write-0 Write-1
to cell01 to cell11
WLa[0]
0
WLb[0]
WLa[1]
~Vwrite/2
WLb[1]
BL[1]
Vref
~Vwrite
DOUT
SET
R1 R0
I(cell01b)
RESET
I(cell01a)
Write operation Read operation
Features
Clock Frequency
Density
Power supply
Write voltage (Vwrite)
Read voltage (Vread)
Reference voltage (Vref)
RH/RL
Write current (one block)
Read current (one block)
Standby current
500 MHz
64KB
1.0 V
0.95 V
0.4 V
0.2 V
90KΩ/8KΩ
140 µA
16.6 µA
~0A
Comparison
Differential 2R
SRAM
RRAM
Performance
500MHz
> 1GHz
Active Power
Large (DC
Small (Static Logic)
current)
Standby Leakage 0
570pJ/cell
Area
0.04 um2 (*)
0.1 um2 (22nm)
8
Endurance
>10214
*: assume metal width and~10
space are 50nm, area = (0.05*4)
Fit for L2/L3 cache in mobile electronics to save battery life
Conclusion
• Differential 2R crosspoint RRAM design
o 64KB RRAM circuit
o Divided WL and Sense-before-Write approach
o 28/32nm PTM, RRAM cell model, Eldo simulator
• Crosspoint RRAM  Cache?
o Area: yes
o Power: depending on application
o Endurance
CPU
Register
Cache
L1
L2
Main Memory
(DRAM)
Permanent Storage
Hard Disk Drive, Solid State Drive
• Future Work:
o Cell characterization
o Leakage reduction, Cell distribution
?
Thanks!
Reference
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ITRS Roadmap (http://www.itri.net)
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