Instructor: Evgeniy Kuksin Preformed by: Ziv Landesberg Duration: 1 semester

 Create a FIR filter that can process pulses from photon counting detectors and perform Peak Detection using NI Labview FPGA.

   The project is completed!

Final clock rate – 125MHz (due A/D) Successfully processing 4 channel simultaneously

Photons + 𝐶 𝐹 ADC FPGA Shaper Peak Detector Readout To PC

Signal generator (Preamplifier emulator) A\D NI 5761 14 bit 125 MHz FPGA(125MHz)

  Trapezoidal can achieve optimal noise performance from signal. Trapezoidal Shaper, unlike many analog pulse shaper, immune to “ballistic deficit”, that causes energy distortion in the spectrum.

Trapezoidal shaper can not be implemented by analog circuits.

 The Coefficients were calculated by the method at the article of “On nuclear spectrometry pulses digital shaping and processing” , the biexponential pulse part.

the method is to inverse the transfer function of the pulse(making it a digital delta) , and then convolute the delta with a trapezoid. Due to the fact that both the inverse function of the pulse and the trapezoid were finite length , the resulted filter was FIR.

Calc trapez impulse response Calc invers function of pulse Delete zeroes from output

   The input signal was generated at 2 main stages : 1) create an array with Poisson distributed digital delta’s in it. It was done by the Poisson noise generator, that each event was transformed to delta, and each none event was transformed to zero.

2 ) transfer the deltas to linear rising- exponential decaying pulse, was done simply by convoluting the array with the response of such pulse(with cut off values lower than exp(-10 ))

Impulse generating Shape of a pulse Convolut deltas with wanted shape

Impulses Resulted signal Wanted shape

The building of the filter in Labview was done using the fir template already existing in the program. So first stage was to create a fds file to generate filter from it.

The second stage was to use the automatic filter generation

Distributed arithmetic does not use DSP units !

Input signal Shaped signal

Input signal Shaped signal Result of shaper with ballistic defflict histogram

Current Next shper (8 rise time) 6 rise time shaper

Mean-60 80 60 40 20 160 140 120 100 80 60 40 20 0 0 140 120 100 80 60 40 20 0 0 2 Mean-120 0 2 Mean-140 0 2 4 4 4 6 6 6 8 8 8 10 10 10 4 3 2 1 3 2 1 0 0 4 0 0 4 3 2 1 0 0 2 2 Std-140 4 2 Std-60 4 Std-120 4 6 6 6 8 8 8 10 10 10

Rise time: std_60 mean_60 1 3.5

60 std_120 mean 120 3.2

121 std_140 3.7

mean_140 140 6 1.9

60 1.9

123.5

1.9

142.5

8 1.9

60 1.8

125 1.8

144.5

3,5 3 2,5 2 1,5 1 0,5 0 0 std channel 0 1 2 3 0,5 1 std_60 3.2

3.2

3.2

3.2

1,5 2 std_60 std_120 std_140 2,5 3 3,5 mean_60 60 60 60 60 std_120 3.3

3.3

3.3

3.3

mean 160 140 120 100 80 60 40 20 0 0 1 mean_120 std_140 122.5

3.2

122.5

3.2

122.5

122.5

3.2

3.2

2 mean _60 mean _120 mean _140 3 mean_140 142 142 142 141 4

  The shaper which is most resistance to noise is the 16 length, with 8(sample) rise time. But apparently he is effected by quantization effect, and he caused distortion in pulses heights( probably because they have different rise time) The 8 length shaper is nearly unaffected by quantization effect, and is the not distortive . The third filter is kind of the middle between them, with low noise and low distortion .

 The final system is operating at 125MHz due to the clock rate of the A/D(can only be 125MHz or 250MHz). However the “bottle neck” of the system is the FIFO to the host, so in order to increase throughput we could create the histogram of the peak detector on the FPGA himself, and send it to the host(needs slower FIFO to do it).