Transcript spi_final_presentation - vlsi-spi

Serial Peripheral Interface
Final Project Presentation
27.12.2011
Presented by:
• Omer Shaked
• Beeri Schreiber
Supervised by:
• Tal Yahav
• Leon Polishuk
Project Requirements
1. Implement SPI Master and SPI Slave cores (VHDL)
2. Implement Master and Slave hosts (VHDL)
3. Verify the entire design (SystemVerilog)
SPI Protocol Description
• Serial data link standard
• Operates in full duplex mode
• Devices communicate in master/slave mode
• Single master, multiple slaves
• The master initiates the data frame
SPI Interface Description
• The interface is consumed of four signals:
• SPI_CLK: Serial Clock (output from master)
• SPI_MOSI: Master Output, Slave Input
• SPI_MISO: Master Input, Slave Output
• SPI_SS: Slave Select (output from master)
SPI Clock Configuration
• The master configures the clock polarity and phase
SPI Master Burst Waveform
1
3
Enable
SPI Slave
End of Reset
5
Disable
SPI Slave
4
a
b
2
a.
b.
6
SPI_CLK
Divide Factor : 2
8
SPI_CLK
Divide Factor : 4
FIFO:
Request for data
Data is Valid
Write to Registers:
Data (0x4) + data_valid
7
SPI Response:
Register acknowledge
9
Output data from
SPI Slave is valid
SPI Slave Burst Waveform
1
3
End of Reset
6
SPI_SS is
Activated
SPI_SS is
De-activated
a
b
2
a.
b.
FIFO:
Request for data
Data is Valid
4
Data is sampled after
SPI_CLK rising edge
Data is propagated after
SPI_CLK falling edge
5
End of Transaction
Dout is valid
Wishbone Description
• Wishbone: Flexible design methodology for use
with semiconductor IP cores
• Wishbone Interface is used, in this project, to read
and write data.
Wishbone Description:
Write Burst
Start of Cycle
Data Acknowledged
Address
Burst Length
Repeat last transaction
Output Data
Writing
New Input Data
Wishbone Description:
End of Write Burst
End of Cycle
Last Strobe
Address
Burst Length
Input Data
Writing
New Input Data
Data with no
strobe (Ignored)
Wishbone Description:
Read Burst
Start of Cycle
Data Valid
Address
Repeat last transaction
Burst Length
Output Data
Continue to
next transaction
Reading
New Output Data
Wishbone Description:
End of Read Burst
End of Cycle
Last Strobe
Address
Burst Length
Continue to next transaction
Output Data
Reading
New Output Data
Implementation Stages
Unit Level
• Design of SPI Master and SPI Slave cores
• Design internal blocks of master and slave hosts
• SPI Master and SPI Slave individual Test Benches
Implementation Stages
Top Level
• SPI top test bench (SPI Slave  SPI Master)
• Top architecture test bench (Whole system)
SPI Core Design
• Four main interfaces:
SPI Core
Configuration interface
• Generic word length
• Generic number of slaves
SPI Interface
FIFO Interface
Received Data Interface
Slave
Host
RAM
Interface
SPI
Slave
Interface
Master
Host
SPI
Master
Interface
Wishbone
Slave
Interface
Top Architecture Design
• Master host implements Wishbone slave interface
• Hosts communicate via SPI
• Slave host implements RAM interface
RAM
Master Host Design
Master Host
Wishbone
Slave
Controller
M.P.
Decoder
Checksum
Enc.
RAM
M.P.
Encoder
‘0’
FIFO
SPI
Master
SPI Interface
Dec.
RAM
MUX
Wishbone Interface
Checksum
Slave Host Design
Slave Host
Slave Host Controller
SPI
Slave
Dec.
RAM
RAM
Controller
Registers
Checksum
FIFO
M.P.
Encoder
Enc.
RAM
RAM Interface
SPI Interface
M.P.
Decoder
Read
MUX
Checksum
R
A
M
Verification Plan
• Basic block-level VHDL TBs for SPI cores during
design stage
• SystemVerilog TBs
• SPI Master
Not part of the original
• SPI Slave
verification plan
• Top: SPI Master + Slave
• Top Architecture (Whole system)
Main Verification Guidelines
• Randomly generated values
• Functional Coverage collection
• Automatic scoreboarding
• SPI cores – includes possible edge cases
• Top architecture – only basic functionality
SPI Master Test Bench
Test Name
5
Status
Scoreboard
Simple burst
All CPOL, CPHA configurations
2
Passed
3
7
Generator
All SPI clock frequencies
and
SPI Master
Driver
Reset drives outputs to default values
(DUT)
SPI Interface
FIFOI interface
1
Passed
Forbidden Configuration
Receiver
Generator
Passed
and
Driver
Passed
4
Passed
Receiver
CFG interface
FIFO Error (Not responding)
6
CFG_DUT
Illegal SPI Clock Frequencies
Passed
Passed
SPI Slave Test Bench
Test Name
Status
6
Simple burst
Passed
All CPOL, CPHA configurations
Passed
Scoreboard
1
7
Interrupt
CFG_DUT
SPI Interface
FIFOI interface
8
Passed
GeneratorMax SPI clock frequency
4
3
and
Generator
Reset
drives
outputs
to
default
values
Passed
SPI Slave
Driver
SPI Master
(DUT)
BFM Passed
Configuration
during
active
2
5
transmission
Receiver
Receiver
CFG interface
Timeout
Passed
Passed
SPI Top Test Bench
Test Name
Status
5
Simple burst
Passed
All CPOL, CPHA configurations
Passed
Scoreboard
7
DUT
Different SPI clock frequencies
Passed
1
3
CFG interface
SPI Slave0 Passed Generator
and
SPI Slave1
Passed Driver
SPI Slave2
4
Receiver
SPI Slave3
FIFOI interface
SPI Interface
Receiver
SPI Interface
2
FIFOI interface
Generator Max SPI clock frequency
and
Driver
Generics
SPI Master
CFG interface
6
CFG_DUT
Top Test Bench (UVM 1.1)
UVM_TEST
UVM_ENV
Sequencer
Monitor
Driver
Scoreboard
WBS
DUT
Agent
Master
Host
SPI
I/F
Slave
Host
External
RAM
Top Test Bench (UVM 1.1)
Test Name
Status
All burst lengths
Passed
All CPOL, CPHA configurations
Passed
All SPI clock frequencies
Passed
Burst length exceeds RAM address
Removed. Not
relevant.
Transaction interrupted
Removed. Not
relevant.
Reset in middle of transaction
Removed.
SV Verification Summary
• Total of 7 major bugs were found and fixed:
• SPI Master – 2
• SPI Slave---------------------------------------------------------------------------------------------------–3
Covergroup
Metric Goal/ Status
At Least
• Top – 2 ---------------------------------------------------------------------------------------------------COVERGROUP COVERAGE:
TYPE /top/master_host_monitor/cov_trans
100.0%
100 Covered
Coverpoint cov_trans::length
100.0%
100 Covered
Coverpoint cov_trans::init_addr
100.0%
100 Covered
Coverpoint cov_trans::div_factor
100.0%
100 Covered
Coverpoint cov_trans::cpol_cpha
100.0%
100 Covered
CLASS master_host_monitor
TOTAL COVERGROUP COVERAGE: 100.0% COVERGROUP TYPES: 1
• Reached 100 % functional coverage for all TBs
Summary & Conclusions
• A lot more than the original project
Design:
• Master and Slave host implementation, instead of
only SPI Master and Slave
Verification:
• Implemented 4 TBs instead of 3 TBs
• All major SystemVerilog features have been used
• U s a ge o f U V M 1 . 1
Summary & Conclusions
• A lot more than the original project
• Well-organized development methodology
• Relatively fast completion of the project
• Very enjoyable and fruitful
The End
Thanks to both of our supervisors !