Setup of the stdio-functions: ● AVR Libc supports stdin, stdout and stderr devices needed for printf, scanf and stream I/O ● no standard in/output device is defined for the microcontroller ● the I/O-subsystem has to be initialised -> setup functions for character based IO: FILE * fdevopen ( int (*) (char, FILE*) put , int (*) (FILE*) get ); ● fdevopen() replaces fopen() the first write device is used for stdout, stderr; the first read-device is used for stdin ● these functions can use any physical medium / bus ● beware: printf is useful but need lots of memory (floating point conversion routines etc.)

Setup of the stdio-functions: int uart_putchar_file(char c, FILE * fp) // helper function to put out a character on the UART { if (c == '\n') uart_putchar_file('\r',0); // add a carrige return to a line feed character loop_until_bit_is_set(UCSRA, UDRE); // wait until the Data Register Empty bit is set UDR = c; // send out the character return(0); } ( …) fdevopen(uart_putchar_file, NULL); printf (" The value is %.2f \n", (float) val ); ( …)

USART – RS232 Level Converter ● RS232 – Levels (10/-10 V) extend transmission distance ● Max 232: 2 TTL inputs -> RS232 outputs 2 RS232 inputs -> TTL outputs

RS232 Alternatives

UART – USB Converter Solutions Example: FTDI 232 / FTDI245 converter chips ● connect directly to UART ● provide USB enumeration Device IDs (Eeprom) ● royality free Driver for Win / Linux generates virtual Com Port (VCP) ● data rates up to 1 MBit/s ● 5V and 3.3V designs supported ● Bus-powered and self-powered configurations

UART – USB Converter Solutions ● UM232 Dip – Module with Crystal and USB- Plug ● FT245 based parallel FIFO Module up to 3MBit/s ● Vinculum VDrive USB Host controller USB Flash Drive <-> UART Interface http://www.ftdichip.com

Wireless communication: UART <-> Bluetooth Example: Bluegiga WT11 – module http://www.bluegiga.com

● Class 1 BT Device (<300m) ● on-chip or external antenna ● UART, SPI, USB busses ● iWrap firmware ( AT - like commandset ) ● RFCOMM, HCI, HID stacks and Serial Port Profile

The Analog Digital Converter ● 10-bit Resolution (8-bit Accuracy on ADC4 and ADC5) ● Up to 15 kSPS at Maximum Resolution ● 6 Multiplexed Single Ended Input Channels ● 8 Multiplexed Single Ended Input Channels in TQFP / MLF Package ● 0 - VCC ADC Input Voltage Range ● Selectable internal 2.56V Reference Voltage ● Free Running or Single Conversion Mode ● Interrupt on ADC Conversion Complete ● Sleep Mode Noise Canceler

http://www.reedag.ch

The Analog Digital Converter ● A/D conversion by successive approximation: DAC and comparator Min: 0x0000 = GND Max: 0x03FF = AREF-1LSB ● Internal 2,56V reference: do not connect external voltages to AREF if internal reference is used ● Channel multiplexer select input channel before conversion starts

The Analog Digital Converter Successive approximation: ● Starting with the MSB, test values are generated converted to analog (DAC) ● Result of comparation influences current bit in approximation register ● After n bits, the result is latched out

The Analog Digital Converter Types of Conversion Errors: Offset error ATmega8 – ADC: Gain error Non-linearity

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0.5 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy

The Analog Digital Converter ● ADC Clock should run at 50kHz – 200kHz to give full resolution ● Prescaler generates ADC clock from CPU clocks >= 100 kHz ● ADPS2:0 bits of ADCSRA Register select clock prescaler value

The Analog Digital Converter Single / First conversion takes 25 ADC clock cycles Free running conversions take 13 ADC clock cycles After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH)

The Analog Digital Converter ADEN: ADC Enable ADSC: ADC Start Conversion start a single conversion or free running mode ADFR: ADC Free Running Select 1: continuous sampling and update of data registers ADIF: ADC Interrupt Flag ADIE: ADC Interrupt Enable Reset pending interrupts by writing 1 to the ADIF-Bit !

The Analog Digital Converter REFS1:0 Reference Selection Bits 00: external AREF, 01: AVCC, 11: internal 2,56V reference ADLAR: ADC Left Adjust Result 1: result is left adjusted, 0: result is right adjusted MUX3:0: select the A/D input channel: 0000: ADC0 – 0111: ADC7, 1110: 1,23V, 1111: GND

The Analog Digital Converter Handling of the ADC Data Registers (ADCL, ADCH): ADLAR=0 ADLAR=1 ● read Low Byte (ADCL) first, then high byte (ADCH) ● If only 8 bits resolution are needed, use left adjustment and read only high byte

The Analog Digital Converter ADC Noise canceler: ● conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals ● select single conversion mode and enable ADC interrupts Enter ADC Noise Reduction mode (select sleep mode „Idle“) ● ADC conversion be will start automatically after CPU is put to sleep using the sleep () command ● ADC interrupt (or other interrupt) will wake up the CPU ● next conversion will be issued after next sleep - command

The Analog Digital Converter General issues for using the A/D converter ● connect low impedance sources ( < 10kOhm) to achieve fast sampling rates ● do not connect signals with frequencies higher than the Nyqist frequency (half the sampling frequency) ● Use a low-pass filter to remove higher frequency components to prevent aliasing ● Keep analog signal paths as short as possible

The Analog Digital Converter General issues for using the A/D converter ● Make sure analog tracks run over the analog ground plane, keep them well away from high-speed switching digital tracks ● Use an LC network to connect AVCC (low pass filter the supply voltage)

The Analog Digital Converter Example: Initialisation for Interrupt driven AD Conversion ADCSRA = (1<