Transcript PowerPoint プレゼンテーション

Super Belle CDC
Shoji Uno (KEK)
Dec-12th, 2008

Basic design
 Electronics
 Test of pre-amplifier chips

Wire stringing method
 Schedule
Baseline Design
sBelle
Belle
Main parameters
Radius of inner boundary (mm)
Radius of outer boundary (mm)
Radius of inner most sense wire (mm)
Radius of outer most sense wire (mm)
Number of layers
Number of total sense wires
Effective radius of dE/dx measurement (mm)
Gas
Diameter of sense wire (mm)
Present
77
Future
160
880
88
863
1140
172
1120
50
8400
752
58
15104
978
He-C2H6 He-C2H6
30
30
Wire Configuration
250 mm
Present CDC
New CDC
250 mm
1200 mm
Yesterday CDC meeting

One and half hours from 16:00
 Main topics
 Test results of pre-amplifier chips
 Wire stringing method

Several new people joined.
 One new KEK posdoc candidate
 3 persons from KEK electronics group
 5 foreigners
 One Japanese person (non current CDC member)
 3 current CDC KEK members
 13 in total : more than I expected.
 We are waiting for more people.
Prototype of readout board by Y. Igarashi

Under 20cm

FADC
ASB +
Discriminator
RJ45
SFP
ASB +
Discriminator
Optical Transceiver

 TDC: 1 nsec counting
 FADC reading
 Control

FPGA
FPGA: Spertan3A
 SiTCP
(CONTROL,
TDC)

ASB +
Discriminator

FADC
ASB +
Discriminator

16ch/board
BJT-ASB/Comparator part
FADC: over 20MHz / 10bit
FPGA : Vertex-5 LXT
FPGA
(SiTCP)


RJ45


RJ-45 for SiTCP
RJ-45 for Belle DAQ timing
signals
SFP for Belle DAQ data line
LEMO input x 3
LEMO output x1
Shielded substrate
Test of Amplifier by N. Taniguchi

Three amplifiers
 Hybrid pre-amplifier (with receiver, gain:10) used in Belle-CDC
 ASD ( Amp + Shaper + Discriminator ) chip (with receiver, gain:7 ) used in ATLASTSC
 No production, now.
 ASB ( Amp + Shaper + Buffer ) developed by ASIC group of KEK
 Can be optimized for Super Belle CDC in near future.

Check signal shape using oscilloscope
Gas (Ar 90%+CH4 10%)
Fe55 5.9keV X-ray
Amp
Tungsten wire
Small tube chamber
Receiver
Comparison
HV=1.7kV
~300mV
100ns
Pulse height [mV]
Belle AMP
● Belle AMP
■ ATLAS ASD
▲ T-ASD
~220mV
40ns
ATLAS ASD
~140mV
HV [kV]
40ns
T-ASD
Comparison
Noise level
~5mV
Belle AMP
Saturation
~3mV
~5mV
T-ASD
ATLAS ASD
HV=1.9kV
ATLAS ASD
~600mV
HV=1.9kV
T-ASD
~600mV
distorted
saturate
Results on test of amplifiers

New ASIC chip is usable after some
modifications.

We can contact KEK electronics group
closely.
Wire stringing

Now, I am thinking a vertical stringing, not
horizontal.
 Once, I thought the horizontal stringing.

Vertical stringing with outer cylinder.
Human can stand inside the chamber and can touch
the wire.
 Inner diameter without the small cell part : ~500mm
 Inner diameter of present transition cylinder : 580mm
Stringing with tension can be done from outer layer.
 Two-way method ( Belle-CDC ) is not necessary.
Discussion with technical stuffs

We just started discussion with KEK
technical stuffs.
 Calculation of deformation and stress
 Support method
 etc

Need more man power.
My Personal Plan for Construction
Backup Slides
Hit rate
Apr.-5th ,2005
IHER = 1.24A
ILER = 1.7A
Lpeak = 1.5x1034cm-2sec-1
ICDC = 1mA
Small cell
Inner
Main
10kHz
×20
200kHz
Hit rate at layer 35
410I**2 + 1400*I + 80
740I**2 + 470*I + 80
3000
1600
HER
1400
LER
2500
H it Rate(Hz)
1200
H it rate(Hz)
Dec.,2003
1000
800
600
2000
1500
1000
400
500
200
0
0
0
0.2
0.4
0.6
0.8
HER Beam Current(A)
1
IHER = 4.1A Hit rate = 13kHz
ILER = 9.4A Hit rate = 70kHz
In total 83kHz
0
0.5
1
1.5
LER Beam Current(A)
Dec., 2003 : ~5kHz
Now
: ~4kHz
2
Simulation Study for Higher Beam Background
by K.Senyo.
MC +BGx1
MC+BGx20
Talk by T. Kawasaki
BG effect on analysis
J /  ( mm ) K S (    )
B Eff
Ratio-1
Nominal
56.8 %
0.0 %
×5 BG
56.0 %
×20 BG
49.0 %
B Eff
Ratio-1
Nominal
6.48
0.0 %
-1.5 %
×5 BG
5.69
-12.2 %
-13.8 %
×20 BG
2.28
-64.9 %
With 40% shorter shaping
×20 BG
51.4 %
D* D* ( D*  D s , D  K 3 )
With 40% shorter shaping
×20 BG
-9.5 %
Preliminary




3.86
-40.5 %
By H.Ozaki
Major loss come from low tracking efficiency on slow particles.
Efficiency loss on high multiplicity event is serious.
Pulse shape information by FADC readout can save efficiency.
SVT standalone tracker will be a great help (not included in this study).
Jan24-26, 2008
BNM2008
Atami, Japan
18
Background effect on tracking
H. Ozaki
BNM2008
D* D* ( D*  D s , D  K 3 )
Many low momentum tracks, the hardest case for tracking
Gain in reconstruction efficiency of BgD*D*
Tracker
BKG
Belle
×5 BG
×20 BG
Belle
e=4.3%
0% (definition)
Software
update
+SVD tracker
e=7.1%
e=11.9%
+65%
+177%
e=6.3%
e=11.2%
+47%
+160%
e=3.8%
e=8.8%
–12%
+105%
Excellent with help of SVD
19
Idea for upgrade

In order to reduce occupancy,
Smaller cell size
 A new small cell drift chamber was constructed and installed.
 It has been working, well.
Faster drift velocity
 One candidate : 100% CH4
 Results show worse spatial resolution due to a large
Lorentz angle.
 A beam test was carried out under 1.5T magnetic field.
 So far, no other good candidate.
Small Cell Drift Chamber
Photo of small cell chamber
Just after wire stringing
Installation in 2003 summer
XT Curve & Max. Drift Time
Normal cell(17.3mm)
Small cell(5.4mm)
Chamber Radius

Inner radius
 Physics : Vertexing efficiency using Ks
 SVD determines the boundary.
 At present, the boundary is 15cm in radius.

Outer radius
 New barrel PID device determines the outer radius.
 At present, 115cm is selected, tentatively.

The boundary condition is important to
start construction.
Basically, CDC can manage any radius.
Wire configuration 1
Super-layer structure
 6 layers for each super-layer

 at least 5 layers are required for track reconstruction.
 Even number is preferred for preamp arrangement on
support board to shorten signal cable between feedthrough and preamp.

Additional two layers in inner most superlayer and outer super-most layer.
 Higher hit rate in a few layers near wall.
 Inner most layer and outer most layer are consider as
active guard wire.
Wire configuration 2

9 super-layers : 5 axial + 4 stereo(2U+2V)
A 160*8, U 160*6, A 192*6, V 224*6,
A 256*6, U 288*6, A 320*6, V 352*6, A 388*8
Number of layers : 58
 Number of total sense wires : 15104
 Number of total wires : ~60000

Deformation of endplate

Number of wires increase by factor 2.
 Larger deformation of endplate is expected.
 It may cause troubles in a wire stringing process and other occasions.

Number of holes increases, but a chamber radius also
enlarges. Cell size is changing as a function of radius to
reduce number of wires.
 The fraction of holes respect to total area is not so different, as comparing
with the present CDC.
 11.7% for present CDC
 12.6% for Super-Belle CDC

In order to reduce deformation of endplates,
 The endplate with a different shape is considered.
 Wire tension of field wires will be reduced.

Anyway, we can arrange the wire configuration and can
make a thin aluminum endplate.
Expected performance

Occupancy
Hit rate : ~100kHz  ~5Hz X 20
Maximum drift time : 80-300nsec
Occupancy : 1-3%  100kHz X 80-300nsec = 0.01-0.03

Momemtum resolution(SVD+CDC)
 sPt/Pt = 0.19Pt  0.30/b[%] : Conservative
 sPt/Pt = 0.11Pt  0.30/b[%] : Possible  0.19*(863/1118)2

Energy loss measurement
6.9% : Conservative
6.4% : Possible  6.9*(752/869)1/2
About readout electronics

At present,
 S/QT + multi-hit TDC
 S/QT : Q to Time conversion
 FASTBUS TDC was replaced with pipeline COPPER TDC.

Three options,
 High speed FADC(>200MHz)
 Pipeline TDC + Slow FADC(~20MHz)
 ASD chip + TMC(or new TDC using FPGA) + slow FADC near
detector.
 ASIC group of KEK Detector Technology Project is developing new
ASD chip.
 New TDC using FPGA is one candidate for TDC near detector.
Summary

When Belle group decides the upgrade plan, we
can start construction of the new chamber soon.
 It takes three years to construct the chamber.

Outer radius( and inner radius) should be fixed as
soon as possible.
 Barrel PID determines the schedule.
 Inner radius should be determined by SVD.
 Supporting structure should be discussed.

One big worry is man power.
 I hope many people join us when the upgrade plan starts.
Gain degradation
Radiation Damage Test
Total accumulated charge on sense wire(C/cm)
a: ’93 Plastic tube
d: ’94 SUS tube
b: ’93 Plastic tube + O2 filter e: ’94 SUS tube + O2 filter
c: ’94 Plastic tube
f: ’94 Plastic tube
Test chamber and beam test

A test chamber with new cell structure was
constructed.
 Part of inner most 20 layer( 8 layers with small cell + 12 layers with
normal cell)

A beam test was carried out in the beginning of
June at 2 beam line of 12GeV PS.
 We confirmed the simulation for pure CH4 is correct. Velocity under
1.5T is not faster than the present gas and the drift line is largely
distorted due to larger Lorentz angle.
 Similar performance could be obtained using new S/QT module with
less dead time.
 Many data were taken using 500MHz FADC, which was developed
by KEK electronics group. Now, a student is analyzing data. We
hope to get information about minimum necessary sampling speed
for timing and dE/dx measurement.
xt curve for new gas(7mm cell)
He/C2H6 = 50/50
100nsec
Distance from wire (cm)
Pure CH4
100nsec
Distance from wire (cm)
Drift Velocity

Two candidate gases
were tested.
 CH4 and He-CF4

In case of He-CF4, higher
electric field is necessary
to get fast drift velocity.

In case of CH4, faster drift
velocity by factor two or
more can be obtained,
even in rather lower
electric field.
dE/dx Resolution

The pulse heights for
electron tracks from 90Sr
were measured for
various gases.

The resolutions for CH4
and He(50%)C2H6(50%) are same.

The resolution for HeCF4 is worse than Arbased gas(P-10).
Wire chamber

Wire chamber is a good device for the central
tracker.




Less material  Good momentum resolution.
Cheap  It is easy to cover a large region.
Established technology  Relatively easier construction.
Many layers  Provide trigger signals and particle
ID information.

Wire chamber can survive at Super-KEKB.
 Our answer does not change after the last WS in
2004.
 The beam background became smaller even for higher beam
current and higher luminosity.
 We recognize the luminosity term is small, clearly.
CDC Total Current

Maximum current is
still below 1.2mA,
even for higher
stored current and
higher luminosity.

Vacuum condition is
still improving.
 Thanks KEKB people for
hard work.
 I hope there is still room
to improve vacuum
condition further.
Luminosity Dependences
Feb, 2004
CDC BG did not change!
Inner most
Middle
Outer
Occupancy
Random trigger
Luminosity
No. of
1034cm-2sec-1 channel
NTotal
Readout
time
(msec)
Belle
1.5
8464
6
Babar
0.8
7104
2
Occ. =
NHit/NTotal
(%)
Occ./Time
(%/msec)
Max. drift
time
(msec)
Q>0
Q>50
NHit
-
~700
300
~350
Occ./Time Normalized
x Max. Drift by Lum.(%)
time (%)
Belle
3.5
0.58
0.4
0.23
0.15
Babar
4.9
2.45
~0.6
1.47
1.84
x20 Bkgd in Belle CDC ~ x3 Bkgd in Babar DCH
at HL6 in KEK
Curved Endplate

Deformation of endplate due to wire
tension was calculated at design stage of
present Belle CDC (Total tension: 3.5 Ton).
Deformation(mm)
35.2
2.03
1.31
Present
New
Weight

Endplate
 Al, Thickness : 10mm (12mm)
 110kgx2 = 220kg (264kg)

Outer Cylinder
 CRRP, Thickness : 5mm
 210kg

Electronics Board
 G10, 48ch/board
 0.3kgx315 = 95kg
Present support
Calculation of deformation and etc

Deformation of Aluminum endplate
 Thickness of endplate 10mm  12mm
 Deformation 1/t3
 Tension of field wire
1  0.58
120g  80g
 Gravitational sag, Sense : 120mm(80g), Field:300mm(80g)
 Total tension 4.8ton

Stress calculation
 Thickness of outer cylinder CFRP：mm
 Transition structure between endplate and outer cylinder

Support structure
 Structure for wiring jig
 Simpler one as compared with Belle-CDC

Etc.
Installation

Cathode installation
in vertical direction
Removing and installation
can be done using similar
small bar in horizontal
direction.
CDC installation in horizontal direction
Signal Shape
Each signal shapes are
not same.
 Rise time : ~10sec
 Pulse width : ~200nsec.
 Maximum drift time :
~300nsec

Timing resolution

Good timing resolution
for the drift time
measurement is key
item.
250MHz sampling is
not good enough.
 Present leading edge
measurement shows 130mm
resolution.
 1nsec resolution is required.
FADC test
Spatial resolution (m m)

700
600
500
400
300
200
100
0
Before correction
After correction
0
10
20
30
Sampling width (nsec)
40


Slow sampling rate
is good enough for
energy loss
measurement.
20MHz is OK.
分解能（%）
measurement (%)
dE/dx Resolution
Sampling rate for energy loss measurement
12
10
8
6
4
2
ns
0
0
100
200
300
サンプリングレート（1/T）
Sampling
width (nsec)
Purposes of the Readout board Prototype

A study of the CDC readout scheme
Charge measurements by FADC
Drift time measurements by FPGA base TDC
A evaluation of ASB for CDC readout
 A study of the noise diffusion from the
readout board to CDC
 We hope to study about CDAQ/Front-end
data transport.

ASB part diagram

ASB
 Amp. Shaper Buffer
 4ch/chip
 Gain :
 -360mV/pC ~ -1400mV/pC
 (4 step variable)
 Power consumption : ~18mA
LOGIC part
diagram
CLK
For GFP
RocketIO
GFP
16
LVDS
8 pairs
ASB
Discriminator
5
FADC
Ti
ADS5287
16
TDC
(with FIFO)
De-serializer
CONTROL 3x4
TIMING LVDS 4x4 pairs
RocketIO
GFP
SFP
(Optical connector)
LVDS 2 pairs
SFP
(Optical connector)
LVDS 4 pairs
CLK
50MHz
15 100base
CONTROL
LVDS
8 pairs
ASB
Discriminator
FADC
Ti
ADS5287
DAC
(Vth)
5
Vertex-5 LXT
(XC5VLX50T, IO:360pin)
LVDS
CLKs
8
PHY
48 Spertan3A
SiTCP
ASB
Discriminator
RJ-45
FIFO
LVDS
CLKs
ASB
Discriminator
LVDS 2 pairs
Sampling CLK
20~40 MHz
CLK
125MHz
CLK
42.33MHz
PUSH
SW
4
8
16
8
TEST PIN
32
DIP-SW
3
LED
DIP-SW
TEST PIN
RJ-45
LEMO
LEMO
LEMO
LEMO
Schedule plan
2008/11
Specification design
design and drawing the circuit
2008/11,12
2008/12 end
2009/2
2009/3
ASD part (T.Taniguchi-san)
Digital part (M.Saito-san)
order the substrate
Check the mask pattern
M.Ikeno-san etc…
Start the practical study
Introduction
ATLAS-ASD

 Pre gain 0.8 V/pC , main x 7
ASD buffer
Fe55

T-ASD (Taniguchi-san, ASIC group)
 ~ 7V/pC
Fe55
Conclusion






Gain : T-ASD is smaller (0.6 x
ATLAS ASD, half of Belle
AMP)
Noise level: T-ASD is smaller
Resolution : T-ASD seems to
be better than ATLAS ASD
Rise time is ~ 20 ns for ATLAS
ASD and T-ASD
Saturation : ~ 1.9kV
Beam test using test chamber
and new ASIC chip ~ Apr,
2009
ATLAS ASD
HV=1.6kV
~80mV
HV=1.7kV
~220mV
40ns
HV=1.8kV
~500mV
HV=1.9kV
~600mV
distorted
T-ASD
HV=1.6kV
HV=1.7kV
~50mV
~140mV
40ns
HV=1.8kV
~300mV
HV=1.9kV
~600mV
saturate
Belle AMP (HV=1.8kV)