Transcript Computer Organization

Computer Organization
Computer Organization
This module surveys the physical resources of a
computer system.
– Basic components
CPU
Memory
Bus
I/O devices
– CPU structure
Registers
Processing units
– Instruction cycle
CPU and the Memory
The Central Processing Unit (CPU)
– responsible for instruction execution
– determines how the memory is to be modified
– contains a few data container called registers
The Main Memory
– large collection of data containers
– each is labeled with a positive integer called
its address
For each instruction, the CPU fetches
input data from registers or memory, then
writes output to a register or memory
Instruction Types
Arithmetic and logical instructions apply a
function to input data to produce output
– Addition, logical AND, negation
Control instructions test or compare values
of variables and make decisions about
what instruction is going to be executed
next
– The only output is a possible change in the
register that keeps track of the address of the
next instruction
Fetch-Decode-Execute Cycle
The CPU is endlessly looping through
these steps
– Actual steps will vary from processor to
processor
MIPS R2000 steps
1. instruction fetch & PC update
2. instruction decode & operand load
3. operation execution (control instructions
update PC)
4. memory access
Basic Architecture
Processor (CPU)
Main Memory
CPU
Memory
– volatile
I/O devices
– secondary memory
– communications
– terminals
System Bus
Disk
Network
Controller Controller
Serial Device
Controller
System interconnection
– a bus is used to exchange data and control
information
Interconnection: the bus
Conceptually, a collection
of parallel wires, each of
which is dedicated to
carrying one of
– data
– address
– control (of access to the bus)
Only one component can
“write” to a particular wire
of the bus at a time
data
address
control
Device Controllers
Devices are not
connected directly to
the system bus
Each device has a
device controller
between it and the
system bus
One controller may
have multiple devices
For example: SCSI
devices, IDE devices,
CPU
Memory
System Bus
Disk
Network
Controller Controller
Serial Device
Controller
I/O Devices
Each device has a
buffer which
mediates data
transfer.
Transfer between
memory and
devices is limited by
the size and speed
of the data bus.
For example,
though a disk reads
data to its buffer
one block at a time,
CPU
Memory
System Bus
buffer
Device
Controller
Memory
Can be viewed as a linear
array of data values
– Indexed by non-negative
integers: addresses
– Memory is usually byte
addressable
each byte has its own unique
address
– The word-size (width of the
data bus) of a system is often
more than 1 byte
231 –1
Central Processing Unit
Arithmetic logic unit (ALU)
– performs arithmetic and logic operations
Control unit
– reads and decodes
instructions
– initiates execution of
instruction by proper
component
Registers
– some have special purpose
CPU
ALU
Control
PC PSW CP
SP
DL
IR
AR DP CL
v0
a0
s0
s3
s1
s2
CPU Design
CPU design defines what the computer’s
instruction do and how they are specified (the
instruction set)
The instruction set determine the computer’s
capabilities.
– All computers should be able to implement any logical
function on a finite number of bits.
Such instruction sets are said to be complete
– Not all complete designs are equal!
Execution time may vary…
A computer’s machine language is determined
by its manufacturer
The assembly language is also formally defined
$zero
1
$at
2
$v0
3
$v1
4
$a0
7
$a3
8
$t0
…
15
$t7
16
$s0
…
 Return values from functions
 Pass parameters to functions
…
23
 Value is always zero
 Used by the assembler for address
$s7
24
$t8
25
$t9
26
$k0
27
$k1
28
$gp
29
$sp
30
$fp
31
$ra
`
 Caller saved register
 Callee saved registers
 More caller saved registers
 Used by the kernel (operating system)
MIPS ALU Registers
0
 Global pointer
 Stack pointer
 Frame pointer
 Return address (used by JAL instruction)