Transcript Digital Image Processing

CoE3DJ4
Digital Systems Design
Parallel I/O Ports
I/O devices
• Peripheral devices (also called I/O devices) are pieces of
equipment that exchange data with a CPU
• Examples: switches, LED, CRT, printers, keyboard, keypad
• Speed and characteristics of these devices are very different
from that of CPU so they cannot be connected directly
• Interface chips are needed to resolve this problem
• Main function of an interface chip is to synchronize data
transfer between CPU and I/O device
• Data pins of interface chip are connected to CPU data bus and
I/O port pins are connected to I/O device
I/O devices
• Since a CPU may have multiple I/O devices, CPU data bus
may be connected to data buses of multiple interface
• An address decoder is used to select one device to respond to
the CPU I/O request
• Different CPUs deal with I/O devices differently
• Some CPUs have dedicated instructions for performing input
and output operations (isolated I/O)
• Other CPUs use the same instruction for reading from
memory and reading from input devices, as well as writing
data into memory and writing data into output devices
(memory-mapped I/O)
• MCS-51 (8051) is memory mapped
Synchronization of CPU and interface chip
•
There must be a mechanism to make sure that there are valid
data in the interface chip when CPU reads them
• Input synchronization: two ways of doing this
1. Polling method
– interface chip uses a status bit to indicate if it has valid data for CPU
– CPU keeps checking status bit until it is set, and then reads data from
interface chip
– Simple method, used when CPU has nothing else to do
2. Interrupt driven method: interface chip interrupts the CPU
when it has new data. CPU executes the ISR
Synchronization of CPU and interface chip
• Output synchronization: two ways of doing this
1. Polling method
– interface chip uses a status bit to indicate that the data register is
empty
– CPU keeps checking status bit until it is set, and then writes data into
interface chip
2. Interrupt driven method: interface chip interrupts the CPU
when it data register is empty. CPU executes the ISR
Synchronization of interface chip & I/O device
•
Methods used to synchronize data transfer between interface
chip and I/O devices:
1. Brute force method: interface chip returns voltage levels in
its input ports to CPU and makes data written by CPU
directly available on its output ports
•
All 8051 port can perform brute force I/O
2. Strobe method:
– During input, the I/O device activates a strobe signal when data are
stable. Interface chip latches the data
– For output, interface chip places output data on output port. when
data is stable, it activates a strobe signal. I/O device latches the data
3. Handshake method: two handshake signals are needed
– One is asserted by interface chip and the other by I/O device
8051 ports
8051 ports
• Ports 1, 2, and 3 have internal pullups, and Port 0 has open
drain outputs.
• To be used as an input, the port bit latch must contain a 1,
which turns off the output driver FET.
• For Ports 1, 2, and 3, the pin is pulled high by a weak internal
pullup, and can be pulled low by an external source.
• Port 0 differs in that its internal pullups are not active during
normal port operation (writing a 1 to the bit latch leaves both
output FETs off, so the pin floats).
8051 I/O Ports: Hardware Specs
• P0 is open drain.
– Has to be pulled high by external 10K resistors.
– Not needed if P0 is used for address lines
• P1, P2, P3 have internal pull-ups
• Port fan- out (number of devices it can drive) is limited.
– Use buffers (74LS244, 74LS245,etc) to increase drive.
• P1, P2, P3 can drive up to 4 LS-TTL inputs
8051 - Switch On I/O Ports
• Case-1:
– Gives a logic 0 on switch
close
– Current is 0.5ma on switch
close
• Case-2:
– Gives a logic 1 on switch
close
– High current on switch
close
• Case-3:
– Can damage port if 0 is
output
Simple input devices
• DIP switches usually have 8
switches
• Use the case-1 from previous
page
• Sequence of instructions to
read a value from DIP
switches:
mov
mov
P1,#FFH
A,P1,
Interfacing a Keypad
• A 16-key keypad is built as shown in the figure below.
– 16 keys arranged as
a 4X4 matrix.
– Must “activate”
each row by placing
a 0 on its R output.
• Then the column
output is read.
• If there is a 0 on
one of the column
bits, then the button
at the column/row
intersection has
been pressed.
• Otherwise, try next row.
– Repeat constantly.
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
R1
R2
R3
R4
0
C1
C2
C3
C4
Interfacing a Keypad
• Algorithm:
–
–
–
–
Drive a “0” on a row
Read all the columns
If any key had been pressed, its column will be “0”, else 1
Keep repeating in a loop for each successive row
• Example:
– Switch 4 is pressed
• R2 0, C1:C4 = 1111
• R3 0, C1:C4 = 1110
Bouncing Contacts
• Push-button switches, toggle switches, and electromechanical
relays all have one thing in common: contacts.
• Metal contacts make and break the circuit and carry the
current in switches and relays. Because they are metal,
contacts have mass.
• Since at least one of the contacts is movable, it has
springiness.
• Since contacts are designed to open and close quickly, there is
little resistance (damping) to their movement.
Bouncing
• Because the moving contacts have mass and springiness with
low damping they will be "bouncy" as they make and break.
• That is, when a normally open (N.O.) pair of contacts is
closed, the contacts will come together and bounce off each
other several times before finally coming to rest in a closed
position.
• The effect is called "contact bounce" or, in a switch, "switch
bounce”.
Why is it a problem?
• If such a switch is used as a source to an edge-triggered input
such as INT0, then the MCS-51 will think that there were
several “events” and respond several times.
• The bouncing of the switch may last for several milliseconds.
– Given that the MCS-51 operates at microsecond speed, a short ISR
may execute several times in response to the above described
bounciness.
Hardware Solution
• The simplest hardware solution uses an RC time constant to
suppress the bounce. The time constant has to be larger than
the switch bounce and is typically 0.1 seconds.
• As long as capacitor voltage does not exceed a threshold
value, the output signal will be continued to be recognized as
a logic 1.
• The buffer after the switch produces a sharp high-to-low
transition.
Vcc
OUT
Software Solution
• It is also possible to counter the bouncing problem using
software.
• The easies way is the wait-and-see technique
– When the input drops, an “appropriate” delay is executed (10 ms), then
the value of the line is checked again to make sure the line has stopped
bouncing.
Interfacing a Keypad
scan: mov
jnb
scan1: jnb
scan2: jnb
scan3: jnb
scan4: mov
jnb
…..
…..
…..
P1,#EFH
P1.0,db_0
P1.1,db_1
P1.2,db_2
P1.3,db_3
P1,#DFH
P1.0,db_4
F
E
D
B
A
9
8
7
6
5
4
3
2
8051
C
1
P1.7
P1.6
P1.5
P1.4
0
P1.3
P1.2
P1.1
P1.0
Interfacing a Keypad
db_0:
temp_1:
db_1:
temp_2:
…..
…
…..
lcall
jb
mov
ljmp
ljmp
lcall
jb
mov
ljmp
ljmp
wt_10ms
P1.0,temp_1
A, #0
get_code
scan1
wt_10ms
P1.1,temp_2
A, #1
get_code
scan2
Interfacing a Keypad
get_code:
key_tab:
mov
movc
ljmp
db
END
DPRT, #key_tab
A, @A+DPRT
scan
‘0123456789ABCDEF’
Simple output devices
•
Case-1
– LED is ON for an output of
zero
– Most LEDs drop 1.7 to 2.5
volts and need about 10ma
– Current is (5-2)/470
•
Case-2
– Too much current
– Failure of Port or LED
•
Case-3
– Not enough drive (1ma)
– LED too dim
The 7-Segment Display
• The 7-segment display is nothing but 7 LEDs arranged to
form the number 8.
– By turning on and off the appropriate segments (LEDs), different
combinations can be produced.
– The 7-segment display is useful for displaying the digits 0 through 9,
and some characters.
a
f
b
g
e
c
d
The 7-segment Display (Contd.)
• 7-segment displays come in 2 configurations:
Common Anode
Common Cathode
• As we have seen when we discussed interfacing the basic
LED, it would be preferable to connect the cathode of each
diode to the output pin.
– Therefore, the common anode variety would be better for our
interfacing needs.
Interfacing a 7-segment display to the 8051
• Also, as seen with interfacing the LED, a resistor will be needed to control
the current flowing through the diode.
– This leaves two possibilities:
• Case 2 would be more appropriate as case 1 will produce different brightness
depending on the number of LEDs turned on.
LCD Interfacing
• Liquid Crystal Displays (LCDs) have become a cheap and easy way to
display text for an embedded system
– Various configurations (1 line by 20 characters upto 8 lines by 80 characters).
•
•
•
•
LCD needs a driving circuit to work.
Driving circuit and LCD are often integrated into a single chip
Hitachi LM015 can display one line of 16 characters
The display has one register into which commands are sent and one
register into which data to be displayed are sent
• Two registers are differentiated by the RS input
• Data lines (DB7-DB0) are used to transfer both commands (clearing,
cursor positioning, etc) and data (character to be displayed)
Alphanumeric LCD Interfacing
• Pinout
Microcontroller
– 8 data pins D7:D0
– RS: Data or Command
Register Select
– R/W: Read or Write
– E: Enable (Latch data)
E
R/W
RS
communications
bus
DB7–DB0
8
• RS – Register Select
– RS = 0  Command Register
– RS = 1  Data Register
• R/W = 0  Write, R/W = 1  Read
• E – Enable
– Used to latch the data present on the data pins.
• D0 – D7
– Bi-directional data/command pins.
– Alphanumeric characters are sent in ASCII format.
LCD
controller
LCD Module
LCD Commands
• The LCD’s internal controller can accept several commands and modify
the display accordingly. These commands would be things like:
– Clear screen
– Return home
– Decrement/Increment cursor
• After writing to the LCD, it takes some time for it to complete its internal
operations. During this time, it will not accept any new commands or data.
– We need to insert time delay between any two commands or data sent to LCD
Interfacing LCD with 8051
8051
LM015
P3.4
RW
P3.5
E
P3.3
RS
P1.7-P1.0
D7-D0
Interfacing LCD with 8051
mov A, command
call cmd
delay
mov A, another_cmd
call cmd
delay
mov A, #’A’
call data
delay
mov A, #’B’
call data
delay
….
Command and Data Write Routines
data: mov P1, A ;A is ascii data
setb P3.3 ;RS=1 data
clr P3.4 ;RW=0 for write
setb P3.5 ;H->L pulse on E
clr P3.5
ret
cmd: mov P1, A ;A has the cmd word
clr P3.3 ;RS=0 for cmd
clr P3.4 ;RW=0 for write
setb P3.5 ;H->L pulse on E
clr P3.5
ret
8255
• 8051 has very limited number of I/O ports
• If more I/O ports are needed one solution is to add parallel
interface chip(s)
• Intel’s programmable peripheral interface (PPI) chip 8255 is a
parallel interface chip that can be added to 8051 to expand
number of parallel ports
• Besides limited number of I/O ports, 8051 does not have any
I/O port with handshaking capability
• By using 8255 in connection with 8051 we can add
handshaking capability
8255
• 8255 – Programmable Peripheral Interface (PPI)
–
–
–
–
Provides 3 eight bit ports A, B and C
Port C can be used as two 4 bit ports CL and CU
Ports have handshaking ability
Two address lines A0, A1 and a Chip select CS
•
•
•
•
00b selects Port A
01b selects Port B
10b selects Port C
11b selects an internal control register (CR)
8255
8255 Operating Modes
•
Control register controls overall operation of 8255
–
Depending on its most significant bit, control register has two functions:
1. Mode definition: when set to 1
2. Bit set reset: when reset to 0
•
Mode 0 : Simple I/O
–
•
Mode 1: I/O with Handshake
–
–
•
A and B can be used for I/O
C provides the handshake signals
Mode 2: Bi-directional with handshake
–
–
•
Any of A, B, CL and CU can be programmed as input or output
A is bi-directional with C providing handshake signals
B is simple I/O (mode-0) or handshake I/O (mode-1)
BSR (Bit Set Reset) Mode
–
C alone is available for bit mode access
•
Allows single bit manipulation for control applications.
8255 Mode Definition Summary
8255 Configuration
•
•
8255 can be configured by writing a control-word in CR register
CR definition
– D7 : 1I/O mode, 0  BSR
– D6,D5 : Mode selection for A and CU
• 00  Mode0, 01  Mode1, 1x  Mode2
– D4 : Port A control
• 1  A input, 0  A output
– D3 : Port CU control
• 1  CU input, 0  CU output
– D2 : Port B Mode selection
• 0  B is in mode 0, 1  B is in mode 1
– D1 : Port B control
• 1  B input, 0  B output
– D0 : Port CL control
• 1  CL input, 0  CL output
8255 Control Word
Mode 0
• Provides simple input and output operations for each of the
three ports.
– No “handshaking” is required, data is simply written to or read from a
specified port.
– Two 8-bit ports and two 4-bit ports.
– Any port can be input or output.
– Outputs are latched.
– Inputs are not latched.
Mode 1
• Strobed Input/Output.
• Provides a means for transferring I/O data to or from a specified port in
conjunction with strobes or “handshaking” signals.
– In mode 1, Port A and Port B use the lines on Port C to generate or accept
“handshaking” signals.
• Mode 1 Basic functional Definitions:
– Two Groups (Group A and Group B).
– Each group contains one 8-bit data port and one 4-bit control/data port.
– The 8-bit data port can be either input or output. Both inputs and outputs are
latched.
– The 4-bit port is used for control and status of the 8-bit data port.
Mode 1 – Control Signals
• Input Control Signal Definition
– STB (Strobe Input). (C4 for A, C2 for B)
• A “low” on this input loads data into the input latch.
– IBF (Input Buffer Full F/F) (C5 for A, C1 for B)
• A “high” on this output indicates that the data has been loaded into the
input latch; in essence, an acknowledgement from the 8255 to the device.
– INTR (Interrupt Request) (C3 for A, C0 for B)
• A “high” on this output can be used to interrupt the CPU when an input
device is requesting service.
Mode 1 – Control Signals
• Output Control Signal Definition
– OBF (Output Buffer Full F/F). (C7 for A, C1 for B)
• The OBF output will go “low” to indicate that the CPU has written data
out to the specified port.
– A signal to the device that there is data to be read.
– ACK (Acknowledge Input). (C6 for A, C2 for B)
• A “low” on this input informs the 8255 that the data from Port A or Port B
has been accepted.
– A response from the peripheral device indicating that it has read the data.
– INTR (Interrupt Request). (C3 for A, C0 for B)
• A “high” on this output can be used to interrupt the CPU when an output
device has accepted data transmitted by the CPU.
Functions of Port C pins in Mode 1
Pin
Port A as
input
Port A as
output
Port B as
input
Port B as
output
PC7
I/O
OBF
NA
NA
PC6
I/O
ACK
NA
NA
PC5
IBF
I/O
NA
NA
PC4
STB
I/O
NA
NA
PC3
INTR
INTR
NA
NA
PC2
NA
NA
STB
ACK
PC1
NA
NA
IBF
OBF
PC0
NA
NA
INTR
INTR
Mode 1
Mode 2 - Strobed Bidirectional Bus I/O
• Provides a means for communicating with a peripheral device on a single
8-bit bus for both transmitting and receiving data (bidirectional bus I/O).
• “Handshaking” signals are provided to maintain proper bus flow discipline
in a similar manner to mode 1.
• MODE 2 Basic Functional Definitions:
–
–
–
–
Used in Group A only.
One 8-bit, bi-directional bus port (Port A) and a 5-bit control port (Port C).
Both inputs and outputs are latched.
The 5-bit control port (Port C) is used for control and status for the 8-bit, bidirectional bus port (Port A).
Mode 2
• Output Operations
– OBF (Output Buffer Full). The OBF output
will go low to indicate that the CPU has
written data out to port A.
– ACK (Acknowledge). A low on this input
enables the tri-state output buffer of Port A to
send out the data. Otherwise, the output buffer
will be in the high impedance state.
• Input Operations
– STB (Strobe Input). A low on this input loads
data into the input latch.
– IBF (Input Buffer Full F/F). A high on this
output indicates that data has been loaded into
the input latch.
Pin
Function
PC7
OBF
PC6
ACK
PC5
IBF
PC4
STB
PC3
INTR
PC2
I/O
PC1
I/O
PC0
I/O
BSR Mode
• If used in BSR mode, then the bits of port C can be set or
reset individually.
Interfacing 8255 with 8051
• CS is used to interface 8255 with 8051
• If CS is generated from lets say Address
lines A15:A12 as follows,
A15:A13 = 110
• Address of 8255 is 110 xxxxx xxxx xx00b
• Base address of 8255 is
– 1100 0000 0000 0000b=C000H
• Address of the registers
–
–
–
–
A = C000H
B = C001H
C = C002H
CR = C003H
Interfacing 8255 with 8051
8051
74F138 (3 to 8 decoder)
A2
A1
A0
8255
CS
O1
O0
AD7-AD0
A1
A0
D7-D0
74F373
(Latch with Three-State Outputs)
D7-D0
8255 Usage: Simple Example
• 8255 memory mapped to 8051 at address C000H base
– A = C000H, B = C001H, C = C002H, CR = C003H
• Control word for all ports as outputs in mode0
– CR : 1000 0000b = 80H
• Code segment
test:
repeat:
mov
mov
movx
mov
mov
movx
inc
movx
inc
movx
cpl
acall
sjmp
A, #80H
DPTR, #C003H
@DPTR, A
A, #55h
DPTR, #C000H
@DPTR, A
DPTR
@DPTR, A
DPTR
@DPTR, A
A
MY_DELAY
repeat
; control word
; address of CR
; write control word
; will try to write 55 and AA alternatively
; address of PA
; write 55H to PA
; now DPTR points to PB
; write 55H to PB
; now DPTR points to PC
; write 55H to PC
; toggle A (55AA, AA55)
; small delay subroutine
; for (1)