Transcript ECE 353 Lesson Slides

ECE 353
Introduction to
Microprocessor Systems
Week 3
Michael G. Morrow, P.E.
Topics
Code Generation and Debugging Tools
ARM7TDMI Microprocessor


Organization
Programming
Code Generation
Programming Language Characteristics
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High-Level Language (HLL)
Assembly Language
Machine Language
Assembler Functions

What does an assembler do?
Assembly Language
Assembler Types
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Native assembler
Cross-assembler
General Instruction Syntax
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Label
Mnemonic
Operands
Comments
Key ARM Assembler Directives
Code
Generation
Process –
Generic
EDITOR
source f ile (*.s)
ASSEMBLER
Other object files
f rom assembler
or HLL compilers
list f ile (*.lst)
relocatable object file (*.o)
LINKER
linker map f ile (*.map)
relocatable linked object f ile
LOCATOR
locator map f ile (*.map)
absolute executable f ile (*.axf )
HEX Conversion
HEX-ASCII object f ile (*.hex)
blank device
DEVICE
PROGRAMMER
programmed device
Code
Generation
Process –
ECE 353
and
ECE 315
EDITOR
source f ile (*.s)
ASSEMBLER
Other object f iles
f rom assembler
or HLL compilers
list file (*.lst)
relocatable object f ile (*.o)
LINKER/
LOCATOR
map f ile (*.map)
absolute executable f ile (*.axf )
ADuC7026
Simulator
HEX
conversion
ULink JTAG Pod
Device
Programmer
ADuC7026
Hardw are
Hardware
for
Sample
Program
Source Code File
; Filename:
; Author:
; Description:
sample.s
ECE 353 Staff
sample program for week 3 lecture
; do **NOT** use this as the basis for any programming!
EXPORT
IOPORT_ADDRESS
AREA
ARM
Reset_Handler
LDR
Loop
LDR
LDR
LSL
MVN
STR
NOP
B
aLoop
aPort
DCD
DCD
END
Reset_Handler
EQU
;make available to linker
0x80001000
Reset, CODE, READONLY
PC, aLoop
;jump absolute
R0,
R1,
R1,
R1,
R1,
;load address of port
;read switch state
;shift left 8 bits to align
;complement
;write LEDs
;do nothing
;repeat forever
aPort
[R0]
#8
R1
[R0]
Loop
Loop
IOPORT_ADDRESS
Assembler Listing File (1)
4 00000000
5 00000000
6 00000000
; do **NOT** use this as the basis for any programming!
EXPORT
7 00000000
8 00000000 80001000
IOPORT_ADDRESS
EQU
9 00000000
10 00000000
AREA
11 00000000
ARM
12 00000000
13 00000000
Reset_Handler
14 00000000 E59FF018
LDR
15 00000004
Loop
16 00000004 E59F0018
LDR
17 00000008 E5901000
LDR
18 0000000C E1A01401
LSL
19
20
21
22
23
24
00000010
00000014
00000018
0000001C
00000020
00000020
E1E01001
E5801000
E1A00000
EAFFFFF8
00000000
aLoop
25 00000024 80001000
aPort
26 00000028
27 00000028
Reset_Handler ;make available t
o linker
0x80001000
Reset, CODE, READONLY
PC, aLoop
R0, aPort
R1, [R0]
R1, #8
;load address of port
;read switch state
;shift left 8 bits
to align
;complement
;write LEDs
;do nothing
;repeat forever
MVN
STR
NOP
B
R1, R1
R1, [R0]
DCD
Loop
DCD
IOPORT_ADDRESS
END
Loop
Assembler Listing File (2)
Command Line: --debug --xref --device=DARMAD --apcs=interwork -osample.o -IC:\K
eil\ARM\INC\ADI --list=sample.lst sample.s
ARM Macro Assembler
Relocatable symbols
Page 1 Alphabetic symbol ordering
Loop 00000004
Symbol: Loop
Definitions
At line 15 in file sample.s
Uses
At line 22 in file sample.s
At line 24 in file sample.s
Reset 00000000
Symbol: Reset
Definitions
At line 10 in file sample.s
Uses
None
Comment: Reset unused
Reset_Handler 00000000
Symbol: Reset_Handler
Definitions
At line 13 in file sample.s
Uses
At line 6 in file sample.s
Comment: Reset_Handler used once
Assembler Listing File (3)
Symbol: aLoop
Definitions
At line 24 in file sample.s
Uses
At line 14 in file sample.s
Comment: aLoop used once
aPort 00000024
Symbol: aPort
Definitions
At line 25 in file sample.s
Uses
At line 16 in file sample.s
Comment: aPort used once
5 symbols
ARM Macro Assembler
Absolute symbols
Page 1 Alphabetic symbol ordering
IOPORT_ADDRESS 80001000
Symbol: IOPORT_ADDRESS
Definitions
At line 8 in file sample.s
Uses
At line 25 in file sample.s
Comment: IOPORT_ADDRESS used once
1 symbol
321 symbols in table
Disassembly Window
aLoop
aPort
0x00080000
0x00080004
0x00080008
0x0008000C
0x00080010
0x00080014
0x00080018
0x0008001C
0x00080020
0x00080024
0x00080028
0x0008002C
0x00080030
0x00080034
E59FF018
E59F0018
E5901000
E1A01401
E1E01001
E5801000
E1A00000
EAFFFFF8
00080004
80001000
00000000
00000000
00000000
00000000
DD
LDR
LDR
MOV
MVN
STR
NOP
B
DD
ANDHI
ANDEQ
ANDEQ
ANDEQ
ANDEQ
0xE59FF018
R0,[PC,#0x0018]
R1,[R0]
R1,R1,LSL #8
R1,R1
R1,[R0]
0x00080004
0x00080004
R1,R0,R0
R0,R0,R0
R0,R0,R0
R0,R0,R0
R0,R0,R0
B/BL{<cond>} <target_address>
RTL: PC  PC + (signed_immediate_24 << 2)
Linker Map File (1)
ARM Linker, RVCT3.0 [Build 942] for uVision [Evaluation]
================================================================================
Section Cross References
================================================================================
Image Symbol Table
Local Symbols
Symbol Name
sample.s
Reset
Loop
Value
Ov
0x00000000
0x00080000
0x00080004
Global Symbols
Symbol Name
Value
Type
Number
Section
ARM Code
Ov Type
Size
0
40
0
Object(Section)
sample.o ABSOLUTE
sample.o(Reset)
sample.o(Reset)
Size
Object(Section)
BuildAttributes$$THUMB_ISAv1$ARM_ISAv4$M$PE$A:L22$X:L11$S22$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL
$OSPACE$EBA8$PRES8$EABIv2 0x00000000
Number
0 anon$$obj.o ABSOLUTE
Reset_Handler
0x00080000
ARM Code
0 sample.o(Reset)
================================================================================
Memory Map of the image
Image Entry point : 0x00080000
Load Region LR_1 (Base: 0x00080000, Size: 0x00000028, Max: 0xffffffff, ABSOLUTE)
Execution Region ER_RO (Base: 0x00080000, Size: 0x00000028, Max: 0xffffffff, ABSOLUTE)
Base Addr
Size
Type
Attr
Idx
E Section Name
Object
0x00080000
0x00000028
Code
RO
1 * Reset
sample.o
Execution Region ER_RW (Base: 0x00010000, Size: 0x00000000, Max: 0xffffffff, ABSOLUTE)
**** No section assigned to this execution region ****
Execution Region ER_ZI (Base: 0x00010000, Size: 0x00000000, Max: 0xffffffff, ABSOLUTE)
**** No section assigned to this execution region ****
Linker Map File (2)
Image component sizes
Code (inc. data)
40
8
RO Data
RW Data
ZI Data
Debug
0
0
0
244
Object Name
sample.o
-----------------------------------------------------------------------40
8
0
0
0
244
Object Totals
0
0
0
0
0
0
(incl. Generated)
0
0
0
0
0
0
(incl. Padding)
-----------------------------------------------------------------------0
0
0
0
0
0
Library Totals
0
0
0
0
0
0
(incl. Padding)
-----------------------------------------------------------------------================================================================================
Code (inc. data)
40
40
8
8
RO Data
RW Data
ZI Data
Debug
0
0
0
0
0
0
244
244
Grand Totals
Image Totals
================================================================================
Total RO Size (Code + RO Data)
Total RW Size (RW Data + ZI Data)
Total ROM Size (Code + RO Data + RW Data)
40 (
0 (
40 (
0.04kB)
0.00kB)
0.04kB)
================================================================================
Hex Record Format
:0400000500080000EF
:020000040008F2
:1000000018F09FE518009FE5001090E50114A0E1AD
:100010000110E0E1001080E50000A0E1F8FFFFEA38
:0800200004000800001000803C
:00000001FF
0x00080000 E59FF018
Record Record Load Address Record Data
Mark Length or 0000
Type
Checksum Record Description
:
04
0000
05
00080000
EF
:
02
0000
04
0008
F2
:
10
0000
00
:
10
0010
00
:
08
0020
00
18F09FE518009FE5 AD
001090E50114A0E1
0110E0E1001080E5 38
0000A0E1F8FFFFEA
0400080000100080 3C
:
00
0000
01
FF
Start linear address
record
Extended linear
address record
Data record
Data record
Data record
End-of-file record
Debugger Basics
So, why is it called debugging, anyway?
Terminology
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Testing
Debugging
Types of errors
Symbolic debugging
UUT/DUT
Typical Debugger Capabilities
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Display/modify machine state
Load/run/halt
Step-into / step-over
Breakpoints
Simulator
Runs on a host computer, and simulates execution
of your code. No actual hardware required.
Strengths
Weaknesses
Native Debugger
Code is executed on a host computer with a
compatible instruction set.
Strengths
Weaknesses
Resident Monitor
Monitor is a stand-alone program that runs on the
UUT, typically communicates over serial interface
to a terminal.
Strengths
Weaknesses
Remote Debugger
Similar to resident monitor, but only small
debugger kernel on UUT. Main debugger software
runs on a host computer connected to the UUT.
Strengths
Weaknesses
In-Circuit Emulator (ICE)
Replaces UUT CPU with hardware that gives full control of
CPU pins (i.e. can run arbitrary bus cycles). Often contain
overlay memory to allow testing of software before system
hardware is available. May clamp over existing CPU that is
soldered in place.
Strengths
Weaknesses
JTAG Emulators
Special serial interface to the device (IEEE 1149.1)
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Boundary scan cell
Boundary scan chain
Emulation (internal) scan chain
Background debug support
Strengths
Weaknesses
Hardware-Assisted Debug
In microprocessors with on-chip nonvolatile
memory (like the ADuC7026), it is not
feasible to set software breakpoints
Debug hardware is added to support
debugging in these conditions
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
Code breakpoint registers
Data breakpoint registers
ARM7 combines both of these into a
watchpoint register set
Code Development Tips
Use structured programming methods

No spaghetti code!
Use descriptive symbols and names
Write comments as you go (or before!)
When fixing assembler errors, fix only the
top one or two and re-assemble – a lot of
the later errors may be due to the first few
When debugging, verify what the registers
are loaded with as compared to what you
think (know?) they should be loaded with

Textbook has a good section on debugging
ARM7TDMI
Processor
Core
ARM7 Operating Modes
User

Normal program execution mode
System

For running operating system tasks at user privilege level
Supervisor
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Protected mode for operating system
Abort
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
Used to implement process and/or memory protection
Two classes of aborts – data abort, prefetch abort
Undefined

Supports software emulation of unsupported instructions and
unimplemented hardware coprocessors
FIQ
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Fast interrupt handling
IRQ
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General purpose interrupt handling
ARM7 Programmers’ Model
R15-R0
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Sixteen general-purpose registers
Special functions

R15 is the Program Counter (PC)
 If R15 is the destination operand, some instructions
will exhibit special behavior for mode changes

R14 is the Link Register (LR)
 For subroutine calls and interrupts/exceptions, the
return address is stored in LR. It must be saved
before calls are made in the subroutine.

R13 is used as the Stack Pointer (SP)
ARM7 Programmers’ Model (cont)
Current Process Status Register (CPSR)
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

Condition code flags (N, Z, C, V)
Interrupt disable bits (I, F)
Thumb mode enable (T)
 Never change directly!


Operating mode select
Reserved bits
 Do not alter the state of these bits for compatibility with future
ARM products

I, F and mode cannot be changed in user mode!
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
NZCV
reserved
9
8
7
6
5
4
3
2
1
I F T mode
0
ARM7 Programmers’ Model (cont)
Suspended Process Status Register (SPSR)

SPSR is only present when the CPU is
operating in one of the exception modes
 Each exception mode has its own SPSR, since
exception handlers may cause other exceptions.

SPSR is a copy of the CPSR immediately before
the exception mode was entered.
 When returning from the exception, the value in
SPSR is used to restore the CPSR to the proper
state for the process that was interrupted.
ARM7 Register Banking
User Mode
Privileged Modes
Exception Modes
User
System
Supervisor
Abort
Undefined
IRQ
FIQ
R0-R7
R0-R7
R0-R7
R0-R7
R0-R7
R0-R7
R0-R7
R8-R12
R8-R12
R8-R12
R8-R12
R8-R12
R8-R12
R8-R12
R13-R14 R13-R14 R13-R14 R13-R14 R13-R14 R13-R14 R13-R14
PC
PC
PC
PC
PC
PC
PC
CPSR
CPSR
CPSR
CPSR
CPSR
CPSR
CPSR
SPSR
SPSR
SPSR
SPSR
SPSR
ARM7 Reset
CPSR



Supervisor mode
I & F set (interrupts disabled)
T cleared (ARM mode)
PC is cleared to 0x00000000 and an
instruction is fetched

This is the bootstrap instruction
All register values except PC and CPSR are
indeterminate
ARM7 Reserved Addresses
0x00000000
0x00000004
0x00000008
0x0000000C
0x00000010
0x00000014
0x00000018
0x0000001C
Reset
Undefined instruction exception
Software interrupt
Prefetch abort exception
Data abort exception
Reserved
Interrupt request (IRQ)
Fast interrupt request (FIQ)
ARM7 Coprocessors
The ARM architecture is designed to support the
addition of tightly-coupled hardware coprocessors


System control processor (CP15)
Floating-point coprocessor
Special instructions are used to read/write
coprocessor registers

If the coprocessor is not implemented, an undefined
instruction exception occurs, permitting software
emulation of the coprocessor functions.
The ADuC7026 does not implement any
coprocessors
ARM7 Condition Codes
Opcode
[31:28]
Mnemonic
extension
Meaning
Condition flag state
0000
EQ
Equal
Z==1
0001
NE
Not equal
Z==0
0010
CS/HS
Carry set / unsigned higher or same
C==1
0011
CC/LO
Carry clear / unsigned lower
C==0
0100
MI
Minus / negative
N==1
0101
PL
Plus / positive or zero
N==0
0110
VS
Overflow
V==1
0111
VC
No overflow
V==0
1000
HI
Unsigned higher
(C==1) AND (Z==0)
1001
LS
Unsigned lower or same
(C==0) OR (Z==1)
1010
GE
Signed greater than or equal
N == V
1011
LT
Signed less than
N != V
1100
GT
Signed greater than
(Z==0) AND (N==V)
1101
LE
Signed less than or equal
(Z==1) OR (N!=V)
1110
AL
Always (unconditional)
Not applicable
1111
(NV)
Never
Obsolete, ARM7TDMI unpredictable
ARM7 Condition Codes (cont)
Things to remember when using conditions

Signed and unsigned arithmetic require
different conditions to get same result
 Unsigned HS equivalent to signed GE


The AL (always) condition is implied if no
condition mnemonic is used
The meaning of the condition is true if op1
cond op2
 CMP R0, R1
 BLLT subroutine
 Subroutine called if R0 is less than R1 (signed)
ARM7 Instruction Encoding
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Multiply (accumulate) cond
Multiply (accumulate) long cond
Branch and exchange cond
Single data swap cond
Halfword data transfer, register
cond
offset
Halfword data transfer, immediate
cond
offset
Signed data transfer
cond
(byte/halfword)
Data processing and PSR transfer cond
Load/store register/unsigned byte cond
Undefined cond
Block data transfer cond
Branch cond
Coprocessor data transfer cond
Coprocessor data operation cond
Coprocessor register transfer cond
Software interrupt cond
0 0 0 0 0 0 A S
Rd
Rn
9
8
7
6
5
4
3
2
1
Rs
1 0 0 1
Rm
Rn
1 0 0 1
Rm
0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1
Rn
0 0 0 1 0 B 0 0
Rn
Rd
0 0 0 0 1 0 0 1
Rm
0 0 0 P U 0 W L
Rn
Rd
0 0 0 0 1 0 1 1
Rm
0 0 0 P U 1 W L
Rn
Rd
offset
0 0 0 P U B W L
Rn
Rd
addr_mode
0 0 1
S
Rn
Rd
operand2
0 1 I P U B W L
Rn
Rd
addr_mode
0 0 0 0 1 U A S Rd_MSW Rd_LSW
opcode
1 0 1 1
1
Rn
register list
1 0 1 L
offset
1 1 0 P U NW L
1 1 1 0
CP
opcode
1 1 1 0 CP opc L
1 1 1 1
offset
1 1 H 1 addr_mode
0 1 1
1 0 0 P U 0 W L
0
Rn
CRd
CP#
CRn
CRd
CP#
CP
0
CRm
CRn
Rd
CP#
CP
1
CRm
ignored by processor
offset
Wrapping Up
Homework #2 due Wednesday 2/22
Reading for next week


Chapter 4, 5
ARMINSTREF
Pre-Quiz #3 on Learn@UW, complete
by Monday class time
Boundary Scan I/O Cell
Boundary Scan Chain
Emulation Scan Chain
RADM
Grace
Hopper
References


http://www.arlingtoncemetery.net/ghopper.htm
http://www.history.navy.mil/photos/images/h96000/h96566kc.htm