Prototype Test of SPring-8 FADC Module Da-Shung Su Wen-Chen Chang 02/07/2002

Lab

Status of Prototype Test • 4-channel FADC card: – Conversion of analog input into digital output in differential OPA and FADC.

– Functionality of shift register in FPGA.

– Functionality of data writing into FIFO from FPGA.

• FADC mother board: – Functionality of single action of VME “read” and “write” by NI-VXI software.

To be finished before TPC on-site test 03/03-03/15 • Zero suppression and fine timing tuning in FPGA.

• Implement VME BLT read action into CPLD.

• Stuffing 16 4-channel FADC cards and 2 FADC mother boards.

• Overall system test using TEXONO DAQ for reading calibration pulse. Exercising the coordination with trigger and DAQ system.

• Check the validity of offline reconstruction of data.

SPring-8 FADC Module (4 channels, 10 bits, 40 MHz)

FADC FIFO OPA FPGA

4-channel FADC card

OPA FADC FPGA FIFO

Driver

FADC Mother Board

CPLD Clock Driver VME Connector

FADC Mother Board

FADC Mother Board

CPLD

Left: FADC input Right: FADC readout Clock: 10 MHz

Digital Delay in FPGA: functioning of Shift Register 8 micro-sec (80 time bins) delay

Logic Analyzer: FPGA->FIFO Time bin counter

Header of event Trailer of event ADC Write of event Time Write of event

CS: CheckSum bit ND: Not defined.

Data Format Lowest Bit 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01

Header

CS 0 0 1 ND FADC Module number (1-64) Channel Number (1-32)

ADC

CS 0 1 0 ND ND

Time

CS 0 1 1 12 11

Trailer

CS 1 0 0 ND ND ADC (0-1024) Time (0-1024) Number of data bins (0-600)

FADC VME Action List (A24/D16) • • • • • •

0x0i0000

: address to write 0x0100 for resetting the FADC i. (Address modifier: 0x3D).

0x0i0001

: address to write for setting the sampling count of FADC i. (Address modifier: 0x3D).

0x0i0100

: address to read the merged 32 FIFOs’ content in BLT mode for FADC i. (Address modifier: 0x3B, 0x3F).

0x0i0101

: address to read the BLT reading cycle for FADC i. (Address modifier: 0x3B, 0x3F).

0x0i0000+j*0x000100

: address to read the single FIFO content in AO mode for channel j. (Address modifier: 0x3D)

0x0i0000+j*0x000102

: address to write for setting the zero suppression threshold for channel j. (Address modifier: 0x3D)

For each channel The Control Flow of FADC Preamplifier Module

Trigger Count

*Veto NIM Trigger signal

CPLD

FADC Trigger Clock 100MHz FADC Module

Master

VME CPU Clear Trigger

FADC

Reset

Slave Start Measurement

Yes

< 5 events

No

Send IRQ to VME CPU CPU start read action CPU send reset FADC set ready Clear trigger Veto

Things to finish up during SPring-8 visit • Complete one full 32-channel FADC module.

• Finalize and implement the VME action list.

• Determine and implement the default values for shift register length and sampling count.

• Implement the functions of “reset” and “ready” on the front-panel inputs and the definition of LED light.

• Fix up the gain range and signal coupling on the analog input.

• DAQ.

Things to do after Spring-8 visit • Finish up another 32-channel FADC module and ship it for use by the end of March.

• Get the feedback and finalize the layout and part lists for FADC modules.

• Issue the purchase orders of electronic parts and board fabrication by 04/15.