Transcript Title Slide - University of Utah

Senior Project Proposal
Micron Contact:
Tim Hollis
[email protected]
7/7/2015
208-363-3944
Micron Confidential
©2008 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron’s production data sheet specifications.
Information, products and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without
warranties of any kind. Dates are estimates only. Drawings not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
What would Micron like?
Windows/Unix compatible tool for implementing Worst-Case and
Statistical Link Analysis.
Deliverables:
•
Compiled GUI to run without Matlab license
•
Tool should:

Read in several data formats (ADS, Hspice, etc.) and allow the user to request Worst-Case or Statistical
Analysis.

Provide visualization of resulting data eye

Allow for multiple sources of co-channel interference

Allow for user defined TX and RX jitter
•
The worst-case tool should output a pass/fail based on a user-defined sampling window
•
The statistical tool should output a BER based on a user-defined sampling uncertainty distribution
•
Extra:
•
Be able to incorporate a user-defined TX FIR filter and/or RX DFE
•
Tool could output a worst-case pattern, based on the pulse response, for use in time domain simulation
•
Analysis of the impact of nonlinearity and driver asymmetry
•
Consider how to add simultaneous switching output noise (SSO)
Be able to justify all decisions
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Market Driven Trends
SPEED, CAPACITY, FORM-FACTOR, POWER, COST ⇔ SIGNAL INTEGRITY
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Digital Chip-to-Chip
Communication
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Typical High-Speed Memory Interface
Controller
Data
Channel
Driver
Memory
Capture
De-serializer
Serializer
Data[0:7]
Data
Driver
Capture
De-serializer
Serializer
CLK
Timing
Adjustment
Driver
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Reference Clock
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The Eye Diagram
Bit-stream
Voltage
Time
Voltage
Time
Bits
Superimposed
1 Unit Interval (UI)
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The Eye Diagram (Noise)
Bit-stream
Voltage
Voltage Noise
Time
Voltage
Time
Bits
Superimposed
1 Unit Interval (UI)
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The Eye Diagram (Jitter)
Bit-stream
Voltage
Time
Jitter
Voltage
Time
Bits
Superimposed
1 Unit Interval (UI)
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The “Real” Eye Diagram
Data Jitter
Clock Jitter
Signal Noise
Vref Noise
+
Receiver
Sensitivity
Vref
Data Signal
Clock Signal
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Signals are Still Analog
• Understanding the analog nature of the digital
signals being communicated helps explain the
degradation of the signals at high speeds.
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Digital Signals contain Many Analog Signals
(Fourier Series)
First Harmonic
Triangle Wave Construction
Square Wave Construction
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Micron Confidential
Digital Signals contain Many Analog Signals
(Fourier Series)
First + Third Harmonics
Triangle Wave Construction
Square Wave Construction
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Digital Signals contain Many Analog Signals
(Fourier Series)
First + Third + Fifth Harmonics
Triangle Wave Construction
Square Wave Construction
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Digital Signals contain Many Analog Signals
(Fourier Series)
50 Accumulated Harmonics
Triangle Wave Construction
Square Wave Construction
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Components of a
Single Digital Signal
Amplitude Distortion
Components of a
Single Digital Signal
Impact of Channel on Analog Signals
Phase Distortion
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Chip-to-Chip Signal Degradation
6 inches
1.0
DQout1(5)-.72
DQin1(5)-.68
0.8
2 Gbps
Gb/s
1
0.6
0.4
0.2
-0.0
-0.2
0.0
0.5
1.5
1.0
2.0
2.5
3.0
2.0
2.5
3.0
2.0
2.5
3.0
time, nsec
1.0
DQout1(5)-.72
DQin1(5)-.68
0.8
5 Gb/s
0.6
0.4
0.2
-0.0
-0.2
0.0
0.5
1.0
1.5
time, nsec
1.0
DQout1(5)-.72
DQin1(5)-.68
0.8
10 Gb/s
0.6
0.4
0.2
-0.0
-0.2
0.0
0.5
1.0
1.5
time, nsec
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Chip-to-Chip Signal Degradation
T1
T2
P3
P1
P2
Inter-symbol
Interference
Data-dependent
Jitter
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Signal Degradation leads to Communication Errors
M i c r o n
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M i c r o 
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Handling Communication Errors
• Because it’s theoretically impossible to communicate
without errors indefinitely, a certain number of errors
per a given number of transmitted bits is specified:

Bit-Error-Rate (Ratio) = # Errors / # Bits Transmitted
• Usually spec’d below 1 / 1,000,000,000,000

Requires simulating more than 1,000,000,000,000
cycles to verify.
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Pulse-Response-based
Link Analysis Methods
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Pulse Response Analysis
• Most emerging analysis methods are
based on the information contained
in the system pulse response(s).
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Worst-Case Link Verification
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Worst Case Eye (Peak Distortion Analysis)
Worst Case Eye Due to Inter-symbol Interference
Data-Rate = 10 Gb/s
Voltage
Voltage
Voltage
1
1
0.9
0.5
0.8
0.7
0
891
0.6
Pulse
Pulse
Response
Response
Pulse
Response
Pre-Cursor
Pre-Cursor
Pre-Cursor
Cursor
Cursor
Cursor
Post-Cursor
Post-Cursor
Post-Cursor
1 UI
1091 1291 1491 1691 1891 2091 2291 2491 2691 2891 3091
Picoseconds
ISIpp = 815.9948 mV
DDJpp = 34.3117 ps
0.5
pp
0.4
1
0.3
0.2
0.5
0.1
0
0
-50
0
50
100
-100
891 1091 1291 1491 1691 1891 2091 2291 2491 2691 2891 3091
Picoseconds
Picoseconds
J. G. Proakis, “Digital Communication”, McGraw-Hill, 3rd Ed., 1995.
B. K. Casper, M. Haycock, and R. Mooney, “An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes”,
in Digest of Technical Papers from the IEEE Symposium on VLSI Circuits, June 2002, pp. 54–57.
©2008 Micron Technology, Inc. All rights reserved.
Micron Confidential
7/7/2015
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Worst Case Eye (Peak Distortion Analysis)
Worst Case Eye Due to Inter-symbol Interference
Data-Rate = 10 Gb/s
Voltage
Voltage
Voltage
1
1
0.9
0.5
0.8
0.7
0
891
0.6
Pulse
Pulse
Response
Response
Pulse
Response
Pre-Cursor
Pre-Cursor
Pre-Cursor
Cursor
Cursor
Cursor
Post-Cursor
Post-Cursor
Post-Cursor
1 UI
1091 1291 1491 1691 1891 2091 2291 2491 2691 2891 3091
Picoseconds
0.5
ISIpp = 815.9948 mV
DDJpp = 34.3117 ps
0.4
1
0.3
0.2
0.5
0.1
0
0
-100
-50
0
50
100
891 1091 1291 1491 1691 1891 2091 2291 2491 2691 2891 3091
Picoseconds
Picoseconds
J. G. Proakis, “Digital Communication”, McGraw-Hill, 3rd Ed., 1995.
B. K. Casper, M. Haycock, and R. Mooney, “An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes”,
in Digest of Technical Papers from the IEEE Symposium on VLSI Circuits, June 2002, pp. 54–57.
©2008 Micron Technology, Inc. All rights reserved.
Micron Confidential
7/7/2015
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Worst Case Eye
WC1
WC2
WC3
ISI Only
xTalk DBI
xTalk WC
Pass/Fail Mask
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Statistical Link Verification
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What is a PDF (probability density function)?
If Gaussian Distribution:
µ = mean
2= variance
1 = rms value
voltage/time
•Describes the probability of encountering a sample (noise/jitter) at a specific
voltage/time.
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Calculating Probability from the PDF
voltage/time
a
b
•Describes the probability of encountering a sample (noise/jitter) at a specific
voltage/time.
•Because the total area under the PDF integrates to 1, the probability that a
sample will fall between two values requires integrating the function over the
range between the values of interest.
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Error due to Voltage Uncertainty
Ideal ONE
Ideal ZERO
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Error due to Voltage Uncertainty
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Error due to Timing Uncertainty
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Error due to Timing Uncertainty
* Complete *
integration leads
to Bathtub curves
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Bathtub Curves
Eye Height
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Eye Width
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Statistical Analysis
(Deriving a 3D Bathtub)
Recursively convolve 1UI sample
terms assuming equal probability
of a transmitted ‘0’ or ‘1’
1UI
[0 -0.01]  [0 0.59]

[0 -0.07]

[0 0.015]

[0 0.055]

[0 0.2]
0.59

[0 0.5]

0.0
[0 0]

[0 0.7]
Each step scaled by ½ to account for P(0) = P(1)
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y(t)
Error due to simultaneous
Voltage and Timing Uncertainty
Probabilistic Data Eye
Probabilistic Data Eye
Sample Voltage
Probability of Error
ts
VREF
Sample Time
P( E)  102  1/ 100
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Computing Bit Error Ratio
Sampling Uncertainty Distribution
Sampling Probability
Probability of Error
Probabilistic Data Eye
BER EYE
Error Rate
2D integration
provides BER value
B. K. Casper, M. Haycock, and R. Mooney, “An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling scheme”,
in Digest of Technical Papers from the IEEE Symposium on VLSI Circuits, June 2002, pp. 54–57.
©2008 Micron Technology, Inc. All rights reserved.
Micron Confidential
7/7/2015
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Statistical Eye
built from Step
Statistical Eye built
from Transient
10x
10x
All figures
correspond to 350
received bits.
Results are
almost identical
Transient Eye
(50W)
Vout
Linear
Driver
Vin
©2008 Micron Technology, Inc. All rights reserved.
Micron Confidential
7/7/2015
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Correct Jitter Modeling
Bit transitions convolved with
channel step response =
received transitions, no jitter
“Jittered” bit transitions
convolved with channel
impulse response =
channel-effected TX jitter
Bit transitions convolved with
channel impulse response,
then “jittered” =
RX jitter
* Not implemented correctly in existing tools *
P. K. Hanumolu, B. K. Casper, R. Mooney, G. Y. Wei, and U. K. Moon, “Jitter in high-speed serial and parallel links”, in Proceedings of
the IEEE International Symposium on Circuits and Systems, May 2004, pp. 425–428.
7/7/2015
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Who’s working on this?
• Intel: First to publish
• AMD: Has an internally developed tool
• StatEye.Org: Open-source code with several contributors
• Agilent: Has wrapped StatEye code into their Ptolemy tool.
• Ansoft: Has wrapped StatEye code (VerifEye) and a variant
(QuickEye) into their Designer tool.
• Mentor Graphics: Has implemented a non-convolution based
approach called FastEye within their HyperLynx tool.
• Synopsys (Hspice): Currently in development.
• Tools available for purchase are limited in flexibility (multi-trace
analysis, etc.) and vendors do not completely understand the
assumptions.
7/7/2015
©2008 Micron Technology, Inc. All rights reserved.
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Micron Confidential
What would Micron like?
Project Deliverables
7/7/2015
Micron Confidential
What would Micron like?
Windows/Unix compatible tool for implementing Worst-Case and
Statistical Link Analysis.
Deliverables:
•
Compiled GUI to run without Matlab license
•
Tool should:

Read in several data formats (ADS, Hspice, etc.) and allow the user to request Worst-Case or Statistical
Analysis.

Provide visualization of resulting data eye

Allow for multiple sources of co-channel interference

Allow for user defined TX and RX jitter
•
The worst-case tool should output a pass/fail based on a user-defined sampling window
•
The statistical tool should output a BER based on a user-defined sampling uncertainty distribution
•
Extra:
•
Be able to incorporate a user-defined TX FIR filter and/or RX DFE
•
Tool could output a worst-case pattern, based on the pulse response, for use in time domain simulation
•
Analysis of the impact of nonlinearity and driver asymmetry
•
Consider how to add simultaneous switching output noise (SSO)
Be able to justify all decisions
7/7/2015
©2008 Micron Technology, Inc. All rights reserved.
41
Micron Confidential
Resources
B. K. Casper, M. Haycock, and R. Mooney, “An accurate and
efficient analysis method for multi-Gb/s chip-to-chip signaling
scheme”, in Digest of Technical Papers from the IEEE
Symposium on VLSI Circuits, June 2002, pp. 54–57.
B. K. Casper , G. Balamurugan, J. E. Jaussi, J. Kennedy, M. Mansuri,
“Future microprocessor interfaces: Analysis, design and
optimization”, in Proceedings of the IEEE Custom Integrated
Circuits Conference, Sept. 2007, pp. 479-486.
P. K. Hanumolu, B. K. Casper, R. Mooney, G. Y. Wei, and U. K.
Moon, “Jitter in high-speed serial and parallel links”, in
Proceedings of the IEEE International Symposium on Circuits and
Systems, May 2004, pp. 425–428.
www.stateye.org
7/7/2015
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