Assembly Language Basic Concepts IA-32 Processor Architecture

Hardware

  Intel386, Intel486, Pentium, or latest processors, AMD processors, or compatible processors. The same architectures, but different organizations.

Not working in MAC computers, SUN Sparc workstations.

Operating Systems

   MS-DOS, Windows 95/98/ME/NT/2000/XP.

Advanced programs relating to direct hardware access and disk sector programming must be run under MS-DOS, Windows 95/98/ME.

Not working in Linux, MAC OS.

Programming Software

    Editor: Microsoft Visual C++ (6.0, 2005 Express, 2008 Express), TextPad, Notepad.

Assembler and linker: MASM 6.15, MASM 8.0.

32-but debugger: Microsoft Visual C++.

Other: MASM 32.

Two Types of Programs

  16-bit real-address mode: Run under MS-DOS and in the console window under MS-Windows. Written for the Intel 8086 and 8088 processors. Not discussed in this class.

32-bit protected mode: All the programs in this class.

Build Environments

   Get started: http://kipirvine.com/asm/gettingSta rted/index.htm

Microsoft Visual C++ (6.0, 2005 Express, 2008 Express) installed.

Install MASM 8.0 (if 2005 Express is installed)

Build Environments

 If Microsoft Visual C++ 6.0 is installed:  Install MASM 6.15

 Set tools: Build, run, and debug. http://kipirvine.com/asm/4th/ide/vs6/i ndex.htm

A Simple C File

      #include    void main() { int i; i = 0x10000; i = i + 0x40000; i = i - 0x20000; printf("i= %d\n", i); }

Into Assembly Language

                3: void main() 4: { 0040B450 push ebp 0040B451 mov ebp,esp 0040B453 sub esp,44h 0040B456 push ebx 0040B457 push esi 0040B458 push edi 0040B459 lea edi,[ebp-44h] 0040B45C mov ecx,11h 0040B461 mov eax,0CCCCCCCCh 0040B466 rep stos dword ptr [edi] 5: int i; 6: 7: i = 0x10000; 0040B468 mov dword ptr [ebp-4],10000h

               8: i = i + 0x40000; 0040B46F mov eax,dword ptr [ebp-4] 0040B472 add eax,40000h 0040B477 mov dword ptr [ebp-4],eax 9: i = i - 0x20000; 0040B47A mov ecx,dword ptr [ebp-4] 0040B47D sub ecx,20000h 0040B483 mov dword ptr [ebp-4],ecx 10: printf("i= %d\n", i); 0040B486 mov edx,dword ptr [ebp-4] 0040B489 push edx 0040B48A push offset string "i= %d\n" (0041fe50) 0040B48F call printf (0040b710) 0040B494 add esp,8 11: }

A Simple MASM File

 TITLE Add and Subtract (AddSub.asm)   ; This program adds and subtracts 32-bit integers.

; Last update: 2/1/02  INCLUDE Irvine32.inc

      .code

main PROC mov eax,10000h add eax,40000h sub eax,20000h call DumpRegs    exit main ENDP END main ; EAX = 10000h ; EAX = 50000h ; EAX = 30000h

Portability

  Assembly language is not portable.

Well-known processor families are Motorola 68x00, Intel IA-32, SUN Sparc, DEC Vax, and IBM-370.

Applications

      Small embedded programs.

Real-time applications.

Computer game consoles.

Help understand computer hardware and operating systems.

Subroutines hand optimized for speed, for example, bitwise manipulation and data encryption.

Device drivers.

Applications

      Small embedded programs.

Real-time applications.

Computer game consoles.

Help understand computer hardware and operating systems.

Subroutines hand optimized for speed, for example, bitwise manipulation and data encryption.

Device drivers.

Virtual Machines

• Tanenbaum: Virtual machine concept • Programming Language analogy: • Each computer has a native machine language (language L0) that runs directly on its hardware • A more human-friendly language is usually constructed above machine language, called Language L1 • Programs written in L1 can run two different ways: • Interpretation – L0 program interprets and executes L1 instructions one by one • Translation – L1 program is completely translated into an L0 program, which then runs on the computer hardware Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples

Translating Languages

English: Display the sum of A times B plus C.

C++: cout << (A * B + C); Assembly Language: mov eax,A mul B add eax,C call WriteInt Intel Machine Language: A1 00000000 F7 25 00000004 03 05 00000008 E8 00500000 Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples

Specific Machine Levels

High-Level Language Assembly Language Operating System Instruction Set Architecture Microarchitecture Digital Logic Level 5 Level 4 Level 3 Level 2 Level 1 Level 0 (descriptions of individual levels follow . . . ) Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

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High-Level Language

• Level 5 • Application-oriented languages • C++, Java, Pascal, Visual Basic . . .

• Programs compile into assembly language (Level 4) Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples 18

Assembly Language

• Level 4 • Instruction mnemonics that have a one-to one correspondence to machine language • Calls functions written at the operating system level (Level 3) • Programs are translated into machine language (Level 2) Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples 19

Operating System

• Level 3 • Provides services to Level 4 programs • Translated and run at the instruction set architecture level (Level 2) Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples 20

Instruction Set Architecture

• Level 2 • Also known as conventional machine language • Executed by Level 1 (microarchitecture) program Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples 21

Microarchitecture

• Level 1 • Interprets conventional machine instructions (Level 2) • Executed by digital hardware (Level 0) Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples 22

Digital Logic

• Level 0 • CPU, constructed from digital logic gates • System bus • Memory • Implemented using bipolar transistors Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

next: Data Representation Web site Examples 23

Character Storage

• Character sets • Standard ASCII (0 – 127) • Extended ASCII (0 – 255) • ANSI (0 – 255) • Unicode (0 – 65,535) • Null-terminated String • Array of characters followed by a

null byte

• Using the ASCII table • back inside cover of book Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples 24

Unicode Standard

   UTF-8  Used in HTML.  The same byte values as ASCII UTF-16  Windows NT, 2000, and XP.

UTF-32

Basic Microcomputer Design

• clock synchronizes CPU operations • control unit (CU) coordinates sequence of execution steps • ALU performs arithmetic and bitwise processing data bus registers

Central Processor Unit (CPU)

ALU CU clock address bus control bus Memory Storage Unit I/O Device #1 I/O Device #2 Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples 26

Clock

• synchronizes all CPU and BUS operations • machine (clock) cycle measures time of a single operation • clock is used to trigger events one cycle 1 0 Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples 27

Instruction Execution Cycle

• Fetch • Decode • Fetch operands • Execute • Store output memory op1 op2 PC read I-1 program I-2 I-3 I-4 fetch registers registers I-1 instruction register flags (output) ALU execute Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples 28

Multi-Stage Pipeline

• Pipelining makes it possible for processor to execute instructions in parallel • Instruction execution divided into discrete stages Example of a non pipelined processor. Many wasted cycles.

7 8 9 10 11 12 1 2 3 4 5 6 S1 I-1 S2 Stages S3 S4 S5 S6 I-1 I-1 I-1 I-1 I-1 I-2 I-2 I-2 I-2 I-2 I-2 Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples 29

Pipelined Execution

• More efficient use of cycles, greater throughput of instructions: 1 2 3 4 5 6 7 S1 I-1 I-2 S2 Stages S3 S4 I-1 I-2 I-1 I-2 I-1 I-2 S5 S6 I-1 I-2 I-1 I-2 For k states and n instructions, the number of required cycles is: k + (n – 1) Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples 30

Wasted Cycles (pipelined)

• When one of the stages requires two or more clock cycles, clock cycles are again wasted.

8 9 10 11 1 2 3 4 5 6 7 S1 I-1 I-2 I-3 S2 Stages exe S3 S4 S5 I-1 I-2 I-3 I-1 I-2 I-3 I-1 I-1 I-2 I-2 I-3 I-3 I-1 I-2 S6 I-1 I-2 I-3 I-3 For k states and n instructions, the number of required cycles is: k + (2n – 1) Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples 31

Superscalar

A superscalar processor has multiple execution pipelines. In the following, note that Stage S4 has left and right pipelines (u and v).

Stages S4 S3 u v 1 2 3 4 5 6 7 8 9 10 S1 I-1 I-2 I-3 I-4 S2 I-1 I-2 I-3 I-4 I-1 I-2 I-3 I-4 I-1 I-1 I-3 I-3 I-2 I-2 I-4 I-4 S5 S6 I-1 I-2 I-3 I-4 I-1 I-2 I-3 I-4 For k states and n instructions, the number of required cycles is: k + n Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples 32

Reading from Memory

• Multiple machine cycles are required when reading from memory, because it responds much more slowly than the CPU. The steps are: • address placed on address bus • Read Line (RD) set low • CPU waits one cycle for memory to respond • Read Line (RD) goes to 1, indicating that the data is on the data bus Cycle 1 Cycle 2 Cycle 3 Cycle 4 CLK Address ADDR RD Data DATA Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples 33

Cache Memory

• High-speed expensive static RAM both inside and outside the CPU.

• Level-1 cache: inside the CPU • Level-2 cache: outside the CPU • Cache hit: when data to be read is already in cache memory • Cache miss: when data to be read is not in cache memory.

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples 34

How a Program Runs

User sends program name to gets starting cluster from Operating system returns to searches for program in loads and starts Directory entry Program Current directory System path Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples 35

Multitasking

• OS can run multiple programs at the same time.

• Multiple threads of execution within the same program.

• Scheduler utility assigns a given amount of CPU time to each running program.

• Rapid switching of tasks • gives illusion that all programs are running at once • the processor must support task switching.

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples 36

IA-32 Processor Architecture

      Modes of operation Address space Program registers System registers Floating-point unit History

Modes of Operation

• Protected mode • native mode (Windows, Linux) • Real-address mode • native MS-DOS • System management mode • power management, system security, diagnostics • Virtual-8086 mode • hybrid of Protected • each program has its own 8086 computer Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples

Basic Execution Environment

• Addressable memory • General-purpose registers • Index and base registers • Specialized register uses • Status flags • Floating-point, MMX, XMM registers Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

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Addressable Memory

• Protected mode • 4 GB • 32-bit address • Real-address and Virtual-8086 modes • 1 MB space • 20-bit address Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples

Microsoft Visual C++

Web site Examples

Flags

Book OF D I x SF ZF x AC x P x CF Visual C OV UP EI x PL ZR x AC x PE x CY Web site Examples

General-Purpose Registers

Named storage locations inside the CPU, optimized for speed.

32-bit General-Purpose Registers

EAX EBX ECX EDX EBP ESP ESI EDI EFLAGS EIP

16-bit Segment Registers

CS SS DS ES FS GS Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples

Accessing Parts of Registers

• Use 8-bit name, 16-bit name, or 32-bit name • Applies to EAX, EBX, ECX, and EDX 8 AH 8 AL 8 bits + 8 bits AX 16 bits EAX 32 bits Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples

Index and Base Registers

• Some registers have only a 16-bit name for their lower half: Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples

Some Specialized Register Uses

(1 of 2) • General-Purpose • EAX – accumulator • ECX – loop counter • ESP – stack pointer • ESI, EDI – index registers • EBP – extended frame pointer (stack) • Segment • CS – code segment • DS – data segment • SS – stack segment • ES, FS, GS - additional segments Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples

Some Specialized Register Uses

(2 of 2) • EIP – instruction pointer • EFLAGS • status and control flags • each flag is a single binary bit Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples

Status Flags

• Carry • unsigned arithmetic out of range • Overflow • signed arithmetic out of range • Sign • result is negative • Zero • result is zero • Auxiliary Carry • carry from bit 3 to bit 4 • Parity • sum of 1 bits is an even number Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples

System Registers

       IDTR (Interrupt Descriptor Table Register) GDTR (Global Descriptor Table Register) LDTR (Local Descriptor Table Register) Task Register Debug Registers Control registers CR0, CR2, CR3, CR4 Model-specific Registers

Floating-Point, MMX, XMM Registers

• Eight 80-bit floating-point data registers • ST(0), ST(1), . . . , ST(7) • arranged in a stack • used for all floating-point arithmetic • Eight 64-bit MMX registers • Eight 128-bit XMM registers for single instruction multiple-data (SIMD) operations

80-bit Data Registers

ST(0) ST(1) ST(2) ST(3) ST(4) ST(5) ST(6) ST(7) Opcode Register Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples

48-bit Pointer Registers

FPU Instruction Pointer FPU Data Pointer

16-bit Control Registers

Tag Register Control Register Status Register

Intel Microprocessor History

• Intel 8086, 80286 • IA-32 processor family • P6 processor family • CISC and RISC Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

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Early Intel Microprocessors

• Intel 8080 • 64K addressable RAM • 8-bit registers • CP/M operating system • S-100 BUS architecture • 8-inch floppy disks!

• Intel 8086/8088 • IBM-PC Used 8088 • 1 MB addressable RAM • 16-bit registers • 16-bit data bus (8-bit for 8088) • separate floating-point unit (8087) Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

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The IBM-AT

• Intel 80286 • 16 MB addressable RAM • Protected memory • several times faster than 8086 • introduced IDE bus architecture • 80287 floating point unit Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

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Intel IA-32 Family

• Intel386 • 4 GB addressable RAM, 32-bit registers, paging (virtual memory) • Intel486 • instruction pipelining • Pentium • superscalar, 32-bit address bus, 64-bit internal data path Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

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Intel P6 Family

• Pentium Pro • advanced optimization techniques in microcode • Pentium II • MMX (multimedia) instruction set • Pentium III • SIMD (streaming extensions) instructions • Pentium 4 and Xeon • Intel NetBurst micro-architecture, tuned for multimedia Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

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CISC and RISC

• CISC – complex instruction set • large instruction set • high-level operations • requires microcode interpreter • examples: Intel 80x86 family • RISC – reduced instruction set • simple, atomic instructions • small instruction set • directly executed by hardware • examples: • ARM (Advanced RISC Machines) • DEC Alpha (now Compaq) Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples 56

IA-32 Memory Management

• Real-address mode • Calculating linear addresses • Protected mode • Multi-segment model • Paging Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

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Real-Address mode

• 1 MB RAM maximum addressable • Application programs can access any area of memory • Single tasking • Supported by MS-DOS operating system Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

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Segmented Memory

Segmented memory addressing: absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset F0000 E0000 D0000 C0000 B0000 A0000 90000 80000 70000 60000 50000 40000 30000 20000 10000 00000 8000:FFFF 8000:0000 seg ofs 0250 8000:0250 one segment Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Calculating Linear Addresses

• Given a segment address, multiply it by 16 (add a hexadecimal zero), and add it to the offset • Example: convert 08F1:0100 to a linear address

Adjusted Segment value: 0 8 F 1 0 Add the offset: 0 1 0 0 Linear address: 0 9 0 1 0

Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples

Protected Mode

(1 of 2) • 4 GB addressable RAM • (00000000 to FFFFFFFFh) • Each program assigned a memory partition which is protected from other programs • Designed for multitasking • Supported by Linux & MS-Windows Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

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Protected mode

(2 of 2) • Segment descriptor tables • Program structure • code, data, and stack areas • CS, DS, SS segment descriptors • global descriptor table (GDT) • MASM Programs use the Microsoft flat memory model Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples

Flat Segment Model

• Single global descriptor table (GDT).

• All segments mapped to entire 32-bit address space FFFFFFFF (4GB) Segment descriptor, in the Global Descriptor Table 00040000 base address 00000000 limit 00040 access - - - Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

00000000 Web site Examples

Multi-Segment Model

• Each program has a local descriptor table (LDT) • holds descriptor for each segment used by the program RAM Local Descriptor Table 26000 base 00026000 00008000 00003000 limit 0010 000A 0002 access Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

8000 3000 Web site Examples

Paging

• Supported directly by the CPU • Divides each segment into 4096-byte blocks called pages • • Sum of all programs can be larger than physical memory • • Part of running program is in memory, part is on disk Virtual memory manager (VMM) – OS utility that manages the loading and unloading of pages Page fault – issued by CPU when a page must be loaded from disk Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

Web site Examples

Levels of Input-Output

• Level 3: Call a library function (C++, Java) • easy to do; abstracted from hardware; details hidden • slowest performance • Level 2: Call an operating system function • specific to one OS; device-independent • medium performance • Level 1: Call a BIOS (basic input-output system) function • may produce different results on different systems • knowledge of hardware required • usually good performance • Level 0: Communicate directly with the hardware • May not be allowed by some operating systems Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

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Displaying a String of Characters

Application Program Level 3 When a HLL program displays a string of characters, the following steps take place: OS Function Level 2 BIOS Function Level 1 Level 0 Hardware Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

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ASM Programming levels

ASM programs can perform input-output at each of the following levels: Library Level 3 ASM Program OS Function BIOS Function Hardware Level 2 Level 1 Level 0 Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007.

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