Transcript Lecture 4 Instruction Set Architecture
Lecture 4 Instruction Set Architecture
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 1
Instruction Set Architecture
•
1950s to 1960s: Computer Architecture Course
Computer Arithmetic
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1970 to mid 1980s: Computer Architecture Course
Instruction Set Design, especially ISA appropriate for compilers
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1990s: Computer Architecture Course
Design of CPU, memory system, I/O system, Multiprocessors Lecture 4 - 2 Instruction Set Architecture CS510 Computer Architectures
Languages of Computers
• • •
Machine Language
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Programs consist of machine instructions Directly executable without preprocessing
– – –
Direct manipulation of machine registers Efficient in view of machine resource utilization Difficult to program Assembly language
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Improved version of machine language with emphasis on user-friendliness
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Symbolic machine language(symbols for operations and addresses)
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Assembler is needed to translate into a machine language program High-Level Language
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Programs consist of statements, each of which can be translated into several machine language instructions
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Need a compiler to translate into a machine language program Relatively easy to program compare to ML or AL
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Hardware resource utilization may be inefficient
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 3
Semantic Gap Between ML and HLL
• • • •
As Hardware cost goes down, Software cost goes up
– –
Shortage of programmers Unreliable Software => Unreliable Computers System cost
– –
Response: Keep the programming cost down Develop powerful, complex user-friendly HLL HLL programmers are easy to train HW
– – –
Greater Semantic Gap between HLL and Machine Language Execution inefficiency Software complexity Compiler complexity
– – –
To offset the semantic gap Large instruction set Variety of addressing modes Hardware/Firmware implementation of HLL primitives SW year
Lecture 4 - 4 Instruction Set Architecture CS510 Computer Architectures
Instruction Set
Boundary between Designers(architects) and programmers
– –
For designers: For Programmers: Specification of the function of CPU A pool of functions from which they choose to use in the program
One would expect that human language should directly reflect the characteristics of human intellectual capabilities that language should be a direct mirror of mind in ways which other systems of knowledge and belief cannot. - Noam Chomsky
Instruction Set
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Language of a machine
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Characterizes the machine’s capability and behavior Performance Issues
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Memory Bandwidth is used 1/2 for Instructions and 1/2 for Data
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For efficient utilization of MB, instruction representation must as compact as possible whilst still being compatible with data
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von Neumann Bottleneck exists in MB
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 5
Memory Bandwidth Issue
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Memory Bandwidth is used by CPU and I/O Memory Bandwidth
• •
instruction execution I/O instruction execution I/O Memory Bandwidth given to CPU is used for Instruction Fetches and Operand Fetches or Operand Stores Consider an AC-machine; ADD X, or LDA X Memory bandwidth given to CPU IF OF IF OF IF OF D/IP E D/IP E D/IP E
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 6
Machine Language
Machine Language
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Vocabulary
• •
Operations Addressing Modes for operands’ addresses and the next instruction address
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Syntax
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Methods of representing operation(OP-code), operands, addresses in an instruction
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Instruction format Encoding of Instruction fields
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Grammar
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Rules of using instructions to make a program
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 7
Components of an Instruction
Operation Code(OP-code)
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Format specifier
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Long / Short Field definition
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Operation Types of operands Operand Address(es)
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Operand itself Address themselves(including abbreviated) Address modification specification
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Automatic indexing Relative address
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Sequencing
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 8
Instruction Set and Computer Architecture
Computer Architectures are classified into three classes according to the Register Structures for operands storage
– – –
Stack Computer Architecture AC Computer Architecture General Purpose Register Computer Architecture Input Bus Input Bus General Purpose Registers Stack Stack Architecture ALU Other Registers ALU AC Registers ALU Output Bus AC Architecture Output Bus GPR Architecture
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 9
Stack Computer Architecture
SP Full(F) Empty(E) S n-1 0 ALU Instruction PUSH POP X X Unary Instr.
(Shift Left) Binary Instr.
(ADD) Operation if F=1, then S overflow; else SP SP+1, S[SP] M[X], if SP=(n-1), then F 1, E 0 if E=1, then empty S; else M[X] S[SP], SP SP-1, F 0, if SP=(n-1), E 1 if E=1, then empty S; else ALU S[SP], then S[SP] ALU if E=1, then empty S; else ALU S[SP], SP SP-1, if SP=(n-1), then E 1, empty S; else ALU S[SP], then S[SP] ALU
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 10
Characteristics of the Stack Architecture
• • •
Instruction length is short
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No need to represent the address(es) of operand(s) in functional instructions Instruction execution time is fast
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Operand(s) access is fast because they are in the stack(register) Operand(s) must be stored in the stack before operating on them
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Inconvenient to prepare data in the stack Frequent use of PUSH and POP instructions to prepare data in the stack - memory access
Lecture 4 - 11 Instruction Set Architecture CS510 Computer Architectures
AC Computer Architecture
Input Bus Other Registers ALU Output Bus AC Instruction Unary Instruction (CPA) Binary Instruction (ADD X) Operation AC f(AC) AC f(AC, M[X]) Transfer Instruction (LDA X) AC M[X] (STA X) M[X] AC Characteristics: - Instruction execution time of binary instructions are slow
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One of the operands must be read from memory - Instruction length is longer than in the stack architecture
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One of the operand’s memory address must be specified in the instruction although AC(a data register) can be implied - Frequency of LDA/STA instructions is high
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There is only one data register
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 12
GPR Computer Architecture
Input Bus Instruction Operation Registers ALU Unary Instruction (COMP R1, R2) R1 f(R2) Binary Instruction (ADD R1, R2) or R1 f(R1, R2) or (ADD R1, R2, R3) R3 f(R1, R2) Output Bus Transfer Instruction (LD R1, X) (ST R1, X) R1 M[X] M[X] R1 Characteristics: - Instruction length is short because register addresses are used for operands - Instruction execution time is fast because all the operands are in the registers - Frequency of using LD/ST instructions depends on the number of registers - Opportunities of storing the results of operations in GPR is high because there are many registers
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 13
Computer Architecture?
. . . the attributes of a [computing] system as seen by the programmer , i.e. the conceptual structure and functional behavior , as distinct from the organization of the data flows and controls, the logic design, and the physical implementation.
Amdahl, Blaaw, and Brooks, 1964
SOFTWARE
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 14
Towards Evaluation of ISA and Organization
software instruction set hardware
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 15
Interface Design
A Good Interface:
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Lasts through many implementations ( compatibility ) portability,
• • •
Is used in many different ways ( Provides
convenient functionality
Permits an generality
efficient implementation
) to higher levels at lower levels use use use
Interface Interface
imp 1 imp 2 imp 3 time
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 16
Evolution of Instruction Sets
Single Accumulator
(EDSAC 1950)
Accumulator + Index Registers
(Manchester Mark I, IBM 700 series 1953)
Separation Instruction set from Implementation High-level Language Based
(B5000 1963)
Concept of a Family
(IBM /S360 1964)
General Purpose Register Machines Complex Instruction Sets
(Vax, Intel 432 1977-80)
Instruction Set Architecture Load/Store Architecture
(CDC 6600, Cray 1 1963-76)
RISC
(Mips,Sparc,88000,IBM RS6000, . . .1987)
CS510 Computer Architectures Lecture 4 - 17
Evolution of Instruction Sets
• • •
Major advances in computer architecture are typically associated with landmark instruction set designs
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Ex: Stack(B1700) vs GPR (System S/360) Design decisions must take into account:
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technology(component)
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machine organization programming languages
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compiler technology operating systems And they in turn influence these
Lecture 4 - 18 Instruction Set Architecture CS510 Computer Architectures
Design Space of ISA
• • •
Five Primary Dimensions Number of explicit operands Operand Storage Effective Address
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Type and Size of Operands
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Operations ( 0, 1, 2, 3 ) Where besides memory?
How is memory location specified?
byte, int, float, vector, . . .
How is it specified?
add, sub, mul, . . .
How is it specified?
• • • •
Other Aspects Successor Conditions Encoding Parallelism How is it specified?
How are they determined?
Fixed or variable? Wide?
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 19
Number of Explicit Operands
Maximum number of operands to be specified is 3 - 2 source operands and 1 result operand To optimize the memory bandwidth required by instructions(for fetching from Memory), the number of explicitly specified operands in the instruction needs to be reduced
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2 operands(GPR machine) 2 source operands(1 of the source operands is destroyed after execution to store the result)
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1 operand(AC machine) 1 of the operands is implied to a specific hardware register called Accumulator(AC)(result of the execution is also stored in this register)
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0 operand(Stack machine) Both of the operands and the result are implied to a stack
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 20
Operand Storage
Storage Memory Register - Long memory addressing - Need to represent the address with a few bits
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Relative addressing with displacement
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Page/Segment addressing - General purpose register
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Short register addressing - AC Stack(register) - Does not need for addresses
Lecture 4 - 21 Instruction Set Architecture CS510 Computer Architectures
• • • •
Address Space and Storage Space
Address Space
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Consists of addresses that programmers can use Storage Space
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Consists of physical storage locations For a simple low cost machine, the Address Space and the Storage Space are identical
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Programmers program with the actual storage addresses Modern computers provide the storage systems with Independent Address and Storage Spaces
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An Effective Address(EA) needs to be obtained from the Address used in the program to access the operand from the memory
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Usually the Address Space is much larger than the Storage Space
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Virtual Storage System
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 22
Effective Address
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Address and Physical Storage Location are two different concepts.
Addresses of Operands are represented or implied in the instruction.
Operand’s address needs to be mapped into an Effective Address of the physical storage location
Basic Addressing Modes(A or R in instructions)
Mode Immediate Direct Indirect Register R Indirect Displacement Stack Algorithm opd=A EA=A EA=M[A] EA=R EA= M[R] EA= A+[R] opd=S[TOP] Advantage Disadvantage # of M refer limited value simple limited addr space large addr space multiple M refer no M refer limited addr space large addr space extra M refer flexibility complexity no M refer limited applications
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 23
Specification of Type and Size of Operand
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Specification of the Type of the operand
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Usually different op-codes for different types of operands Specification of the Size of the operand
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op-code represents the resolution of the operand address
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bit, byte, half word(upper/lower half) , word, ...
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Length of operands
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Implicit Variable length
:
Specified explicitly in the instruction
: :
Specified by a designated register Specified by the delimiter marks in the operand reserved-bit delimiter(field or word mark) reserved-bit configuration(record or group mark)
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 24
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 25
Operation
• •
Specification
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Encoded to reduce the instruction length reason Types
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Minimal Instruction Set Complex Instruction Set vs RISC
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 26
Four Types of Operations
Functional ADD, AND, CPA, CPC, ROL, CLA, CLC, INC, … Transfer LDA, STA(LD, ST), … Control JMP, JNA, JZA, JZC(SMA, SZA, SZC), … Input/Output INP, OUT, …
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 27
Minimal Instruction Set
Bn instruction Bn X1,X2,X3 M[X1] M[X1] - M[X2] AC M[X1] - M[X2] If AC < 0 PC X3 Move the content of Source to Destination A 2-address instruction(X1, X2) A M[PC], PC PC+1 Temp M[A] B M[PC], PC PC+1 M[B], AC SUB(Temp, M[B]) Memory mapped ALU
Instruction Set Architecture
PC Temp ALU(f) AC
CS510 Computer Architectures PC PC+1
M X1 X2 M[X1] M[X2]
Lecture 4 - 28
Why NOT Use a Minimal Instruction Set?
ADD X, Y a3: JMP X BN BN BN a1, a1, a3 a1, Y, a3 X, a1, a3 /M[a1] /M[a1] /M[X] 0 - M[Y] M[X] + M[Y]
Instruction Set Architecture
BN BN a1, a1, a3 a1, 1, X /M[a1] /AC 0 -1, PC X Inefficient Program Size(M bandwidth) - Large IC and CPI Programming difficulty
CS510 Computer Architectures Lecture 4 - 29
Instruction Set Design: Operations to Include in the Instruction Set
Trade-off 3 Es(Elegance, Efficiency, Environment) Elegance
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Completeness(Even Bn instruction is complete) Symmetry: Flexibility, Generality AC <= f(AC, M[X]) and M[X] <= f(AC, M[X]) Efficiency
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Space
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Bit budget
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Efficient specification of address
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Fewer instructions require fewer bits to encode OP-code
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Frequency of use arguments Bandwidth arguments(NOP simply waste memory bandwidth) Ratio of overheads: non-functional to functional Environment
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Multiprogramming(Relocation, Protection, Sharing) Code generation by compilers(Compiler favors only a little portion of instruction set)
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 30
ISA Metrics
• • • •
Aesthetics: Orthogonal
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No special registers, few special cases, all operand modes available with any data type or instruction type Completeness
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Support for a wide range of operations and target applications Regularity
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No overloading for the meanings of instruction fields Streamlined
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Resource needs easily determined Ease of compilation (programming?) Ease of implementation Scalability
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 31
Powerful Instruction
Conventional Instruction Cycle I-F I-P O-F E Instruction Fetch, Decode, Opd addr decision, and fetch Overhead for Execution(O) Execution (Operation) (E) Rich, Powerful Instruction: Instruction with longer Execution Time(E) to balance the overhead penalty(O) Instruction which has a large E/O IF IP OF E O E
Lecture 4 - 32 Instruction Set Architecture CS510 Computer Architectures
Powerful Instructions
• • •
Extended Arithmetic Function
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Multiply, divide, Trigonometric Functions, etc Automatic Indexing
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BCT R1, addr
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(R1 <- R1 - 1, if R1 = 0 then PC <- addr) BXLE R1, R3, addr (R1 <- R1 + R3, if R3=odd, R1 < R3, PC <- addr if R3=even, R1 < R3+1, PC <- addr) Subroutine Linkage
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JMS X (M[X] <- PC, PC <- X+1)
Lecture 4 - 33 Instruction Set Architecture CS510 Computer Architectures
Powerful Instructions
Process State Exchange(Context Switch): Instructions required in the multiprogramming environments LM R1, R5, addr R1 M[addr] R2 M[addr+1] … R5 M[addr+4] Otherwise LD R1, addr LD R2, addr+1 … LD R5, addr+4 SM R1, R5, addr M[addr] R1 M[addr+1] R2 … M[addr+4] R5 XJ (Exchange Jump of CDC 6000 series)
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 34
Basic ISA Classes: Type of Internal Storage Stack:
0-address ADD S[TOS] S[TOS] + S[TOS+1]
General Purpose Register:
2-address 3-address ADD A B ADD A B C S[EA(A)] S[EA(A)] + S[EA(B)] S[EA(A)] S[EA(B)] + S[EA(C)]
Accumulator:
1-address (1+x)-address ADD A ADDX A
Load/Store:
3-address AC AC + M[EA(A)] AC AC + M[EA(A + [X])] ADD Ra Rb Rc Ra Rb + Rc LD Ra B ST Ra B Ra M[EA(B)] M[EA(B)] Ra
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 35
Stack Machines
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Instruction set: Arithmetic operators(+, -, *, /, . . .) push A, pop A
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Example: a*b - (a+c*b) ab*(a(cb)*+) push a push b * push a push c push b * + B B A A A*B A*B A C A A*B C A A*B B*C A A*B B*C+A A*B (B*C+A)-A*B a * b a + c * b
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 36
The Case Against Stacks
• • • •
Performance is derived from the existence of several fast registers , not from the way they are organized Data does not always “ surface ” when needed
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Constants, repeated operands, common sub-expressions so TOP and Swap instructions are required Code density is about equal to that of GPR instruction sets
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Registers have short addresses Keep things in registers and reuse them Slightly simpler to write a poor compiler, but not an optimizing compiler
Lecture 4 - 37 Instruction Set Architecture CS510 Computer Architectures
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 38
GPR Machines GPR(General Purpose Register)
• • • •
Faster than memory Easier for a compiler to use Used to hold variables, intermediate operands
– –
the memory traffic reduces the code density improves How many registers?
–
depends on how they are used by the compiler
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 39
How Many Registers in RF
6 algorithms from CALGO(ACM) written in 4 languages; ALGOL,BASIC, BLISS,FORTRAN
Register Life
Life Length 1~1 2~3 4~7 8~15 16~31 32~63 64~127 128~ No. of Lives 174,927 728,346 547,072 252,508 116,404 41,673 17,790 15,603 Fraction Cum.
0.09
0.38
0.29
0.13
0.06
0.02
0.01
0.01
Fraction 0.09
0.48
0.77
0.90
0.96
0.98
0.99
1.00
Register Life . . .
R1 . . .
. . .
. . .
R1 . . .
f(R1) f(R1) We need to try to keep the live registers in the RF Avg number of simultaneous RL: 2 ~ 6 No program uses more than 15 registers simultaneously
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 40
GPR Machines
• •
Maximum number of operands(O)
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two or three operands Number of memory addresses(M)
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0,1,2,3 Type (M,O) No of memory addresses Maximum No of operands allowed (0,3) 0 3 (1,2) (2,2) (3,3) 1 2 3 2 Intel 80x86, Motorola 68000 2 3 Examples SPARC, MIPS, PowerPC, ALPHA VAX VAX
Lecture 4 - 41 Instruction Set Architecture CS510 Computer Architectures
GPR Machines
Type Register register (0,3) Register memory (1,2) Advantages Simple, fixed-length instr. encoding.
Simple code generation model Disadvantages Higher instruction count.
Some instructions are short and bit encoding may be wasteful.
Data can be accessed without loading first. Instruction format tends to be easy to encode and yields good density.
A source operand is destroyed.
Clocks per instruction varies by operand location.
Memory memory (3,3) Program becomes most compact. No waste of registers for temporaries.
Large variation in instruction sizes and in work per instruction. Memory accesses create memory bottleneck.
Example (0,3): ADD R1,R2,R3 (1,2): ADD R1, X (3,3): ADD X1,X2,X3
Instruction Set Architecture
R[R1] R[R2] + R[R3] R[R1] M[X1]
CS510 Computer Architectures
R[R1] + M[X] M[X2] + M[X3]
Lecture 4 - 42
R-R vs RM
A+B+C
Instruction Set Architecture
RR Instructions LD R1,A LD LD ADD ADD R2,B R3,C R4,R1,R2 R5,R4,R3 RM instructions LD ADD ADD R1,A R1,B R1,C RM instructions reduce IC
CS510 Computer Architectures Lecture 4 - 43
What About Actual Programs
Consider a GPR machine with a large register file.
- Highly probable that the intermediate data can be found in a register - Thus, LD/ST instruction will be used less frequently - However, frequency of using LD/ST instructions in the computers that use RM instructions will reduced further
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 44
VAX-11
Variable format, 2- and 3-address instructions Byte 0 1 OpCode A/M n A/M A/M m
• • • • •
32-bit word size, 16 GPR (4 reserved) Rich set of addressing modes (apply to any operand) Rich set of operations
–
bit field, stack, call, case, loop, string, poly, system Rich set of data types (B, W, L, Q, O, F, D, G, H) Condition codes
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 45
Kinds of Addressing Modes
OP Ri Rj v
• • • • • • • • • • •
Addressing Mode Register direct Immediate (literal) Direct (absolute) Register indirect Base+Displacement Base+Index Scaled Index Autoincrement Autodecrement Memory Indirect [Indirection Chains] value in [ ] is the operand [ Ri ] v M [v] M [[ Ri ]] M [[ Ri ] + v] M [[ Ri ] + [ Rj ]] M [[ Ri ] + [ Rj ]*d + v], eg. d=8 M [[ Ri ]+1] reg. file M [[ Ri ] - 1] M [ M [ Ri ] ] R memory M
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 46
%
60
Memory Addressing Modes (VAX)
55 50 43 40 40 39 32 Tex spice gcc 30 24 20 10 6 1 1 0 Memory Indirect
Instruction Set Architecture
16 17 11 6 3 0 Scaled Register deferred Immediate
CS510 Computer Architectures
Displacement
Lecture 4 - 47
Operand Address bits: Displacement Values
• • • •
This value is related to the operand address field when the address is represented by the displacement from the base address Wide distribution The vast majority --- positive A majority of the large displacements -negative
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 48
Operand Address bits: Immediate Addressing Mode
Percentage of operations that use immediates % 90 80 70 60 50 40 30 20 10 0 10 Loads 45 87 Compares 77 58 ALU op 78 35 All instr 10 Integer Avg.
FP Avg.
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 49
Operand Address bits: Immediate Addressing Mode
% 60 50 40 30 20 10 0 0 4 8 12 16 20 24 28 Number of bit needed for an immediate value 32 Cumulatively 8 bits : 50% to 70% 16 bits : 75% to 80 % gcc TeX spice
Lecture 4 - 50 Instruction Set Architecture CS510 Computer Architectures
Operations in the Instr. Set
Operator type Arithmetic and logical Data transfer Control System Floating Point Decimal String Graphics Examples Add, Subtract, … Load, Store, Move, … Branch, Jump, Procedure Call, Return, Trap Operating System Call, VMM instructions Floating Point Add Decimal Add, Decimal-to-Character Conversion String Move, String Compare, String Search Pixel operations, Compress/Decompress op.
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 51
Operations in the Instr. Set
Rank 4 5 6 1 2 3 7 8 9 10 Total
Instruction Set Architecture
80x86 instructions load conditional branch compare store add and sub move reg-reg call return Integer average (% total executed) 22% 20% 16% 12% 8% 6% 5% 4% 1% 1% 96%
CS510 Computer Architectures Lecture 4 - 52
Control Flow Instructions
% 90 80 70 60 50 40 30 20 10 13 0 Call/return
Instruction Set Architecture
11 81 87 6 4 Jump Conditional branch
CS510 Computer Architectures
Integer Avg.
FP Avg.
Lecture 4 - 53
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 54
RISC Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 55
Instruction Execution Characteristics: Type of Operations
Relative Dynamic Frequencies of statements in HLL programs Language Workload Assignment LOOP Call If goto others PASCAL FORTRAN PASCAL Scientific Student Systems 74 4 67 3 45 5 1 20 2 3 11 9 7 15 29 6 C Systems 38 3 12 43 3 1 SAL Systems 42 4 12 36 6 What type of statements is most frequent?
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Assignment statements dominate
»
Functional instructions and Transfer instructions
»
Movements of data must be made simple, thus fast
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Conditional Statements(if and loop together)
»
Instructions with Control function
»
Sequence control mechanism is important
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 56
Instruction Execution Characteristics: Time Consumed by Statements
Time Consumed Number of Machine Instructions Assignment Loop Call/Return If goto others Dynamic Occur PASCAL C 45 38 5 15 29 6 3 12 43 3 1 Machine Instr Wt PASCAL C 13 13 42 31 11 3 32 33 21 1 Memory Ref Wt PASCAL C 14 15 33 44 7 2 26 45 13 1 Machine instruction weighted = [Average No. of machine Instr. / Statements] x [Frequency of Occurrences] Memory reference weighted = [Average No. of memory references / Statement] x [Frequency of Occurrences] Most time consuming statement is procedure CALL/RETURN
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 57
Instruction Execution Characteristics: Type of Operands
Dynamic Frequencies of Occurrences Integer Constant Scalar Variable Array/Structure PASCAL 16 58 26 C 23 53 24 Average 20 55 25 Majority of references to scalar
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80% are local to a procedure
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References to arrays/structure require index or pointer Locations of operands(Average per instruction)
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0.5 operands in memory
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1.4 operands in registers
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 58
Instruction Execution Characteristics: Procedure Calls
• •
Two most significant aspects in implementing procedure Call/Returns
– –
Number of parameters Depth of nesting Statistics on Number of Parameters
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98% of dynamically called procedures were passed fewer than 6 parameters
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92% of them used fewer than 6 local scalar variables CALL SUB(X1, X2, X3) parameters SUB(A, B, C)
Lecture 4 - 59 Instruction Set Architecture CS510 Computer Architectures
Multiple Register Sets
Multiple register sets: - Assume that we have several sets of registers that each set can be used by each different procedure - Saves some time in procedure CALL/RETURN simply by changing the R set pointer value R set pointer
. . .
. . .
. . .
. . .
. . .
Instruction Set Architecture
Set 0 set 1 set 2 . . . Set n-1
CS510 Computer Architectures Lecture 4 - 60
Return
Instruction Execution Characteristics: Depth of Procedure Nesting
Procedure Nesting and Register Set Window t Nesting depth of 5 can be served with register set window of size 5 without using Memory Call Depth Register set window When Nesting depth > 5 - Movements of >5 in either direction(CALL/RETURN) needs to shift the register set window(down/up) Shifting register set window: need to save the information in one register set in the memory so that a register set can be used by the new procedure Statistics: Window depth of 8 will need to shift only on less than 1% of calls and returns
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 61
RISC Philosophy(1): Make the Most Frequent Statements Execute Fast
Most frequent statements are Assignment Type of Statements and each of them are translated by the compiler into a set of Functional Instructions and/or Transfer Instruction . Thus Functional and Transfer Instructions need to be made to execute fast.
Instruction Cycle of Functional Instruction or Transfer Instruction I-F(M) I-P O-F(M) E read istr. from M Decode/ effective addr read opd from M perform operation Short instruction Fixed instr. Format Simple addr. modes Have operands in registers Cannot do anything about it with an instr set Improved Architecture - Pipelined Execution
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 62
Assignment Statements
• • • •
To make the Instruction Fetch fast
– –
Short OP-code part: Small number of instructions in the instruction set Short Operand Address part: Make the operands in the registers instead of M To make the Instruction Preparation fast
– – –
Fixed length instruction Fixed format instruction Simple addressing modes To make the Operand Fetch fast
– –
Make the operands available from registers instead of memory Needs a large register file To make the Instruction Execution fast
– –
Multiple register set; Overlapping MRS Instruction execution pipeline
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 63
RISC Philosophy(2): Make the Most Time-Consuming Statements Execute Fast
Procedure Call and Return CALL SUB(X1, X2, X3) SUB(A, B, C) Methods of passing Parameters
•
Through memory
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Parameters are stored in the memory locations which are commonly accessible
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by both calling and called procedures Execution of CALL and RETURN instructions are very slow due to the memory accesses, especially when there are many parameters to pass
•
Through registers
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Parameters are stored in the registers in CPU
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Calling procedure needs to save the registers, which are not used for passing parameters, in the memory. This results in a lot of memory accesses and makes the execution times of these instructions slow.
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 64
CISC and RISC
Year developed No. of instructions Instruction length Addressing modes No. of GPR CM capacity IBM VAX S/360-168 11-780 73 78 208 16-48 303 16-456 4 16 420Kb 22 16 480Kb 6 4 Intel 8086 78 133 8-32 Berkeley IBM RISC I 801 81 80 31 32 120 32 3 138 0 5 32 0
• • •
RISC A limited and simple instruction set A large number of GPR(Register File) An emphasis on optimizing the instruction pipeline
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 65
Large Register File
Quick access to operands is desirable - Assignment Statements rely on Functional and Transfer Instructions - Functional Instructions heavily rely on registers - Frequency of Transfer Instructions depends on the number of registers in the register file If the number of registers is small, it needs a strategy to keep the most frequently accessed operands in registers to minimize Register-Memory traffic - Software approach Maximize register usage by compiler (Requires sophisticated program analysis) - Hardware approach More registers in the register file
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 66
Register Window
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Fact
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Statistically, most operand references are to local scalars - 80% Local variables to a procedure cannot be accessed by other procedure(s)
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Problem
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Local changes with each procedure CALL/RETURN CALL/RETURN occurs frequently Parameters need to be passed around
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Observations
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Statistically, a few parameters(<6) and local variables(<6) Statistically, depth of procedure activation fluctuates within relatively narrow range(<8)
•
Solution
– – –
Multiple small sets of registers Each set is assigned to a different procedures Windows for adjacent procedures overlap to allow parameter passing
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 67
Multiple Register Set
Register Set Pointer
...
...
… ...
...
Set 1 set 2 set 3 set m Each Register Set is assigned to a different procedure - Size of a Register Set is equal to the size of a window Parameters need to be copied in the called/calling procedure’s Register Set, however, there is no need to copy all the registers from the switched off register set - Require register move instructions
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 68
Overlapping Register Window
When multiple of Register Sets are implemented in a large Register File, we call a Register Set as a Register Window.
Multiple register sets still require to copy the parameter values between register sets.
Overlapping Register Window - Portions of register windows overlap for passing parameters - At any time only one window is visible - No need for moving information for parameter passing Procedure i Window i Parameter Local Temporary Registers Registers Registers CALL Same physical registers Exchange of parameters RETURN Window i+1 Parameter Local Temporary Registers Registers Registers Procedure i+1 How about global variables?
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 69
Global Variables
Global Variables are commonly accessible by all the procedures
• •
Assign to memory locations by compiler
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Straight forward but inefficient for the frequently accessed global variables because of frequent memory accesses Set aside a set of Global Variable registers
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Available to all procedures Unified register numbering system to simplify instruction format
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e.g.
R0 ~ R7: Global R8 ~ R13: Current window
Lecture 4 - 70 Instruction Set Architecture CS510 Computer Architectures
Linear Organization of Register Windows
Physical Register File Global Registers 0 p-1 Set 1 0 p-1 Set 2 0 p-1 p Set 3 .
0 p-1 p m-1 m-1 n-1 p m-1
Lecture 4 - 71 Instruction Set Architecture CS510 Computer Architectures
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 72
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 73
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 74
Code Size
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Smaller programs
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Program takes less memory space Smaller program improves performance
• • •
Fewer instructions Fewer bytes to fetch In paging environment, occupy in fewer pages and reduces page faults CISC
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Smaller number of instructions in the program(program may be shorter but not necessarily smaller space)
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 75
CISC
Example
A B + C Compare total MB 8 4+12 4+12 4+12 Memory Traffic Instruction: Data: Total MB used: 56 bits 32 x 3 = 96 bits 56 + 96 = 152 bits RISC 8 4 4 12 LD Rb B LD Rc C ADD Ra Rb Rc ST Ra A Memory Traffic Instruction: Data: Total MB used: 112 bits 96 bits 200 bits CISC: More instructions in the instructions set Longer OP-code RISC: More chances of storing intermediate results in registers Less use of LD/ST
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 76
Characteristic of RISC(1, 2)
(1) 1 Instruction per cycle(memory cycle)
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Machine cycle: IF + IP + Time to fetch the operands from registers + Perform operation + Store the result in a register
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RISC instruction <=> CISC micro-instruction => No need to microprogram(Hardwired control) (2) Register-to-Register operation
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With only simple Load and Store operations for accessing memory(Load/Store Arch.)
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Simplifies the instruction set, and control unit B B+C A A+B D D- A CISC-I Data: OP-code: 32 bits 8 bits Reg Address: 4 bits M address: MM instr- 12 + 4 bits RISC -- 12 bits ADD B,C, B ADD A, B, A ADD D, A, D I: 56 x 3 = 168 bits D: 96 x 3 = 288 bits Total MB: 456 bits Cycles: 3 x 4 = 12
Instruction Set Architecture CS510 Computer Architectures
RISC ADD Rb, Rc, Rb ADD Ra, Rb, Ra ADD Rd, Ra, Rd I: 28 x 3 = 84 bits D: 0 bits Total MB: 84 bits Cycles: 3 x 1 = 3
Lecture 4 - 77
Characteristic of RISC(3, 4)
(3) Simple Addressing Modes - Shorten EA generation time
– – –
Almost all instructions use register addressing Relative addressing using PC, BAR, and Index address Other complex modes may be synthesized by software OP-code . . . Rs1 S2 Addressing Modes Immediate Direct Register Register Indirect Displacement Effective Address Operand=A EA = A EA = R EA = [R] EA = [R] + A Synthesis S2 0 + S2 Rs1, S2 Rs1 + 0 Rs1 + S2 Used by R-to-R LD/ST R-to-R LD/ST LD/ST (4) Simple Instruction Format - Shorten instruction Decoding Time
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Usually one format
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Fixed length/align on word boundary Fixed field length
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 78
Characteristic of RISC(5)
(5) Pipelining (We will learn this later in detail) At this time, you just need to know that - Instruction execution hardware can be made of a few inter- connected independent sub-modules, called pipeline STAGEs S0 S1 S2 S3 - An instruction execution progresses at each pipeline stage in sequence - When an instruction completes its execution at the i-th stage, the next instruction commences its execution at the i-th stage - Thus, in the ideal situation, throughput increases nearly n times, where n is the number of pipeline stages - Branch instruction makes the pipelined execution inefficient
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 79
Pipelined Execution
S0 S1 S2 S3 1 instruction execution I 0 I 0 I 0 I 0 Execution of a Sequence of Instructions I 0 I 0 I 0 completes at (t x 4) I 1 I I I 1 2 3 I I 2 3 I I 1 2 S0 I 4
Instruction Set Architecture CS510 Computer Architectures
At 4t: I 0 At 5t: I 1 At 6t: I 2 At 7t: I 3 N instructions complete at (n+3)t When n is large it becomes nt Thus, 1 instruction in every t At 8t: I 4
Lecture 4 - 80
A "Typical" RISC
• • • • • •
32-bit fixed format instruction (3 formats) 32 32-bit GPR (R0 contains zero, DP takes a pair) 3-address, R-R functional instruction Single address mode for load/store: base + displacement
»
no indirection Simple branch conditions Delayed branch see: SPARC, MIPS, MC88100, AMD2900, i960, i860 PARisc, DEC Alpha, Clipper, CDC 6600, CDC 7600, Cray-1, Cray-2, Cray-3
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 81
Branch Displacement
%
40 35 30 25 20 15 10 5 0
Instruction Set Architecture
Bits of branch displcament
CS510 Computer Architectures
FP Avg.
Int. Avg.
Lecture 4 - 82
Implementation of Conditional Branch Instructions
Name Condition Code(CC) Condition Register Compare and Branch Evaluating branch conditions How condition is tested Advantages Disadvantages Test special bits set by ALU operations, possibly under program control.
Sometimes condition is set for free, if not 2 instr’s for a branch.
CC is an extra state. CCs constrain the ordering of instrs since they pass info from one instr to a branch.
Test arbitrary registers set by the result of a comparison.
Simple.
2 instr’s for a branch Compare is part of the branch.
Often compare is limited to subset.
1 instr. rather than 2 for a branch Uses up a register.
May be too much work per instruction.
Lecture 4 - 83 Instruction Set Architecture CS510 Computer Architectures
Putting It All Together: DLX Architecture
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Read Section 2.8 ---- MUST
• • • •
DLX emphasizes A simple load-store instruction set Design for pipelining efficiency A fixed instr. set encoding Efficiency as a compiler target
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 84
Example: MIPS
Register-Register 31 26 25 Op Rs1 21 20 Rs2 16 15 Rd 11 10 Register-Immediate 31 26 25 21 20 Op Rs1 Rd 16 15 Branch 31 Op 26 25 Rs1 21 20 16 15 Rs2/Opx 6 5 immediate immediate Opx Jump / Call 31 26 25 Op target 0 0 0 0
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 85
The Different Goals for VAX and MIPS
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VAX - simple compilers and code density
– – – –
powerful addressing modes powerful instructions efficient instruction encoding few registers MIPS high performance via pipelining, ease of HW implementation, compatibility with highly optimizing compiler
– – – –
simple instruction simple addressing modes fixed-length instruction formats a large number of registers
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 86
VAX vs. MIPS
2 1.5
1 0.5
0 4.5
4 3.5
3 2.5
Instruction Set Architecture CS510 Computer Architectures
MIPS/VAX
CPI ratio(MIPS/VAX) Instructions executed ratio Performance ratio (IC, CPI, Cycle Time)
Lecture 4 - 87
Fallacies and Pitfalls
Pitfall : Designing a “high-level” instruction set feature specifically oriented to supporting a high-level language structure.
Fallacy : There is such a thing as a typical program.
Fallacy : An architecture with flaws cannot be successful.
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80x86: supports Segmentation while other support page Extended AC for integer, while others use GPR Stack for FP operations, while others abandoned stack
Fallacy : You can design a flawless architecture.
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All architecture design involves trade-off made in the context of a set of HW and SW technologies.
Lecture 4 - 88 Instruction Set Architecture CS510 Computer Architectures
Most Popular ISA of All Time: Intel 80x86
• • •
1971 : Intel invents microprocessor 4004/8008, 8080 in 1975 1975 : Gordon Moore realized one more chance for new ISA before ISA locked in for decades
» » »
Hired CS people in Oregon Weren’t ready in 1977 (CS people did 432 in 1980) Started crash effort for 16-bit microcomputer 1978 : 8086 dedicated registers, segmented address, 16- bit
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8088; 8-bit external bus version of 8086; added as after thought
Lecture 4 - 89 Instruction Set Architecture CS510 Computer Architectures
Most Popular ISA of All Time: Intel 80x86
• • • • •
1980 : IBM selects 8088 as basis for IBM PC 1980 : 8087 floating point coprocessor: adds 60 instructions using hybrid stack/register scheme 1982 : 80286 24-bit address, protection, memory mapping 1985 : 80386 32-bit address, 32-bit GP registers, paging 1989 : 80486 & Pentium in 1992: faster + MP few instructions
Lecture 4 - 90 Instruction Set Architecture CS510 Computer Architectures
80x86 Addressing/Protection
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 91
80x86 Instruction Format
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8086 in blue ; 80386 extensions in red Repeat Lock Seg. Override Addr. Override Size Override OP- code OP-code Ext.
Mod, reg,n/m SC, index,base Disp8 Disp16 Disp24 Disp32 Imm8 Imm16 Imm24 Imm32
} } }
Prefixes OP-code Address Displacement
}
Immediate (Base reg + 2 Scale x Index reg)
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 92
80x86 Instruction Encoding: Address Specifier Field: Mod, Reg, R/M
r w=0 w=1 r/m mod=0 16b32b 0 AL AX EAX 0 1 CL CX ECX 1 2 DL DX EDX 2 3 BL BX EBX 3 4 AH SP ESP 4 5 CH BP EBP 5 6 DH SI ESI 6 7 BH DI EDI 7 16b 32b addr=BX+SI =EAX addr=BX+DI =ECX addr=BP+SI =EDX addr=BP+SI =EBX addr=SI =( sib ) addr=DI addr=d16 addr=BX =d32 =ESI =EDI 16b
same addr mod=0 +d8
SI+d8 DI+d8 BP+d8 BX+d8 mod=1 mod=2 mod=3 32b 16b 32b
same addr same addr same addr same as mod=0 mod=0 mod=0 reg +d8 +d16 +d32 field
( sib )+d8 SI+d8 ( sib )+d32 “ EBP+d8 DI+d16 EBP+d32 “ ESI+d8 EDI+d8 BP+d16 ESI+d32 “ BX+d16 EDI+d32
“
w from OPcode r/m field depends on mod and machine mode Data Registers Pointers/Index Reg AX: AC BX: Base Address CX: Counter Dx: Data SP: Stack Pointer BP: Base Pointer SI: Source Index DI: Destin. Index
Instruction Set Architecture CS510 Computer Architectures
Address Specifier: Reg=3 bits, R/M=3 bits, Mod=2 bits
Lecture 4 - 93
80x86 Instruction Encoding: Sc/Index/Base field
r Index Base
0 1 2 3 4 5 6 7 EAX ECX EDX EBX EBP ESI EDI EAX if mod<>0, EBP ESI EDI
Base + Scaled Index Mode
Used when: mod = 0,1,2 in 32-bit mode and r/m = 4 2-bit Scale Field 3-bit Index Field 3-bit Base Field
Lecture 4 - 94 Instruction Set Architecture CS510 Computer Architectures
80x86 Addressing Mode Usage for 32-bit Mode
Addressing Mode Gcc Register indirect
Base + 8-bit disp
Base + 32-bit disp Indexed Based indexed + 8b disp Based indexed + 32b disp Base + Scaled Indexed Base + Scaled Index + 8b disp Base + Scaled Index + 32b disp
32-bit Direct
Espr.
10% 46%
2% 1% 0% 0%
12%
2% 6%
19%
NASA7 Spice
10% 43%
0% 0% 0% 0%
31%
1% 2%
12%
6%
32% 24%
1% 4% 0% 9% 2% 2%
20%
Avg.
2% 4%
10%
0% 0% 0% 0% 0%
33% 51%
7%
31%
9% 1% 1% 0%
13%
1%
11% 26% Lecture 4 - 95 Instruction Set Architecture CS510 Computer Architectures
11
80x86 Length Distribution
10
9 8 7 6 0% 0% 1% 1% 0% 0% 0% 0% 0% 0% 0% 0% 2% 2% 4% 3% 4% 6% 27%
5
13% 12% 13% 15% 12%
4
1%
3%
4% 3% 3
2 1
16% 17% 19% 21% 24% 24% 23% 25% 24% 24% 27% 29%
0% 10% 20%
% instructions at each length
Instruction Set Architecture
30%
CS510 Computer Architectures
Espresso Gcc Spice NASA7
Lecture 4 - 96
Instruction Counts: 80x86 vs. DLX
SPEC pgm x86 DLX
gcc 3,771,327,742 3,892,063,460 espresso 2,216,423,413 2,801,294,286 spice nasa7 15,257,026,309 16,965,928,788 15,603,040,963 6,118,740,321
DLX/86
1.03
1.26
1.11
0.39
Instruction Set Architecture CS510 Computer Architectures Lecture 4 - 97
Intel Compiler vs. Compilers YOU Can Buy
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66 MHz Pentium Comparison Intel Internal Optimizing Compiler Best 486 Compiler (June 1993) SpecInt92 64.6
57.6
SpecFP92 59.7
39.9
• •
Typical 486 Compiler in 1990, when Intel started project 41.0
32.5
•
Integer: Intel 1.1X faster, FP: 1.5X faster ……………………………………………………………………….
486 Comparison SpecInt92 SpecFP92 Intel Internal Optimizing Compiler 35.5
17.5
32.2
16.0
Best 486 Compiler (June 1993) Typical 486 Compiler in 1990, when Intel started project Integer: Intel 1.1X faster, FP: 1.1X faster 23.0
12.8
Lecture 4 - 98 Instruction Set Architecture CS510 Computer Architectures
Intel Summary
• • • • •
Archeology: history of instruction design in a single product
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Address size: 16 bit vs. 32-bit
– –
Protection: Segmentation vs. paged Temp. storage: accumulator vs. stack vs. registers “Golden Handcuffs”of binary compatibility affect design 20 years later, as Moore predicted Not too difficult to make faster, as Intel has shown HP/Intel announcement of common future instruction set by 2000 means end of 80x86???
“Beauty is in the eye of the beholder”
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At 50M/year sold, it is a beautiful business
Lecture 4 - 99 Instruction Set Architecture CS510 Computer Architectures