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CS 301 Fall 2002 Computer Organization Slide Set 2 7/7/2015 1 Processors – the 808x line 7/7/2015 Processor Data bus Registers Address space Modes 8088 8-bit 16-bit 1 Megabyte Real 8086 16-bit 16-bit 1 Megabyte R 80286 16-bit 16-bit 16 Megabytes R, Protected 80386 32-bit 32-bit 4 Gigabytes R, P 80486 32-bit 32-bit 4 Gigabytes and cache R, P Pentium 32-bit 64-bit 4 Gigabytes and separate caches R, P Pentium II, III, 4 As Pentium, but Dual Independent Bus for separate paths to cache and memory. 2 Pipelining and other speedups Each more advanced processor does more at once (pipelining) Branch prediction (because processors are faster than memory) 7/7/2015 3 Parts of the CPU Execution Unit: registers, control unit (CU), arithmetic and logic unit (ALU) – executes instructions BIU: brings instructions to EU, manages segment registers and instruction queue. 7/7/2015 4 Internal Memory RAM – random access memory ROM – read only memory 808x processors that handle more than one byte at a time store the most significant byte in the high memory address and the low order byte in the low address. 7/7/2015 5 Real Mode 8086/8088 and up have real mode. Segment registers are 16-bit, addressable space is 00000h to FFFFFh. How do you use 16-bit registers to address into a memory space that requires a 20-bit number? Use two 16 bit values to determine an address. Multiply the first by 10h and add the second. 7/7/2015 6 16-bit protected mode Introduced with 80286, selector values (contents of segment registers) are indexes into a descriptor table. In protected mode, each segment is assigned an entry into a descriptor table. The entry contains all information the system needs to know, such as if it is currently in memory (virtual memory), where it is in memory, its access permissions, etc. Major disadvantage is that offsets are still 16-bit quantities, meaning each segment contains at most 64K. 7/7/2015 7 32-bit protected mode Introduced with 80386, similar to 16-bit protected mode except offsets are now 32 bits, so segments can contain up to 4 gigabytes. Divides segments up into pages of 4K. Virtual memory now works with pages instead of entire segments. 7/7/2015 8 Segment Registers 1 CS register – contains starting address of the code segment. Along with IP, [CS:IP] gives the address of the instruction to be fetched for execution. DS register – contains starting address of the data segment. Used with offsets included in instructions. 7/7/2015 9 Segment Registers 2 SS register – For the stack segment, used as [SS:SP]. Also (in subroutines) [SS:BP]. ES register – Used (as [ES:DI]) by some string operations to handle memory addressing. FS and GS registers – Additional extra segment registers introduced with 80386 processor. 7/7/2015 10 Pointer Registers The 32 bit pointer registers are EIP, ESP, and EBP. Their rightmost 16 bits are called IP, SP, and BP. Pointer registers are offsets to be combined with segment registers. IP is used with CS, SP and BP are used with SS. 7/7/2015 11 General Registers 1 The 32-bit registers are EAX, EBX, ECX, EDX. Their rightmost 16 bits are AX, BX, etc. Of those 16 bits, the leftmost byte (high bits) are AH, BH, etc. and the rightmost byte (low bits) are AL, BL, etc. AH AL AX EAX 7/7/2015 12 General Registers 2 AX – the primary accumulator is used for I/O and most arithmetic (such as multiply, divide, and translate). Many instructions generate more efficient machine code if the reference AX rather than some other register. BX – the base register. BX is the only general purpose register that can be used as an index to extend addressing. BX is also often used for computation and with SI or SI as a base register. 7/7/2015 13 General Registers 3 CX is called the count register. It is often used as a loop index, or a value to shift bits left or right. DX is called the data register. Some I/O operations require it, and large multiplication and division operations use it along with AX as a pair. 7/7/2015 14 Index Registers ESI and EDI are the 32-bit index registers, their rightmost 16 bits are SI and DI respectively. SI is the “source index register” associated with DS for some string operations DI is the “destination index register” associated with ES for some string operations. 7/7/2015 15 Flag Register The 32-bit EFLAGS contains bits indicating the status of various activities. The rightmost 16 bits of EFLAGS is the FLAGS register, nine of its 16 bits indicate the status and results of processing. Many instructions change the status of these flags, other instructions test the flags to determine later action. 7/7/2015 16 Flag bits 1 OF (overflow) Indicates overflow of the leftmost bit during arithmetic. DF (direction) Indicates left or right for moving or comparing string data. IF (interrupt) Indicates whether external interrupts are being processed or ignored. TF (trap) Permits operation of the processor in single step mode. 7/7/2015 17 Flag bits 2 SF (sign) Contains the resulting sign of an arithmetic operation (1=negative) ZF (zero) Indicates when the result of arithmetic or a comparison is zero. (1=yes) AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized arithmetic. PF (parity) Indicates the number of 1 bits that result from an operation. 7/7/2015 18 Flag bits 3 CF (carry) Contains carry from leftmost bit following arithmetic, also contains last bit from a shift or rotate operation. Flag Bit no. 7/7/2015 15 14 13 12 O D I T S Z 11 10 9 8 7 6 A 5 4 P 3 2 C 1 0 19 Hardware Interrupts Some events cause the processor to stop what it is doing and act immediately on something else. Usually these are normal such as keyboard input, but sometimes they are critical, such as divide by zero. There are also software interrupts, such as a request by the program to display data on the screen. After an interrupt is processed the processor returns to what it was doing. 7/7/2015 20