Transcript Introduction to Microprocessors and Microcomputers

Lecture 1: Introduction to
Microprocessors and Microcomputers
Seungryoul Maeng
Computer Science, KAIST
Fall 2000
1
The History of Intel’s Microprocessors
• Pentium III
–
–
–
–
–
1999
Pentium Pro + MMX + Internet Streaming SIMD Instructions
0.25 micron, 9.5 million Trs
600 MHz, 550 MHz,...
32 K(16K/16K) non-blocking level 1 cache
Maeng Lect01-2
IBM PC/AT and ISA Bus
3
Pentium Processor/82430 PCIset ISA
Host Bus
Pentium Processor
CNTL
ADDR
DATA
Latch
82434
PCMC
SRAM
PCI BUS
DRAM
82433
LBX
CNTL
ADDR/DATA
82378 SIO
Graphics
PCI devices
ISA BUS
Maeng Lect01-4
ISA Bus Interface Signals
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
Name
I/O CH CK*
D7
D6
D5
D4
D3
D2
D1
D0
I/O CH RDY
AEN
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
Ty pe
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Pin
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
Name
GND
RESET DRV
+5V
IRQ2
-5V
DRQ2
-12V
RESERVED
+12V
GND
SMEMW*
SMEMR*
IOW*
IOR*
DACK3*
DRQ3
DACK1*
DRQ1
REFRESH*
CLOCK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
DACK2*
T/C
BALE
+5V
OSC
Ty pe
O
I
I
O
O
O
O
O
I
O
I
O
O
I
I
I
I
I
O
O
O
O
Maeng Lect01-5
ISA Bus Interface Signals
Pin
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
Name
SBHE*
LA23
LA22
LA21
LA20
LA19
LA18
LA17
MEMR*
MEMW*
SD08
SD09
SD10
SD11
SD12
SD13
SD14
SD15
Ty pe
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pin
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
Name
MEM CS 16 *
IO CS 16*
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
DACK0*
DRQ0
DACK5*
DRQ5
DACK6*
DRQ6
DACK7*
DRQ7
+5V
MASTER*
GND
Ty pe
I
I
I
I
I
I
I
O
I
O
I
O
I
O
I
I
Maeng Lect01-6
Block Diagram of the System Board
data
data
DMA
•
•
MEM
addr
ISA Bus
addr
CPU
External
Master
Memory
I/O
All signal lines are TTL compatible. Fan-out are two low power Shottkey(LS) TTLs.
SA0 through SA19: System Address Bus:(I/O)
–
–
–
–
to address memory and I/O devices; 16MB of memory with LA17 through LA23
input when CPUHLDA is high and MASTER* is low; output at all other times
SA bus driven by CPU when CPUHLDA is low; SA bus driven by 8237 DMA controller when
CPUHLDA is high
latched with an internally generated ALE signal
Maeng Lect01-7
Lect 2: Real Addressed Mode S/W
Architecture of the 80386DX
Microprocessor
8
386DX Microprocessor
• Internal Architecture
Maeng Lect01-9
Real-Mode Software Architecture
• reset -> real mode; object code compatible with 8086
• Real-mode software model
Maeng Lect01-10
Pointer and GPR
Instruction Pointer (2.7)
• 16-bit IP in real mode
– next code address : CS:IP
General Purpose Data Registers (2.8)
EAX
Accumulator (A): ASCII Adjust, ......
AX
AH
AL
Base (B) : table-lookup translations
Count (C): loop operations, repeat string operations, shift/rotate
Data (D): indirect I/O, I/O string, Multi, Divide
Maeng Lect01-11
Pointer and GPR
Maeng Lect01-12
Pointers and Index Registers (2.9)
•
two index registers (ESI, EDI) and two pointer registers (EBP, ESP);
•
•
contains offset addresses (16-bit in real mode: 64 KB)
ESP(extended stack pointer) and EBP(extended base pointer)
– combined with the contents of the SS register to produce physical memory
address
– TOS (top of stack) : SS:SP
– BP : an offset relative to the SS register
Maeng Lect01-13
Flag Register (2.9)
•
ESI (extended source index register) and EDI (extended destination index
register)
– automatically combined with the value in the DS register
FLAGS REGISTER (2.10)
•
32-bit flags; just nine of its bits are active in the real mode
Maeng Lect01-14
Generating A Real-Mode Memory Addresses (2.11)
• Real-mode physical address generation :
Type of Reference
Segment Used
Register Used
Code Segment
CS register
Default Selection Rule
Stack
Stack Segment
SS register
All stack pushes and pops. Any
memory reference which uses
ESP or EBP ad a base register.
Local Data
Data Segment
DS register
All data references except when
relative to stack or string destination
Destination String
E-segment
ES register
Destination of string instrs
Instructions
Automatic with instruction fetch
Maeng Lect01-15
Example
1 2 3 4
1 2 3 4
Segment
Base
0
0 0 2 2
0 0 2
2
1 2 3 6
2
Logical
Address
Offset
Physical Address
Maeng Lect01-16
Real-Mode Input/Output Address Space (2.13)
Maeng Lect01-17
Lect 3: Instruction Set and
Addressing Modes
18
386 Instruction Set (3.4)
– Basic Instruction Set : 8086/8088 instruction set
– Extended Instruction Set : 80286; several new instructions and
additional addressing modes
– 80386 specific instruction set:
8086/8088
Basic
Instruction
Set
80286
80386
Protected Mode
System control
Instruction set
System control
Instruction set
Basic +
Extended
Instruction
Set
Basic +
Extended+
80386 specific
Instruction
Set
Real Mode
Maeng Lect01-19
386 Instruction Set (3.4)
• Addressing Modes of 386DX (3.5)
– Addressing Modes: a method of specifying an operand
• Operands : in REG, Memory, I/O ports, and within Instruction
– * Control Transfer : direct, indirect addressing
– the modes available
register addressing : REG
immediate addressing: within Instruction
direct addressing
register indirect addressing
based addressing
MEM or I/O
indexed addressing
based indexed addressing
Maeng Lect01-20
Lect 4: Instruction Encoding and
Instruction Set
21
Instruction Encoding
General Instruction Format
TTTTTTTT
7
0
TTTTTTTT
7
0
opcode
(one or two bytes)
(T represents an
opcode bit.)
mod TTT r/m
7 6 5 32 0
“mode r/m”
byte
ss index base
76 5 3 2 0
“s-i-b”
byte
d32| 16 | 8 | none
data32 |16 |8 | none
address
displacement
immediate
data
register and address
mode specifier
Field Name
Description
Number of Bits
w
d
s
reg
mod r/m
Specifies if data is byte or full size (Full size is either 16 or 32 bits)
Specifies Direction of Data Operation
Specifies if an Immediate Data Field Must Sign-Extended
General Register Specifier
Address Mode Specifier (Effective Address can be a General
Register)
Scale Factor for Scaled Index Address Mode
General Register to be used as Index Register
General Register to be used as Base Register
Segment Register Specifier for CS, SS, DS, ES
Segment Register Specifier for CS, SS, DS, ES, FS, GS
For a Conditional Instructions, Specifies a Condition Asserted or a
Condition Negated
1
1
1
3
2 for mod;
3 for r/m
2
3
3
2
3
ss
index
base
sreg2
sreg3
tttn
4
Maeng Lect01-22
Encoding the instruction in Machine code
• Example:
– MOV BL, AL ; MOV opcode byte: 100010dw
• d = 0 REG field is source; w =1 for word operation; mod r/m = 11
011; REG = 000
• First byte : 10001000 (88H); Second byte: 11 000 011 (C3H)
– ADD [BX][DI]+1234H, AX; ADD opcode byte : 000000dw
• d=0 REG field is source; w =1 for word operation; mod r/m = 10 001;
REG = 000
• First byte : 00000001 (01H); Second byte: 10 000 001 (81H)
• Resulting Machine code: 01813412H
Maeng Lect01-23
80386 Instruction Set
• 80386 base instruction set encoding table: See Fig 4.5
• Instruction Types
–
–
–
–
–
–
–
–
General Data Transfer
Arithmetic/Logic
Shift/Rotate
Bit test and bit scan
Flag Control
Control Transfer
String handling
System Control
Maeng Lect01-24
Control Transfer
– Stack Frame Instructions: ENTER and LEAVE
• to allocate and deallocate a data area called a stack frame
• ENTER : make a stack frame
– ENTER imm16,0; Make procedure stack frame
– ENTER imm16,1; Make stack frame for procedure parameter
– ENTER imm16,imm8: Make stack frame for procedure
parameter
– first operand : the number of bytes to be allocated on the stack
for local data storage
second operand: lexical nesting level of the routine
Maeng Lect01-25
Control Transfer
Data for Proc. C
(16 bytes)
BP when executing
Procedure C
BP for Proc. C
BP for Proc. B
BP for Proc. A
BP for Proc. B
Ret addr for proc. B
Procedure A
Procedure B
Enter 32, 1
Enter 12, 2
Leave
Ret
Leave
Ret
Procedure C
Enter 16, 3
Stack
frame
for C
Leave
Ret
Data for Proc. B
(12 bytes)
BP when executing
Procedure B
BP for Proc. B
BP for Proc. A
BP for Proc. A
Ret addr for proc. A
Data for Proc. A
(32 bytes)
BP when executing
Procedure A
Stack frame
for B
Stack frame
for A
BP for Proc. A
Old BP
Maeng Lect01-26
String Handling
• Loop and Loop-handling Instructions
– LOOP, LOOPE/Z, LOOPNE/NZ: CX must be preloaded with a count
• String and String-Handling Instructions
– MOVSB/W/D, compare string, scan string, load string, store string
– the contents of both SI and DI are automatically incremented or
decremented.
– REP : repeat string;
• Check Array Index Against Bounds
– BOUND r16, m16&16 : check if r16 is within bounds
– BOUND r32, m32&m32: check if r32 is within bounds
operation: if (LeftSRC < [RightSRC] or LeftSRC>
[RightSRC+OperandSize/8])
then Interrupt 5;
Maeng Lect01-27
Lect 5: Protected-Mode Software
Architecture
28
Protected-Mode Register Model
•
•
•
•
•
•
•
•
•
EIP
CS
DS
SS
ES
FS
GS
AX
BX
CX
DX
SP
BP
SI
DI
EFLAGS
47
0
16 15
Base
Base
GDTR
IDTR
LDTR
Limit
Limit
MSW
CR0
CR1
CR2
CR3
TR
GDTR : global descriptor table
LDTR : local descriptor table
IDTR : interrupt descriptor table
TR : task register
EIP : 32 bits in length
EFLAGS
CR0, CR1, CR2, CR3
DR0-DR7(Debug registers)
TR6-TR7(Test registers)
DR0
DR1
DR2
DR3
DR4
DR5
DR6
DR7
TR6
TR7
Maeng Lect01-29
Segment Descriptors
• Descriptor:
– the element by which the on-chip memory manager hardware manages the
segmentation of the 80386DX’s 64T-byte virtual memory address space.
– One descriptor exists for each segment of memory in virtual address space.
– 8 bytes long and contains three kinds of information
• Limit
• Base
• Access Rights
– Types of segment descriptors
• system segment descriptor(s=0), non-system segment
descriptor(s=1)(code and data)
Maeng Lect01-30
Segment Descriptors
32
3
BASE 31..24
23
G X 0
16
AVL
7
24
SEGMENT BASE 15 .. 0
LIMIT
19..16
15
P
8
DPL
S
TYPE
A
7
0
BASE 23..16
SEGMENT LIMIT 15 .. 0
4
0
Maeng Lect01-31
Global Descriptor Table
• Global Descriptor Table
– GDT provides a mechanism for defining the characteristics of the 386
global memory address space. Global memory is a general system
resource that is shared by many or all software tasks.
– contains system segment descriptors
8191
Global Descriptor Table Register(GDTR)
16 15
47
BASE
0
Global
Descriptor
Table
(GDT)
MAX: 64k bytes
8K entries
LIMIT
1
0
Maeng Lect01-32
Interrupt Descriptor Table
• Interrupt Descriptor Table (IDT)
– contains interrupt descriptors, not segment descriptors
– IDT can also be up to 64KB; But 386 only supports up to 256 interrupts
and exceptions(2KB)
255
Interrupt Descriptor Table Register(IDTR)
16 15
47
BASE
0
Interrupt
Descriptor
Table
(IDT)
MAX: 2k bytes
256 entries
LIMIT
1
0
Maeng Lect01-33
Local Descriptor Table
• Local Descriptor Table
– Each task can have access to own private descriptor table(LDT) in
addition to GDT.
– contains descriptors that provide access to code and data in segments of
memory
GDTR
15
0
LIMIT
31



GDT
BASE
15
LDTR
0
selector



LDT0
LDTR
0
15
cache
LIMIT
31
BASE
program invisible



LDTn
Maeng Lect01-34
Control Registers
31
23
15
7
0
Page Directory Base Register
CR3
Page Fault Linear Address
CR2
CR1
RESERVED
P
G
RESERVED
TEM P
R SMP E
CR0
MP: math present
EM: emulate
R: extension type
TS: task switched
• MSW : CR0
– the lower 5 bits of CR0 are system-control flags
– PE: protected-mode enable bit
• At reset, PE is cleared.(real mode)
• Set PE to 1 to enter protected mode
• Once in protected mode, 386 cannot be switched back to real
mode under SW control
Maeng Lect01-35
Register With Changed Functionality
SEGMENT SELECTOR REGISTER
INDEX
T
I
RPL
1-0
Requested
Privilege
Level(RPL)
Indicates selector privilege
level desired
2
Table Indicator
(TI)
TI=0 use global descriptor table (GDT)
TI=1 use local descriptor table (LDT)
15-3
Index
select descriptor entry in table
– Example: CS: 1007H, GDT base 00100000H, LDT base
00120000H
• (CS) = 0001 0000 0000 0111 : RPL = 3, TI =1, Index = 0001
0000 0000 0
• Address of the segment descriptor = 00120000H + 1000H =
00121000H
Maeng Lect01-36
Protected Memory Management and
Address Translation
• Virtual Address and Virtual Address Space
– virtual address : selector(16-bit): offset(32-bit)
47
32
offset
selector
–
INDEX
214(16,384
0
31
T
I
RPL
= 16K) unique segments of memory, each of which has a
maximum size of 4G bytes
– Total virtual address space = 246 , 64 TB
Maeng Lect01-37
Physical Address Space and Virtual-toPhysical Address Translation
SELECTOR
OFFSET
LOGICAL ADDRESS
SEGMENT
TRANSLATION
PAGING DISABLED
PG?
PAGING ENABLED
0
31
LINEAR ADDRESS
DIR
PAGE
OFFSET
PAGE
TRANSLATION
PHYSICAL ADDRESS
Maeng Lect01-38
Segmentation Virtual to Physical Address
Translation
OFFSET
SELECTOR
LOGICAL ADDRESS
Selector
Offset(EBX)
(DS)
SEGMENT
TRANSLATION
Data
Segment
PAGING DISABLED
Operand
PG?
PAGING ENABLED
0
31
LINEAR ADDRESS
DIR
PAGE
OFFSET
PAGE
TRANSLATION
Data Segment
Descriptor
Cache Register
Segment
Descriptor
LDT
PHYSICAL ADDRESS
Maeng Lect01-39
Segment Selector Register and the Cache
Registers
Transparently Loaded by MPU
Programmer
accessible
Selectors
Access Rights
Base Address
Limit
CS
DS
64-bit Segment
Descriptor
Cache Registers
SS
ES
FS
GS
63
52 51
20 19
0
Maeng Lect01-40