Test generation
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Transcript Test generation
2. Sissejuhatus teooriasse
1.
2.
Teooria: Boole’i differentsiaalvõrrand
Teooria: Binaarsed otsustusdiagrammid
4
Rike
2
Testi süntees
Test
1
Digitaalsüsteem
Diagnoos
Reaktsioon
Stiimul
Diagnostika
sõnastik
Testi analüüs – rikete simuleerimine
3
Technical University Tallinn,
ESTONIA
1
Fault Propagation Problem
Logic gate
Logic circuit
Path activation
Correct
signal
Fault
activation
1
0
&
1 0
Error
Fault
activation
x3 = 1
Fault
Stuck-at-0
Path
activation
Correct
signal
x1 0
x2 1
x4 0
x5
x6 0
x7
1 0
y
F (X)
Error
Fault“Stuck-at-1”
Technical University Tallinn,
ESTONIA
2
Boolean derivatives
Boolean function:
Y = F(x) = F(x1, x2, … , xn)
Boolean partial derivative:
F ( X )
F ( x1 ,...xi ,...xn ) F ( x1 ,...x i ,...xn )
xi
F ( X )
F ( x1 ,...xi 0,...xn ) F ( x1 ,...xi 1,...xn )
xi
Technical University Tallinn,
ESTONIA
3
Boolean Derivatives
Useful properties of Boolean derivatives:
If F(x) is independent of xi
F ( X )G( X )
G( X )
F(X )
xi
xi
F ( X ) G( X )
G( X )
F(X )
xi
xi
Näide:
x1x4 ( x2 x3 x2 x3 )
F ( X ) x1 x4 G( X ) x2 x3 x2 x3
F ( X )G( X )
G( X )
x1 x4
x2
xi
These properties allow to simplify the Boolean differential equation
to be solved for generating test pattern for a fault at
xi
Technical University Tallinn,
ESTONIA
4
Boolean derivatives
F ( X )
0
xi
F ( X )
1
xi
-
if F(x) is independent of xi
-
if F(x) depends always on xi
F ( X )
F ( x1 ,...xi 0,...xn ) F ( x1 ,...xi 1,...xn )
xi
Examples:
F ( X ) x1 ( x2 x3 x2 x3 ) :
F ( X ) x1 x2 :
F ( X )
x1 x2 x1 x2 0
x3
F ( X )
x2 x2 1
x1
Technical University Tallinn,
ESTONIA
5
Boolean vector derivatives
If multiple faults take place independent of xi
F ( X )
F ( x1 ,...xi , x j ,...xn ) F ( x1 ,...xi , x j ,...xn )
( xi , x j )
Example:
x1
x2
y F ( x1, x2 , x3 , x4 ) x1x2 x3 x4
&
1
x3
x4
&
F ( X )
x1 x 4 x1 x4 x1 x4 ( x 2 x 3 x2 x3 )
( x2 , x3 )
Technical University Tallinn,
ESTONIA
6
Boolean vector derivatives
Calculation of the vector derivatives by Carnaugh maps:
y F ( x1, x2 , x3 , x4 ) x1x2 x3 x4
x2
x2
x2
1 1
x1
1 1
1 1 1
1 1
x3
x
1
1 1
1 1 1
x4
x4
x1 x2 x3 x4
x1 x2 x3 x4
x3
=
x1
1 1
1 1
1
1 1
1
1 1
x3
x4
F ( X )
x1 x 4 x1 x4 x1 x4 ( x 2 x3 x2 x3 ) 1
( x2 , x3 )
Technical University Tallinn,
ESTONIA
7
Boolean vector derivatives
Interpretation of three solutions:
F ( X )
x1 x 4 x1 x4 x1 x4 ( x 2 x3 x2 x3 ) 1
( x2 , x3 )
x1 x4 1
x1
x2
Fault
1
&
1
Two paths activated
x3
x4
y
&
1
x1 x4 1
Single path activated
Fault
x1
x2
1
&
1
x3
x4
y
&
0
Technical University Tallinn,
ESTONIA
8
Derivatives for complex functions
Boolean derivative for a complex function:
Fk ( Fj ( X ), X )
xi
Fk Fj
Fj xi
y y x1 x3
x4 x1 x3 x4
Example:
x4
x3
x1
y
x2
Additional condition:
x2
0
x3
Technical University Tallinn,
ESTONIA
9
Research in ATI
© Raimund Ubar
Topological Idea of Test Generation
Fault
activation
Path
activation
x1
x2
x3 = 0
Fault
Stuck-at-1
Correct
signal
xx1
0
0
1
x4 0
x5
x6 0
x7
y
0 1
11
1
1
x2
xx3
0
y
F (X)
1
x4
Error
x5
0
x6
x7
0
y x1 x2 ( x3 x4 x5 ) x6 x7
0
10
Research in ATI
© Raimund Ubar
Mapping Between Circuit and SSBDD
Each node in SSBDD represents a signal path:
x11
x6
x21 &
Signal path
x1
x2
x12
x31
x3
x4
x13
&
&
x7
x5
x22
x32
1
y
x11 1 x21
1
0
x12
x31
x4
x13
x22
x32
y
&
x8
0
Node x11 in SSBDD represents the path (x1, x11, x6, y ) in the circuit
The SAF-0(1) fault at the node x11 represents the SAF faults on the
lines x11, x6, y in the circuit fault collapsing
32 faults (16 lines) in the circuit 16 faults (8 nodes) in SSBDD
11
Test Generation with BD and BDD
BDD:
BD:
y x1x2 x3 ( x2 x4 x1 ( x4 ( x5 x2 x6 )) x1 x3
y
x1
x2
x3
x2
x4
x1
x4
x
y
( x1 x2 x1 x3 ) x3 ( x2 x4 ) x1 x4 ( x2 x6 ) 5
x5
x5
x5
( x1 x2 )(x1 x3 ) x3 ( x2 x4 ) x1 x4 ( x2 x6 )
x1 x4 x3 x2 ... 1
x2
Test pattern:
x1
x2
x3
x4
x5
x6
y
0
1
-
0
D
-
D
x1
1
x6
x2
0
Technical University Tallinn,
ESTONIA
12
Research in ATI
© Raimund Ubar
Fault Analysis with SSBDDs
Algorithm:
1. Determine the activated path to find the fault candidates
2. Analyze the detectability of the each candidate fault
(each node represents a subset of real faults)
x1
x2
x11
x21
0
1
x12
x31
x3 0
x 1
y
&
&
4
x13
&
x11 1 x21
1
0
0
0
0
0
1
y
x12
x31
x4
x13
x22
x32
&
x22
x32
0
13
Research in ATI
© Raimund Ubar
Test Generation with SSBDDs
Test generation for: x110
x1
x2
x3
x4
10
1
x13
1
x11
x21 &
x12
x31
0
Structural BDD:
&
y
0
0
x12
10
1
x31
x4
y
1
0
x13
&
x22
x32
Test pattern:
x21
10
10
&
x11
1
0
x1 x2 x3 x4 y
1
1
0
-
1 0
x22
x32
Functional
BDD:
1
y
x1
1
x2
1
x4
x3
10
x2
1
0
14
Research in ATI
© Raimund Ubar
Functional Synthesis of BDDs
Shannon’s Expansion Theorem: y F ( X ) xk F ( X ) xk 1 xk F ( X ) xk 0
y x1 ( x2 ( x3 x4 ) x2 ) x1x3 x4
Using the Theorem
for BDD synthesis:
x1 F ( X ) x 0
1
y
y
x1
x2 ( x3 x4 ) x2
x3 x4
x3
x4
x3 x4
1
xk
F(X ) x
0
x2
x3
1
x4
0
1
F(X ) x
k 0
k 1
Research in ATI
© Raimund Ubar
Functional Synthesis of BDDs
Shannon’s Expansion Theorem: y F ( X ) xk F ( X ) xk 1 xk F ( X ) xk 0
y x1 ( x2 ( x3 x4 ) x2 ) x1x3 x4
y
x1
x3
x2
1
y
x1
x3
x4
x2
x3
1
x4
0
x3
x4
0
1
Research in ATI
© Raimund Ubar
BDDs for Logic Gates
Elementary BDDs:
x1
x2
x3
y
&
AND
x1 1 x2
x3
x1
x2
x3
1
0
x1
x2
x3
0
Given circuit:
x1
x2
x21
1
y
1
x2
NOR
1
x1
y
x1
x2
x3
x3
a
&
x22
x3
OR
y
SSBDD synthesis:
SSBDDs for a given circuit are built
by superposition of BDDs for gates
1
b
17
Research in ATI
© Raimund Ubar
Synthesis of SSBDD for a Circuit
Superposition of BDDs:
Given circuit:
x1
x2
x21
1
&
x22
x3
y
a
a
b
y
b
y
a
x22
1
b
x22
x3
x3
Structurally
Synthesized
BDD:
b
Compare to
Superposition of Boolean functions:
a
y
y a & b ( x1 x21 )(x22 x3 )
a
x1
x22
x21
x3
x1
x21
18
© Raimund Ubar
Research in ATI
Logic Operation with BDDs
Generation of BDDs
for
y x1 x2 x3
19
Research in ATI
© Raimund Ubar
Boolean Operations with SSBDDs
x1
x2
x21 &
c
g
1
x52
x6
y
b
x51 &
x1
x22
x21
x3
x4
x52
x51
x6
e
&
x3
y
y=eg
1
x22
x4
x5
AND-operation:
a
&
d
OR-operation:
y=eg
y
x1
x22
x4
x52
x21
x3
x51
x6
20
Research in ATI
© Raimund Ubar
Properties of SSBDDs
Boolean function:
y
x1
x2
x3
x4
x5
y = x1x2 x3 (x4 x5x6)
#1
y
x1
x2
x3
x4
x6
#0
1-nodes of a 1-path represent
a term in the DNF: x3x5x6 = 1
x5
#1
x6
#0
0-nodes of a 0-path represent
a term in the CNF: x1x4x5 = 0
21
Research in ATI
© Raimund Ubar
Boolean Operations with SSBDDs
Boolean function:
y = x1x2 x3
y
x1
x2
x3
Inverted function (DeMorgan):
y = x1x2 x3 = ( x1 x2) x3
y
x3
x1
x2
Dual function:
Inverted dual function:
y*= (x1 x2) x3
x1
x3
y*
y * = x1x2 x3
x2
x1
y*
x2
x3
22
Research in ATI
© Raimund Ubar
Transformation Rules for SSBDDs
SSBDD
BOOLEAN ALGEBRA
Exchange of nodes:
y
y
x1
x2
Commutative law:
=
x2
x1
Node passing:
y
Idempotent law:
y
x1
x2
x2
y = x1 x2= x2 x1
=
x1
x1
y = x 1 x1 x2 =
= x 1 x2
x2
23
Research in ATI
© Raimund Ubar
Properties of SSBDDs
Exchange of nodes:
Boolean function:
y
y = x1x2 x3 (x4 x5x6)
x2
y
x1
x2
=
x2
x1
#1
y
x3
y
x1
x2
x1
x3
x4
#1
x4
x5
x6
x6
x5
#0
#0
24
Research in ATI
© Raimund Ubar
Properties of SSBDDs
Exchange of subgraphs:
Boolean function:
y
y = x1x2 x3 (x4 x5x6)
y
G1
=
G2
y
x1
x2
G1
#1
y
x3
G2
x3
x4
x1
x2
#1
x4
x5
x6
x5
x6
#0
#0
25
Research in ATI
© Raimund Ubar
Transformation Rules for SSBDDs
SSBDD
BOOLEAN ALGEBRA
Node passing:
y
Absorption law:
y
x1
x1
x2
y = x1 x1x2 = x1
x1
=
x1
x2
Distributive law:
y
x1
y
x2
x1
x2
x1
x3
=
x1
x3
y = x1x2 x1x3=
= x1(x2 x3)
26
Research in ATI
© Raimund Ubar
Transformation of SSBDDs to BDDs
y
SSBDD:
y
x11
x21
x12
x31
x13
x22
x1
x2
x4
BDD:
x2
x3
y
x1
x2
x4
x12
x31
x32
x13
x22
y
x1
x2
x4
x12
x3
x4
x32
x13
x22
x32
y
x3
x1
Optimized
BDD:
x2
x4
x3
x2
27
Research in ATI
© Raimund Ubar
Transformation Rules for SSBDDs
SSBDD
BOOLEAN ALGEBRA
Superposition:
y
x1
y
x2
x3
z
Assotiative law:
x3
x2
z
z
y
x1
=
=
x3
z
x1
y = x1 (x2 x3) =
= (x1 x2) x3
x2
28
Research in ATI
© Raimund Ubar
Properties of SSBDDs
Graph related properties:
SSBDD is
planar
asyclic
traceable (Hamiltonian path)
for every internal node there
exists a 1-path and 0-path
homogenous
y
x11
x21 1
1
0
0
x12
x31
x4
x13
0
x22
1
1
x32
1
Research in ATI
© Raimund Ubar
BDDs for Flip-Flops
Elementary BDDs
S
J
C
D Flip-Flop
q
D
C
c
D
JK Flip-Flop
q
K
R
q’
S
R
RS Flip-Flop
S
C
R
q
c
S
q’
R
q c( S q' R) cq'
SR 0
c
q’
q’
J
K
R
q’
U
U - unknown value
30
Research in ATI
© Raimund Ubar
Mapping Between Circuit and SSBDD
From circuit to set of SSBDDs
Fan-out stems
FFR
C
D
FFR
Y1
SSBDD2
SSBDD4
FFR
A
B
C
FFR
SSBDD3
FFR
SSBDD1
Y2
SSBDD5
E
Y
a
b
a
c
31
Research in ATI
© Raimund Ubar
Advantages of SSBDDs
Linear complexity: a circuit is represented as a system
of SSBDDs, where each fanout-free region (FFR) is
representred by a separate SSBDD
One-to-one correspondence
between the nodes in SSBDDs
and signal paths in the circuit
This allows easily to extend the
logic simulation with SSBDDs to
simulation of faults on signal
paths
32
Research in ATI
© Raimund Ubar
Shared SSBDDs - S3BDD
Extension of superposition
procedure beyond the fanout nodes of the circuit
Merging several functions
in the same graphs by
introducing multiple roots
Superpositioning of FFRs
Node of SSBDD signal path up to fan-out stem
Input of SSBDD circuit down to primary inputs
33
Research in ATI
© Raimund Ubar
S3BDDs and Fault Collapsing
19
7
3
4
&
11
1
2
1
&
&
14
12
10
6
17
15
13
8
1
&
1
&
11
20
17
7
18
15
12
10
16
1
1
5
14
1
&
1
16
9
19
17
14
20 11
15
12
3
1
Fault collapsing:
1
2
21
&
5
4
21
18
13
18
9
16
13
8
6
10
From 84 faults to 36 faults
For SSBDD: 50 faults
34
Research in ATI
© Raimund Ubar
Shared SSBDDs
7
Each node represents different paths
(path segments) in the circuit
3
4
&
1
11
&
14
1
SSSBDD for 19
Node
Path
14
140-19 (3)
11
110-19 (4)
7
7-19 (4)
15
150-170-19 (3)
12
120-141-170-19 (4)
3
3-111-141-170-19 (5)
4
4-111-141-170-19 (5)
5
1
2
1
&
10
14
11
15
&
1
16
9
19
1
20
1
21
17
15
13
8
7
17
14
11
&
1
&
6
19
12
1
18
&
12
3
4
35
Research in ATI
© Raimund Ubar
Synthesis of S3BDD for a Circuit
Superposition of BDDs:
Given circuit C17
Y1
Y1
Y1
G1
3
G1
X1
11
3
3
Each node in the SSMIBDD
represents a signal path in the
circuit
Testing a node in SSMIBDD
means testing a signal path in
the circuit
Y1
X1
X3
3
X2
21
Y1
X1
X3
3
X2
21
21
X2
2
3
11
X1
12
X4
11
X1
Y1
X1
X3
3
X2
X3
2
1
X4
Research in ATI
© Raimund Ubar
Synthesis of S3BDD for a Circuit
Given circuit C17
Superposition of BDDs:
Y2
3
Y2
G4
Two-output circuit
is represented
by a single SSBDD
with shared
subgraphs
Y1
X1
X3
3
X2
X3
G4
Y2
2
3
Y1
X1
X3
3
X2
X4
3
X4
Y2
X5
2
X5
2
X5
3
2
X3
X5
37
Research in ATI
© Raimund Ubar
3
Sequentional S3BDDs
T1
10
2
7
15
1
9
1
10 nodes,
20 stuck-at faults,
2,5 times less
12
&
1
8
13
17
&
18
1
&
16
&
T1
15
1
T1
9
8 13
25 nodes,
50 stuck-at faults
8
&
11
9
&
17 1
T3
T2
18
5
14
1
&
6
16
14
4
1
19
8
T3
T2
9
4
14
T3
26
1
9
T2
T1
T1
10
7
2
3
26
T3
19
2
1
23
24
3
T1
1
21
20
1
4
T2
5
14
6
1
22
11
25
20
12
22 1
21 23
24
&
T3
25
14
T2
26
T3
1
8
T2
GAIN:
2,5 times
in logic simulation,
2,5 2 = 6,25 times
in fault simulation
38
Research in ATI
© Raimund Ubar
Structured Interpretation of S3BDDs
3
10
2
T1
1
1
7
G
GT1
9
Nodes
3
2
T1
15
T1
T1
T1
3
9
2
T1
S3BDD represents two
subcircuits
Signal paths
3 – 15 – T1
2 – 9 – 10 – 15 – T1
T1 – 7 – 9 – 10 – 15 – T1
L
3
5
6
Each node in the S3BDD represents a
signal path in the circuit
39
Research in ATI
© Raimund Ubar
Structured Interpretation of S3BDDs
8
11
1
8 13
&
9
&
17 1
18
5
14
1
&
6
T3
T2
16
14
4
G
GT2
G26
1
20
12
22 1 25 T2
21 23
24
&
T3
T2
26
T3
19
Nodes
8
T2
9
14
4
T3
1
Signal paths
8 – 12 – 25 – T2
T2 – 5 – 21 – 23 – 26
9 – 11 – 18 – 20 – 21 – 23 – 26
14 – 17 – 18 – 20 – 21 – 23 – 26
4 – 19 – 20 – 21 – 23 – 26
T3 – 6 – 14 – 16 – 19 – 20 – 21 – 23 – 26
1 – 8 – 13 – 14 – 16 – 19 – 20 – 21 – 23 – 26
L
4
5
7
7
6
9
10
40
Research in ATI
© Raimund Ubar
BDDs and Complexity
Optimization (by ordering of nodes): BDDs for a 2-level AND-OR circuit
BDD optimization:
We start synthesis:
• from the most
repeated variable
2n nodes
22n - 2 nodes
Research in ATI
© Raimund Ubar
BDDs and Complexity
BDDs for an 8-bit data selector
Research in ATI
© Raimund Ubar
BDDs and Complexity
Elementary BDDs
S
J
C
D Flip-Flop
q
D
C
c
D
JK Flip-Flop
q
K
R
q’
R
RS Flip-Flop
S
C
R
q
c
S
q’
R
c
q’
q’
J
K
R
q’
U
q c( S q' R) cq'
SR 0
S
U - unknown value
BDD optimization:
We start synthesis:
• from the most
important variable, or
• from the most
repeated variable
43