Transcript No Slide Title

Constraint-Based Embedded Program Composition
NEW IDEAS
System Design Space/
Embedded Object
Specification
System SW/HW Description
AO
Constraint
Specs
Waveform
Descr. #1
Constraint
Weaver
Constraint
Weaver
System
Composition
Waveform
Descr. #N
System
Composition
Customized/Optimized
Embedded
System
SW-Based
Radio
• AO Merging a Model-Based & Language
Approaches
• Model-Based System Design Space Spec
• Textual Constraints/Requirements Spec.
• System-Level Constraint Expression Language
• AO-Based Strategy Language for Constraint
Distribution and Application
• Weaver Infrastructure for Automated Constraint
Application
• Meta-Weaver for Specification of Weavers
• Automated Application of RT Constraints
IMPACT
SCHEDULE
• Rapid Construction of Efficient Embedded Systems.
• Multiple System Variants for Little Cost.
. 3/01 Spec. & Strategy Lang. V1
• Rapid, Low Cost System Evolution.
. 6/01 Constraint Weaver & ATR Demo
• Traceabilty from Requirements to Implementation
. 3/02 Spec. & Strategy Lang. V2
• Ability to Customize Tools for Specific Domains
. 9/02 Resource Constr. Weaver/Demo
• New Design Methodology: AO + Model-Based
. 3/03 Complete Spec/Strat Lang
. 11/03 Meta-Weaver Descr.
.
9/04 SW Radio Demo
Institute for Software Integrated Systems
Vanderbilt University
Constraint-Based Embedded
Program Composition
Institute for Software Integrated Systems
Vanderbilt University
PI: Ted Bapty
Jeff Gray, Sandeep Neema
Project Goals
• Investigate the Interactions between MBS+AO
• Extend Existing Model-Based Embedded System
Design System
– Language-based Constraints,
– Strategy Language for Constraint Distribution
• Customize the tools for Communications
• Demonstrate on Software-Based Radio
Application
Adaptive Computing Systems
Model-Integrated Design Environment
Multi-Aspect
Modeling
Environment
Graphical
Model
Builder
System
Generation
MODELS
Behavioral Models
Algorithm
Models
Resource
Models
Model
Analysis
Tools
SW HW
SW HW
ATR
Simulation
Environment
Reconfigurable
Runtime Environment
Model-Integrated Design
Environment (MIDE)
• Design Capture for HW/SW Codesign: Multiple Aspects
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Software/Algorithm Data Flow with Multiple Design Alternatives
Hardware Resources: Heterogeneous (DSP,RISC,FPGA)
Dynamic System Behavior: Multi-modal systems
Constraint Specification Language: Link SW/HW/Behavior
Result: Comprehensive, Flexible HW/SW System Model
• Analysis of Models (Design)
– Design-Space Exploration:
• Optimize design, select best configurations from alternative designs
• Highly scalable using OBDD
– Numerical/Algorithmic Simulation with Matlab
– Multiple-Resolution Performance Simulation with Discrete Event
Simulator
Model-Integrated Design
Environment (MIDE)
• HW/SW System Synthesis
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Generate Real-Time Schedules
Generate VHDL for FPGA or ASIC
Generate Interconnection Topology/Communication Maps
Generate Reconfiguration Manager Configuration
Result: Functional HW/SW System w/ Dynamic Reconfiguration
Capabilities. Compatible with Industry-standard VHDL Compilers
• Runtime Support
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–
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Microkernel for Heterogeneous Distributed DSP’s
Virtual Hardware Microkernel for FPGA/ASIC
Dynamic System Reconfiguration Controller
Real-Time, reconfiguration support.
Result: Portable, heterogeneous uniform execution environment
Multiple-View Graphical Modeling/
Flexible Design Space
Behavioral
Structural
Resource
Modeling Paradigm
Structural/Algorithmic Description
Model/Object Hierarchy
Example Model
Primitive
Primitive
Compound
Primitive
Compound
Primitive
Compound
Primitive
Template
Compound
Template
Compound
Software
Compound
Primitive
Hardware
Primitive
Compound
Primitive
Primitive
Defining A Design Space
Templates for Algorithm Alternatives
Long Range
Track
Algorithm
Alternatives
Spatial Domain
Sensor
Spectral Domain
Preprocess
Filter
Preprocess
Image DB
XCorr
Img Spec DB
Error Comp
2D FFT
Mult
Error Comp
Guidance
Loss of Track
Modeling Paradigm
Resource Models
Network
Object
Hierarchy
Processor
Core
Ports
FPGA
Core
Example
Model
ASIC
Ports
Ports
Network
Processor
Processor
ASIC
Processor
FPGA
FPGA
Modeling Paradigm
Behavioral Description: Hierarchical State Machine
Transition
Rules
Mode A
Mode B
Transition
Rules
Transition
Rules
Transition
Rules
Mode C
Attributes
Algorithms
Performance Specs
Constraints (Power/Size/User Defined)
Constraint Modeling
S1
S2
/e1[S21]/
hierarchical
parallel
FSM
/../
(mode=S2 implies (Proc.Powr<10))
Power
Constraints
Behavior and
Compatibility
Constraints
(mode=(S1 or S2))implies(P1=P1i))
P1
hierarchical
interconnect
alternatives
S3
Behavior Model
/../
Resource
Constraints
P2
Pr1
(mode!=S3)implies
(Pr2.assignees =(P1i or P2j))and(Pr2=Pr2j)
Pr2
P3
C1
(D1.time - D2.time) < 2
Processing Structure Models
Pr3
Timing
Constraints
Resource Models
Design Space Exploration
Resource
Model
Binary
Encoding
BDD
Representation
Behavior Mod.
(Hier. Par. FSM)
Binary
Encoding
BDD
Representation
Structural Mod.
(Hier. Altern.)
Binary
Encoding
BDD
Representation
Constraints
(OCL)
Binary
Encoding
BDD
Representation
Full
Symbolic
Design
Space
Pruned
Design
Space
OBDD
Analysis
System Synthesis
HOST
P1
PC
ASIC
C40 DSP
XC4010 FPGA
BIDIR
IFC
STREAMS
IFC - BIDIR
P1
P2
P3
Kernel
Multiple Data
Streams
Kernel
P1
P2
I/O
Interfaces
ASIC IFC
P1
IN IFC
OUT IFC
OUT IFC
IN IFC
STREAMS
IFC OUT
IN IFC
STREAMS
IFC IN
OUT IFC
C40 DSP
Real-Time Schedules,
Communication Maps
COMM
Interfaces
P2
P1
DATA
I/O
P2
P3
I/O
Altera FPGA Interfaces
VHDL for
FPGA Configs
Difficulties in Managing
Graphically Specified
Constraints
4
Multiple Levels
of Hierarchy
A
Replicated
Structures
3
B
1
c
2
d
F
e
3’
B
1’
Context
Sensitive
Change
Maintenance???
c
2’
d
B
e
1’’
c
2’’
d
e
4
Constraints Are Critical!!
• Define functional properties of system
• Ensure proper component interaction
• Designer’s leverage to guide synthesis
• Bad Constraint Management =
Inflexible, unwieldy development.
Develop Constraint Language
Aspect-Oriented
Constraint Language
• Develop Language for Specifying Constraints
– Operational
• Mode-dependent behavior
– Performance
• Timing
• Cost: Power/Parts $/Volume/Weight
– Composibility: (Part A ~ Part B, Part C !~ Part D)
– Resource: Process X requires Part D
– Relationships to Modeling Aspects
Constraint Application
Strategy Language
• Specify how to apply constraints across object
hierarchy.
• Determines how constraints are
divided/responsibility shared among
components.
• Flexible to permit different goals
– Latency optimization
– Throughput optimization
– ….
Propagation/Distribution Strategy
Constrained Object Hierarchy
C
Object Hierarchy
Weaving/
Constraint
distribution
C
C
C C C
C C C
C C C C
C C C C
Constraint
Satisfaction/
Component
Selection
(OBDD)
System Constraints
Pruned Object Hierarchy
void main(void)
{
Task t1, t2, t3;
Mutex m1, m2;
Semaphore s1;
t1 = CreateTask (.
t2 = CreateTask (.
t3 = CreateTask (.
m1 = CreateMut .
m2 = CreateMu .
System Synthesis
Constrained Object Graph
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
Constraint Weaver
AO Strategies and Constraints
Object Graph
Strategized Object Graph
Constraint Weaver
AO Strategies
Object Graph
Constrained Object Graph
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
Constraint Weaver
AO Constraints
Strategized Object Graph
(2) Constraint application
(1) Constraint aspect
(from weaver, or parent strategy)
(3) Propagated Constraint
(to sub-objects)
1. Core.def
2. Aspect..def
Syntax Tree
Generator
5. interpreter.def
Weaver
Interpreter
Generator
Syntax Tree
Definition
(aspect)
Syntax Tree
Definition
(core)
Interpreter
Parser(core)
Parser(aspect)
PCCTS
3. Core.parse
4. Aspect..parse
Weaver
Weaved Program
Syntax Tree
Definition
(core)
Interpreter
Syntax Tree
(core)
Parser(core)
Core Program
Syntax Tree
Definition
(aspect)
Syntax Tree
(aspect)
Parser(aspect)
Aspect Program
Demonstration Plans
Waveform
#1
Strategy
SW “RF”
Components
Waveform
#2
Weaver
Unconstrained
SW Radio
Real-Time Design
Synthesis
Runtime Infrastructure