Power-Aware FPGA Logic Synthesis Using Binary Decision

Transcript Power-Aware FPGA Logic Synthesis Using Binary Decision

Han Liu Supervisor: Seok-Bum Ko Electrical & Computer Engineering Department 2010-Feb-2

Outline

 Information of literature  Background  FPGA Design Flow  Logic Synthesis  Binary Decision Diagram (BDD)  Power-Aware Logic Synthesis  Comparison  Conclusion 2

Information of literature

Power-Aware FPGA Logic Synthesis Using Binary Decision Diagrams Kevin Oo Tinmaung, David Howland, and Russell Tessier

February 2007 FPGA '07: Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays

Background

 Performance-oriented Design Flow  Low Power  High Speed  Methods to achieve these goals  Materials (Si,Ge have different threshold)  Devices (xMOS, FET, Bipolar)  Place and Route (longer route means larger delay)  Synthesis Algorithm  System Design (SW/HW partition) 4

FPGA Design Flow

HDL Behavioral synthesis RTL RTL synthesis Boolean Logic synthesis Circuit Placement Routing Final Chip 5

Logic Synthesis

Boolean Function Optimization Mapping Circuit base on LUT Timing-Aware Area-Aware Power-Aware 6

Binary Decision Diagram 1/2

F=ab+cd a b Variables could be reordered.

b a d c c d 1 0 1 0 7

Binary Decision Diagram 2/2

F=ab+cd a G=ab a H=cd c F=G+H G b b d H c d 1 0 1 0 1 0 0 8

Power-Aware Logic Synthesis 1/2 (1 ) (2) Transition Density (D): the average number of transitions per unit time.

Static Probability (P): the probability of the signal being high for a certain time period.

Lower switching activity means lower dynamic power and lower short circuit power 9

Power-Aware Logic Synthesis 2/2 D (G) = P (G/a) *D (a) + P (G/b) *D (b) = P (b ⊕ 0) * D (a) = P (b) *D (a) + P + P (a) (a *D ⊕ 0) (b) * D (b) = 0.5*0.5 + 0.5*0.6

= 0.55

P (G) = P (a=1,b=1) = P (a) *P (b) = 0.5*0.5

= 0.25

Comparison

SIS Flow (Berkeley)

LUTs Max Delay (nS) Energy@ 50MHz (nJ) Average Power Consumption on benchmarks 1858 8.38

1.39

Power-Aware BDD Flow

LUTs Max Delay (nS) Energy@ 50MHz (nJ) 1629 9.33

(111%) 1.20 (87%) 11

Conclusion

 Power-aware BDD based Synthesis Algorithm could reduce power consumption.

 Power-aware BDD based Synthesis Algorithm may cause increase timing delay.

 Proposed method could be useful in low power design.