Transcript Document

On the Relation between SAT and BDDs
for Equivalence Checking
Sherief Reda
Computer Science &
Engineering Dept.
University of California,
San Diego
Rolf Drechsler
Institute of Computer Science
University of Bremen
Alex Orailoglu
Computer Science &
Engineering Dept.
University of California,
San Diego
Outline
Introduction
BDDs
The Davis-Putnam (DP) Procedure
Equivalence Checking
BDD-DP Relation
Characteristics of CNF Formulas of Logic Circuits
Relation between BDD and the DP
Dynamic Variable Ordering for the DP Procedure
Open questions
Experimental Results
Conclusions
Introduction
BDDs have been traditionally used in logic synthesis and
verification
New Boolean satisfiability (SAT) solvers have shown
recent promise as efficient equivalence checkers
It is essential to understand the relation between BDDs
and SAT procedures and show how the techniques of one
domain can be applied to the other
Binary Decision Diagrams
x1
0
0
x3
1
x2
x2
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x4
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0
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ROBDDs are produced through the repeated application of
 Redundant test elimination
 Equivalent sub-graph sharing
The Davis-Putnam Procedure
a
d
z
b
c
 = (a + d)  (b + d)  (a + b + d)  (c + z) 
(d + z)  (d + c + z).
0
a
b
0
d
By unit clause propagation
z
By unit clause propagation
1
Consistent assignment achieved
0
0
assign(sat_formula , literal v)
begin
a1. v = true;
a2. simplify ;
a3. apply unit clause propagation;
a4. if  has an empty clause
then return false
else return true;
end
DP(sat_formula )
begin
d1. choose literal v to split on;
d2. if v = NULL then return true;
d3. if assign(, v) then
d4. if DP() then return true;
d5. undo v assignment;
d6. if assign(, v) then
d7. if DP() then return true;
d8. return false;
end
The Davis-Putnam Procedure
a
d
z
b
c
 = (a + d)  (b + d)  (a + b + d)  (c + z) 
(d + z)  (d + c + z).
0
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1
b
1
0
By unit clause propagation
d
d
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0
z
c
1
0
z
1
1
1
By unit clause propagation
assign(sat_formula , literal v)
begin
a1. v = true;
a2. simplify ;
a3. apply unit clause propagation;
a4. if  has an empty clause
then return false
else return true;
end
DP(sat_formula )
begin
d1. choose literal v to split on;
d2. if v = NULL then return true;
d3. if assign(, v) then
d4. if DP() then return true;
d5. undo v assignment;
d6. if assign(, v) then
d7. if DP() then return true;
d8. return false;
end
Equivalence Checking
Core equivalence checking techniques
 Using BDDs
Build the BDD of each circuit under verification and check that the
BDDs are isomorphic
 Using SAT
Check that the stuck-at-0 SAT formula of the miter circuit is unsatisfiable
Circuit I
Primary
Input
Circuit II
Miter
output
Equivalence Checking
 Equivalence checking can be viewed as
A search in the decision trees of the two circuits for a path that
leads to the terminal 1(0) in one but leads to the 0(1) terminal in
the other.
0
1
Decision tree
of Circuit I
Decision tree
of Circuit II
Minimization of the number of paths to be compared 
Minimization of equivalence checking time
Characteristics of CNF Formulas of Logic Circuits
Let  be a CNF formula generated from a logic circuit
Let V() be the set of variables that  depends on
It is possible to find a set of variables P()  V() such
that  can be satisfied by only splitting on the variables of
P() in the DP procedure.
P() is the set of primary inputs
Reducing the number of decision variables introduces an
overall reduction in the decision tree size
Characteristics of CNF Formulas of Logic Circuits
Let S denote the set of primary inputs currently assigned
logic values under the assignment As
If As is applied to , the resultant is the logic function fAs
If v  P() but v  S then v is said to be redundant under
As if  fAs /v = 0
A CNF formula  is satisfied under a truth assignment
As of a set S  P() if v(P()-S):  fAs /v = 0
If the primary output variable  is assigned a value under
the current assignment then there is no point in further
assignments
Characteristics of CNF Formulas of Logic Circuits
1
a
d
z
b
c
 = (a + d)  (b + d)  (a + b + d)  (c + z)  (d + z)  (d + c + z)
P() = {a, b, c}
=z
If S = {a} and Bs={a  1}
then  = (d)  (b + d)  (c + z)  (d + z)  (d + c + z)
Characteristics of CNF Formulas of Logic Circuits
1
a
d
z
b
c
 = (a + d)  (b + d)  (a + b + d)  (c + z)  (d + z)  (d + c + z)
P() = {a, b, c}
=z
If S = {a} and Bs={a  1}
then  = (d)  (b + d)  (c + z)  (d + z)  (d + c + z)
Under Bs fBs/b = 0  b is redundant
Characteristics of CNF Formulas of Logic Circuits
a
d
z
b
0
cc
0
 = (a + d)  (b + d)  (a + b + d)  (c + z)  (d + z)  (d + c + z)
P() = {a, b, c}
=z
If S = {c} and As={c  0}
then z  0 and  = (a + d)  (b + d)  (a + b + d).
Characteristics of CNF Formulas of Logic Circuits
a
d
z
b
0
cc
0
 = (a + d)  (b + d)  (a + b + d)  (c + z)  (d + z)  (d + c + z)
P() = {a, b, c}
=z
If S = {c} and As={c  0}
then z  0 and  = (a + d)  (b + d)  (a + b + d).
Under As both fAs/a and fAs/b = 0  a & b are redundant
Characteristics of CNF Formulas of Logic Circuits
Observation 1: DP decision space is reduced to be that of
the primary inputs
Observation 2: Redundant variables are not considered for
decision in the DP procedure
Observation 1 reduces the decision space to be like that of
a BDD and observation 2 parallels the removal of
redundant test in BDDs.
Relation between BDD and DP
Given a BDD  and a CNF formula  for a logic circuit C, then under a
variable ordering  and a truth assignment A on a certain path of  to
the terminal,  is satisfiable using the same variable ordering and truth
assignment.
The equivalence checking problem between two circuits can be viewed as a
search in the decision trees of the two circuits for a path that leads to the
terminal 1(0) in one but leads to the 0(1) terminal in the other.
0
1
Decision tree
of Circuit I
Decision tree
of Circuit II
Relation between BDD and DP
BDD-DP Theorem For BDD  with P paths and a CNF formula  for a logic
circuit C then if DP variable ordering strategy captures the same ordering for
every path of , then DP proves the equivalence of C against an equivalent
version in P-1 backtracks.
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Decision space of circuit I
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Decision space circuit II
9 paths in the
BDD implies 8
backtracks in the
CNF formula
Dynamic Variable Ordering for the DP Procedure
DP dynamic variable ordering strategy should
 The variable ordering strategy should differ for every path of the
decision tree
 No splitting on redundant variables
 Minimum number of splittings to reach the terminals
Var_Choose()
Assign a weight of 1.0 to the primary output
For each circuit level from output to input:
 Divide the weight of the unbounded gate output among its inputs
 Accumulate the weight of the fan-out branches into the fan-out stem
Return the PI with the largest weight
Dynamic Variable Ordering for the DP Procedure
The proposed dynamic variable ordering represent the
structural impact of every primary input of the circuit
 Assigns a weight of zero to redundant variables
 Tries to minimize the number of assignments to the
terminals by splitting on the primary input with the largest
weight
 The weights reflect structural properties of the circuit
and should be considered as a heuristic to the optimal case
Dynamic Variable Ordering for the DP Procedure
1/12 x1
1/12 x2
i
1/4
1/4
1/2
x3
1/3
x4
j
1/2
f
1/4
h
1/2
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Dynamic Variable Ordering for the DP Procedure
1/3
1/3
x1
x2
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1
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x3
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1/3 x4
x3
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x1
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x4 1
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Dynamic Variable Ordering for the DP Procedure
x1
x2
i
j
f
x3
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In this case, the proposed
dynamic variable ordering
strategy faithfully captured
the variable ordering of the
minimum size BDD
1
h
x4
x3
1
x1
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x2
1
x4 1
0 1
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For this example, the
variable ordering that
minimizes the number of
BDD nodes (4) also
minimizes the number of
paths (6)
DP procedure proved the
equivalence in an optimal
number of 5 backtracks
BDD number of nodes and number of paths
Questions that need answering
I. Is there a relation between the number of nodes and the
number of paths in a BDD?
II. Does the minimum size BDD have the minimum
number of paths?
After numerous experiments, we concluded that the
minimum size BDD does not necessarily have the
minimum number of paths
The first question remains an open problem
Experimental Results
1
TEGUS
Proposed
0.5
Optimal
19
16
13
10
7
4
0
1
Millions
Number of Backtracks Comparison
Function
The optimal is determined by picking the minimal path BDD resulting
from sifting
Average 90% reduction in the backtracks for the 21 functions of the
ISCAS’89 benchmark circuits
Experimental Results
800
700
600
500
400
300
200
100
0
TEGUS
Proposed
19
16
13
10
7
4
Experiments
carried out using a
Pentime 233Mhz
with 64 MB RAM
1
Time (sec)
Time Comparison
Circuit
Average 70% time reduction for the hard-SAT functions (13) of the
ISCAS’ 89 benchmark circuits
The multiplier c6288 number of paths does not significantly
change for different variable orderings
Conclusions
The relation between the search tree of the DP procedure and the
BDD of the corresponding circuit was studied
We established the relation between the number of paths in a BDD
and the corresponding number of backtracks in the DP procedure,
enabling the calculation of optimal lower bounds
This relation enabled the inclusion of a modified BDD variable
ordering heuristic in the splitting choice of the DP procedure
Experimental results confirm the reported relation and demonstrate a
dramatic decrease in the number of backtracks and time need to solve
equivalence checking