Transcript HAsim: Hardware Asim

Hasim
Joel Emer†‡
Michael Adler†, Artur Klauser†,
Angshuman Parashar†, Michael Pellauer‡,
Murali Vijayaraghavan‡
†VSSAD
Intel
‡CSAIL
MIT
Overview
•
Goal
– Produce compelling evidence for architecture ideas
• Requirements
– Cycle accurate simulation
– Representative simulation length
– Software development (often)
• Current approach
– Mostly software simulation (10 KHz to 1 KHz)
• New approach
– Build a performance model in an FPGA
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FPGA-based approaches
• Prototyping
– Build a logically isomorphic representation of the design
• Modeling
– Build a performance simulation in gates
• Hybrids
– Build something that is partially a prototype and partially a model
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Recreate Asim in hardware
• Modularity
• Inter-module communication
• Functional/Timing Partitioning
• Modeling Utilities
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Why modularity?
• Speed of model development
• Shared components between products
• Reuse across generations
• Encourages isomorphism to design
• Improved fidelity
• Facilitates speed/fidelity trade-offs
• Architectural experimentation
• Factorial development and evaluations
• Sharing
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ASIM Module Hierarchy
S
F
B
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D
C
M
N
R
X
C
W
ASIM Module Selection
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B
F
B
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D
C
M
N
R
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B
B
Module Selection
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B
F
B
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D
C
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N
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C
B
W
B
B
Module Replacement
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B
F
B
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D
C
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N
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X
C
B
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B
B
(H)ASIM Module Hierarchy
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Communication
C
F
N
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D
R
X
C
N
W
Named connections
A-out
S
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A-in
D
Model and FPGA Cycles
Port
Port
Module B
Module A
Port
A
1.1
B
1.1
1
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1.3
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4
2.1
2.2
2.1
2.2
2.3
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Port
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A
1.1
1.2
1.3
2.1
B
1.1
2.1
2.2
2.3
1
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2.2
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Functional/Timing Decomposition
• ISA semantics
• Platform semantics
• Micro-architecture
Fetch(PC)
…
Timing
Partition
Functional
Partition
Instruction
• Simplifies timing model
• Amortize functional model design effort over many models
• Can be pipelined for performance
• Can be FPGA-friendly design
• Can be split across hardware and software
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Execute@execute phases
Fetch instruction
Speculatively execute instruction
Read memory*
Speculatively write memory* (locally visible)
Commit or Abort instruction
Write memory* (globally visible)
*
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Optional depending on instruction type
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Execution in phases
F
D
X
F
D
F
X
D
X
F
D
F
C
R
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W
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D
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Assertion: All data dependencies can be represented in these phases
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W
HASim: Partitioning Overview
Timing Partition
Token
Gen
Fet
Memory
State
Functional
Partition
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Dec
Exe
Mem
Register State
RegFile
LCom
GCom
Common Infrastructure
• Modules
• Inter-module communication
• Statistics gathering
• Event logging
• Debug Tracing
• Simulation control
•…
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Bluespec (Asim-style) module
module [HAsim_module] mkCache#() (Empty);
Port#(Addr) req_port <- mkSendPort(‘a2cache’);
Port#(Bool) resp_port <- mkRecvPort(‘cache2a’);
TagArray tagarray <- mkTagArray();
rule cycle(True);
Maybe#(Addr) mx = req_port.get();
if (isValid(mx))
resp_port.put(tagarray.lookup(validValue(mx)));
endrule
endmodule
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Bluespec (Asim-style) submodule
module mkTagArray(TagArray);
RegFile#(Bit#(12),Bit#(4)) tagArray<- mkRegFileFull(...);
method Bool lookup(Bit#(16) a);
return (tagArray.sub(getIndex(a)) == getTag(a));
endmethod
function Bit#(4) getTag(Address x);
return x[15:12];
endfunction
function Bit#(12) getIndex(Address x);
return x[11:0];
endfunction
endmodule
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Support functions - stats
Module
Stat Counter
Module
Stat Counter
module mkCache#(...) (Empty);
...
cache_hits <- mkStat(...);
...
hit=tagarray.lookup(...);
if (hit)
cache_hits.increment();
endif
...
endmodule
Module
Stat Counter
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Stat Dumper
2Dreams
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Support functions - events
Module
Event Reg
Module
Event Reg
Module
Event Reg
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module mkCache#(...) (Empty);
...
cache_event <- mkEvent(...);
...
hit=tagarray.lookup(...);
cache_event.report(hit);
...
endmodule
Event Dumper
Support functions – global controller
Module
Controller
Module
Controller
Module
Controller
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module mkCache#(...) (Empty);
...
ctrl <- mkCntrlr(...);
...
rule (ctrl.run())
...
endrule
endmodule
Global
Controller
FPGA-based prototype
Prototyping Catch-22…
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Module Instantiation
U
M
FFF
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D
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D
CCC
M
N
RRR
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X
CCC
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W
W
Factorial Coding/Experiments
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C
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RC
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C
SM
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SM
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SC
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C
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SC
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S
M
RC
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RM
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HAsim: Current status - models
• Simple RISC functional model operating
–
–
–
Simple RISC ISA
Pipelined multi-phase instruction execution
Supports speculative OOO design
• Physical Reg File and ROB
• Small physically addressed memory
• Fast speculative rewinds
• Instruction-per-cycle (APE) model
– Runs simple benchmarks on FPGA
• Five stage pipeline
– Supports branch mis-speculation
– Runs simple benchmarks (in software simulation)
•
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X86 functional model architecture under development
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Connections Implement Ports
foo
baz baz
foo bar bar
bar bar
baz
baz
PM
(Module Tree w. Connections)
foo
PM
(Hardware Modules w. Wrappers)
Implemented via connections.
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foo
Timing Model Resources (Fast)
OOO, branch prediction, three functional units, 32KB 2-way set
associative ICache and DCache, iTLB, dTLB
2142 slices (15% of a 2VP30)
• 21 block RAMs (15% of a 2VP30)
Configurable cache model
• 32KB 4-way set associative cache with 16B cache-lines
– 165 slices (1% of a 2VP30)
– 17 block RAMs (12% of a 2VP30)
•
2MB 4-way set-associative cache with 64B cache-lines
– 140 slices (1% of a 2VP30)
– 40 block RAMs (29% of a 2VP30)
Current FPGAs (4VFX140)
• 142,128 slices
• 552 block RAMs
• 2 PowerPCs
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