Transcript Chapter 12

Chapter 12
Field Programmable Gate Array Testing
EE141
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1
Ch. 12 - FPGA Testing - P. 1
What is this chapter about?

Field Programmable Gate Arrays (FPGAs)
 Have become a dominant digital implementation
media
 Reconfigurable to implement any digital logic
function

Focus on
 Testing challenges due to programmability and
complexity
 Overview of testing approaches
 Test and diagnosis of various resources

New frontiers in FPGA testing
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Ch. 12 - FPGA Testing - P. 2
FPGA Testing

Overview of FPGAs
 Architecture, Configuration, & Testing Problem
Testing Approaches
 BIST of Programmable Resources

 Logic Resources
– Logic Blocks, I/O Cells, & Specialized Cores
– Diagnosis
 Routing Resources
Embedded Processor Based Testing
 Concluding Remarks

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Ch. 12 - FPGA Testing - P. 3
Field Programmable Gate Arrays
Configuration
Memory
 Programmable
Logic Blocks
(PLBs)
 Programmable
Input/Output Cells
 Programmable
Interconnect

Typical Complexity = 5 million – 1 billion transistors
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Ch. 12 - FPGA Testing - P. 4
Basic FPGA Operation


Writing configuration
memory (configuration) 
defines system function
 Input/Output Cells
 Logic in PLBs
 Connections between
PLBs & I/O cells
Changing configuration
memory data
(reconfiguration) 
changes system function
 Can change at anytime
 Even while system
function is in operation
– Dynamic partial
reconfiguration
EE141
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11100110100010001001010100010111
0001010010101010100100100010001
01010010010011001001000011110001
1001010001000011001000101000100
1001001000101001010101001001001
0100010100101000101001010010001
0010101011101010101010101010101
01011110111110000000000000011010
01111100001001110000011100100101
00000000111110010010001010011100
10010100001111000111000100101010
1010101010101001010010101010010
0101010101010101001001001
5
Ch. 12 - FPGA Testing - P. 5
FPGA Architectures

Early FPGAs
 NxN array of unit cells
– Unit cell = CLB + routing

Special routing along center axes
 I/O cells around perimeter

Next Generation FPGAs
 MxN array of unit cells
 Added small block RAMs at edges

PC
More Recent FPGAs
 Added larger block RAMs in array
 Added multipliers
 Added Processor Cores (PC)

PC
PC
Latest FPGAs
 Added DSP cores w/multipliers
 I/O cells along columns for BGA
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PC
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Ch. 12 - FPGA Testing - P. 6
Combinational Logic Functions
 Gates
are combined to
create complex circuits
 Multiplexer example




If S = 0, Z = A
If S = 1, Z = B
Common digital circuit
Heavily used in FPGAs
– Select input (S) controlled
by configuration memory
bit
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A
S
Z
B
Truth table
SAB Z
000 0
001 0
010 1
011 1
100 0
101 1
110 0
111 1
Logic symbol
A
B
0
Z
1
0
S1
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Ch. 12 - FPGA Testing - P. 7
Look-up Tables
Using multiplexer
example
 Configuration
memory holds
truth table
 Input signals
connect to select
inputs of
multiplexers to
select output
value of truth
table for any
given input value

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Multiplexer
0
0
A
0
1
B
0
1
Z
1
S
0
1
1
1
0
0
0
1
Z
1
0
1
0
1
1
0
0
1
1
1
B
0
A
Truth table
SAB Z
000 0
001 0
010 1
011 1
100 0
101 1
110 0
111 1
1
S
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Ch. 12 - FPGA Testing - P. 8
Basic Prog. Logic Block (PLB) Structure
 Look-up
table (LUT) for combinational logic
 Store truth table in LUT (typically 3 to 6 inputs)
 Some LUTs can also act as RAM/shift register
 Flip-flops
for sequential logic
 Programmable clock enable, set/reset
 Special
logic
 Large logic functions with Shannon expansion
 Fast carry for adders and counters
carry out
Input[1:4]
4
LUT/
RAM
Control
clock, enable, set/reset
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Carry &
Control
Logic
carry in
Flip-flop/
Latch
Output
Q output
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Ch. 12 - FPGA Testing - P. 9
Look-up Table Based RAMs
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Address Decoder
LUT mode Data In en0
performs read
en1
operations
en2
 Address decoder
In0
en3
In1
with write enable
In2
en4
generates load
en5
signals to latches
for write operations
en6
en7
 Small RAMs but
Write
can be combined Enable
for larger RAMs
Write Address
 Normal
0
0
0
1
0
1
0
1
1
1
0
0
0
1
Z
0
1
1
1
0
0
1
1
In0
In1
In2
Read Address
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Ch. 12 - FPGA Testing - P. 10
Input/Output Cells
 Bi-directional
buffers
 Programmable for input or output signals
 Tri-state control for bi-directional operation
 Flip-flops/latches for improved timing
– Set-up and hold times
– Clock-to-output delay
 Pull-up/down resistors
 Routing
resources
Tri-state Control
to/from
internal Output Data
routing
resources
Input Data
 Connections to core of array
 Programmable
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Bidirectional
Pad
Buffer
I/O voltage & current levels
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Ch. 12 - FPGA Testing - P. 11
Interconnect Network
 Wire
segments of varying length
 xN = N PLBs in length
– Typical values of N = 1, 2, 4, 6, 8
 Long lines
Wire A
config
bit
Wire B
– xH = half the array in length
– xL = full array in length
 Programmable
Interconnect Points (PIPs)
 Transmission gate connects to 2 wire segments
– Controlled by configuration memory bit
 Four basic types of PIPs
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Ch. 12 - FPGA Testing - P. 12
Programmable Interconnect Points

Break-point PIP
 Connect or isolate 2 wire segments

Cross-point PIP
 2 nets straight through
 1 net turns corner and/or fans out

Compound cross-point PIP
 Collection of 6 break-point PIPs
– Can route 2 isolated signal nets

Multiplexer PIP
 Directional and buffered
 Main routing resource in recent FPGAs
 Select 1-of-N inputs for output
– Decoded MUX PIP – N configuration bits select from 2N inputs
– Non-decoded MUX PIP – 1 configuration bit per input
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Ch. 12 - FPGA Testing - P. 13
Recent Architectural Trends

Addition of specialized cores:
 Memories
– Single and dual-port RAMs
– FIFO (first-in first-out)
– ECC (error correcting codes)
 Digital signal processors (DSPs)
– Multipliers
– Accumulators
– Arithmetic/logic units (ALUs)
 Embedded processors
– Hard core (dedicated processors)


With dedicated program/data
memories
Otherwise, programmable RAMs in
FPGA used for program/data
memories
= PLBs
= routing resources
= special cores
= I/O cells
– Soft core (synthesized from a HDL)
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Ch. 12 - FPGA Testing - P. 14

FPGA Resources
Types and sizes of resources vary with FPGA family
 Example: LUTs vary from 3-input to 6-input
– 4-input LUTs are most common

Typical ranges for some commercially available FPGAs
FPGA Resource
Logic
Routing
Specialized
Cores
Other
Small FPGA Large FPGA
PLBs per FPGA
256
25,920
LUTs and flip-flops per PLB
1
8
Wire segments per PLB
45
406
PIPs per PLB
139
3,462
Bits per memory core
128
36,864
Memory cores per FPGA
16
576
DSP cores
0
512
Input/output cells
62
1,200
Configuration memory bits
42,104
79,704,832
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Ch. 12 - FPGA Testing - P. 15
Configuration Interfaces

Master mode (Serial or Parallel options)
 FPGA retrieves configuration from ROM at power-up

Slave (Serial or Parallel options)
 FPGA configured by external source (i.e., a P)
 Used for dynamic partial reconfiguration

Boundary Scan Interface




4-wire IEEE standard serial interface for testing
Write and read access to configuration memory
Interfaces to FPGA core internal routing network
Not available in all FPGAs
clock
PROM with
Config Data
data out
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CCLK
CCLK
FPGA in
Master Mode
Din
Dout
CCLK
FPGA in
Slave Mode
Din
Dout
FPGA in
Slave Mode
Din
Dout
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Ch. 12 - FPGA Testing - P. 16
FPGA Configuration Memory
 PLB
addressable
 Good for partial reconfiguration
 X-Y coordinates of PLB location to be written
– “Z” coordinate identifies which
resources will be configured
 Frame
addressable
 Vertical or horizontal frame
– Vertical frames most common
 Access to all PLBs in frame
– Only portion of logic and routing
resources accessible in a given frame
– Many frames required to configure PLBs & routing
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Ch. 12 - FPGA Testing - P. 17
Configuration Techniques
 Full configuration & readback
 Simple configuration interface
– Automatic internal calculation of frame address
 Long download time for large FPGAs
 Partial reconfiguration & readback
 Only change portions of configuration memory with
respect to reference design
– Reduces download time for reconfiguration
 Requires a more complicated configuration interface
– Command Register (CMR)
– Frame Length Register (FLR)
– Frame Address Register (FAR)
– Frame Data Register (FDR)
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Ch. 12 - FPGA Testing - P. 18
Configuration Techniques
 Compressed
configuration
 Requires multiple frame write capability
– Write identical frames of config data to multiple frame
addresses
 Extension of partial reconfiguration interface
capabilities
– Frame address is much smaller than frame of
configuration data
 Reduces download time for initial configuration
depending on
– Regularity of system function design
– % utilization of array

Unused portions written with default configuration data
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Ch. 12 - FPGA Testing - P. 19
FPGA Testing Taxonomy
Test Approach Attribute
Test pattern application and
output response analysis
Internal (BIST)
External
System-level testing
Off-line
On-line
System application
Independent
Dependent
Logic
Routing
Target programmable resources

Classification
PLBs
I/O cells Cores
Local
Global
On-line test while system is operational
 Off-line test while system is out-of-service

Application-dependent testing tests only those
FPGA resources used by intended system function
 Application-independent testing tests all FPGA resources
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Ch. 12 - FPGA Testing - P. 20
FPGA Test Configurations

More test configurations required for routing
resources than for logic resources
 Data below from publications on actual test
configuration implementations in commercial FPGAs
FPGA
Vendor
Number of Test Configurations
Series
PLBs
ORCA2C
9
27
0
ORCA2CA
14
41
0
[Abramovici 2001]
[Stroud 2002b]
Atmel
AT40K/AT94K
4
56
3
[Sunwoo 2005]
Cypress
Delta39K
20
419
11
[Stroud 2000]
4000E/Spartan
12
128
0
4000XL/XLA
12
206
0
Virtex/Spartan-II
12
283
11
[Dhingra 2005]
Virtex-4
15
?
15
[Milton 2006]
Lattice
Xilinx
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Routing Cores
Reference
[Stroud 2003]
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Ch. 12 - FPGA Testing - P. 21
A Simple PLB Architecture

Two 3-input LUTs
 Can implement any 4-input
combinational logic function
 Can implement full adder
– Carry in LUT C
– Sum in LUT S

1 flip-flop
– Active levels
– Clock edge
– Set/reset

22 configuration
memory bits
D2-0
LUT
LUT C
8x1
D2-0
3
 Programmable:
C7
C6
C5
C4
C3
C2
C1
C0
111 110 101 100 011 010 001 000
out
Cout
Smux
SOmux
0 Sout
1
0
1
LUT S
8x1
D3
0
1
CB5
CEmux
CB3
Clock Enable
SRmux
0
1
CB4
FF
Set/Reset
Clock
 8 per LUT
– C7-C0 and S7-S0
CB
CB0
CB1
CB2
= Configuration
Memory Bit
 6 control bits
– CB5-CB0
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Ch. 12 - FPGA Testing - P. 22
Test Configurations for Simple PLB

All configuration memory bits must be tested for both
logic values (0 and 1) assuming exhaustive input patterns
 Output effects for each logic value must be observed

Exclusive-OR (XOR) and exclusive-NOR (XNOR)
functions are good for testing LUTs
 Put opposite functions in adjacent LUTs to produce opposite logic
values at inputs to subsequent logic functions

Fault coverage results below are based on collapsed
single stuck-at gate-level fault model (174 faults total)
Configuration Bits Configuration #1 Configuration #2 Configuration #3
LUT C (C7 - C0)
XNOR (01101001)
LUT S (S7 - S0)
XOR (10010110)
CB0 - CB5
000010
111110
000001
Individual FC
149/174 = 85.6%
149/174 = 85.6%
108/174 = 62.1%
Cumulative FC
85.6%
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XOR (10010110)
XOR (10010110)
XNOR (01101001) XNOR (01101001)
97.7%
100%
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Ch. 12 - FPGA Testing - P. 23
BIST for FPGAs
 Basic
idea:
 Program some logic resources to act as
– Test pattern generators (TPGs)
– Output response analyzers (ORAs)
– Resources under test


Logic resources as blocks under test (BUTs)
Routing resources as wires under test (WUTs)
 Goal:
 Minimize number of test configurations to
minimize download time
– Download time dominates total test time
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Ch. 12 - FPGA Testing - P. 24
TPG and ORA Implementations

TPG implementation depends on test algorithm
 May be implemented in different resources (see table below)
 Multiple TPGs prevent faulty TPG from escaping detection
 Lower bound on number of PLBs per TPG, TPLB = BIN  NFF
– BIN = number of inputs to BUT
– NFF = number of FFs/PLB

ORAs most efficiently implemented in PLBs
 Number of PLBs needed for ORAs, OPLB = (NBUT × BOUT)  NFF
– BOUT = number of outputs from BUT
– NBUT = number of BUTs
Resource Under Test
TPGs
ORAs
PLBs
PLBs or DSP cores
PLBs
LUT RAMs
PLBs or DSP and RAM cores
PLBs
I/O cells
PLBs or DSP and RAM cores
PLBs
Cores (memories, DSPs, etc.)
PLBs
PLBs
Interconnect
PLBs
PLBs
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Ch. 12 - FPGA Testing - P. 25
TPG Algorithms

Small logic functions (PLBs, IOBs) can be tested
with pseudo-random test patterns
 LFSRs or counting patterns

Large logic functions (RAMs, DSPs) require
specialized test algorithms for high fault coverage
 Below are examples of typical RAM test algorithms
Algorithm
March Test Sequence
March Y
↨(w0); ↑(r0, w1,r1); ↓(r1, w0, r0);↑(r0)
March LR
w/o BDS
↨(w0); ↓(r0, w1); ↑(r1, w0, r0, r0, w1);
March LR
with BDS
↑(r1, w0); ↑(r0, w1, r1, r1, w0); ↑(r0)
↨(w00); ↓(r00, w11); ↑(r11, w00, r00, r00, w11);
↑(r11, w00); ↑(r00, w11, r11, r11, w00);
↑(r00, w01, w10, r10); ↑(r10, w01, r01); ↑(r01)
Notation: w0 = write 0 (or all 0’s), r1 = read 1 (or all 1’s)
↑= address up, ↓= address down, ↨ = address either way
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Ch. 12 - FPGA Testing - P. 26
Output Response Analyzers
 Comparison-based
 XOR with OR feedback
from flip-flop
BUTj output
BUTk output
shift data
shift mode
– Latches mismatches
observed due to faults
 Results
retrieval
 ORA with shift register
BUTj output
BUTk output
– Requires additional logic
 Configuration memory
readback
– Read contents of ORA
flip-flops

Good with partial
configuration memory
readback capabilities
EE141
System-on-Chip
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Pass/
Fail
Pass/
Fail
BUTj output1
BUTk output1
BUTj outputn
BUTk outputn
Pass/
Fail
27
Ch. 12 - FPGA Testing - P. 27
Logic Resource BIST Architectures
 Basic
comparison
 Multiple TPGs drive alternating
columns (rows) of blocks under
test (BUTs)
 BUTs in center of array observed
by 2 sets of ORAs and compared
with 2 other BUTs
 BUTs along edges of array
observed by only 1 set of ORAs
– Some loss of diagnostic resolution
Basic Comparison
=TPG
=ORA
=BUT
 Originally used to test PLBs
– Later used to test specialized cores
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Ch. 12 - FPGA Testing - P. 28
Logic Resource BIST Architectures
 Circular
Comparison
 Multiple TPGs drive alternating
columns (rows) of blocks under
test (BUTs)
 All BUTs observed by 2 sets of
ORAs and compared with 2 other
BUTs
Circular Comparison
– Good diagnostic resolution
 Originally used to test specialized
cores
=TPG
=ORA
=BUT
– Later used to test PLBs and I/O cells
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Ch. 12 - FPGA Testing - P. 29
Logic Resource BIST Architectures

Expected Results comparison
expected
results
test
patterns
 Multiple TPGs
– One set of TPGs drive BUTs
– Other set of TPGs produce expected
results for comparison with outputs of
BUTs
Expected Results
 BUTs observed by 1 set of ORAs
and compared with expected results
from TPGs
– Simple diagnosis since failing ORA
position indicates faulty BUT
 Good when expected results can be
algorithmically generated easily
=TPG
=ORA
=BUT
– Example: RAM test algorithms
 Originally used to test RAM cores
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Ch. 12 - FPGA Testing - P. 30
Logic Resource Diagnostic Procedure
1.
2.
3.
4.
Record ORA results; 1= failure indication.
For every set of 2 or more consecutive ORAs with 0s, enter
0s for all BUTs observed by these ORAs; the BUTs are faultfree.
For every adjacent 0 and 1 followed by an empty space,
enter 1 to indicate BUT is faulty; continue while such entries
exist.
If an ORA indicates a failure but both BUTs monitored by the
ORA are fault-free, one of the following conditions exist:
A.
B.
C.
5.
A fault in routing resources between one of the BUTs and the ORA,
ORA is faulty, or
There are more than 2 consecutive BUTs with equivalent faults (for
circular comparison only); reorder circular comparison and repeat test
and diagnostic procedure.
Remaining BUTs marked as unknown may be faulty; reorder
circular comparison or rotate basic comparison architecture
by 90, repeat test and diagnostic procedure.
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Ch. 12 - FPGA Testing - P. 31
Diagnostic Procedure Examples


Note that B4 and B5 have equivalent faults in Example A
Circular comparison provides better diagnostic resolution
 Also indicates when more than 2 consecutive BUTs with equivalent
faults (Example C)
Example A
Example B
Example C
BIST Architecture
Basic
Circular
Basic
Circular
Basic
Circular
Diagnostic Step
1 2 3
1 2 3
1 2 3
1 2 3
1 2 3
1 2 3
0
0 0
0
0 0
0
1 1
0
0 0
0
0 0
0
1 1
0
0 0
0
0 0
0
1 1
0
0 0
0
0 0
0
1 1
B1
O12
B2
O23
B3
O34
B4
O45
B5
O56
B6
O61
EE141
System-on-Chip
Test Architectures
0
0
0
0
0
1
1
0 0 0
1
1 1 1
?
0 0
1 1
0
0 0
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
1
1
1 1 1
?
1 1 1
?
0
1
0 0
0 1 1 1 1 1 1
0
0 0
0 0
0 0 0 0 0 0 0
0
0 0
0 0
1 0 0 0 0 0 0
1
0 0
0 0
1 1 1 1 1 1 1 1 1
1
1
0 0
1 1 1 0 0 1 0 0 0
0 0
1
0 0
0 0 0
0
32 0 0
Ch. 12 - FPGA Testing - P. 32
Testing Routing Resources
 Comparison-based
BIST approach
 Developed for on-line FPGA BIST
 Testing restricted to routing resources
for 2 rows or 2 columns of PLBs
 Small Self-Test AReas (STARs)
 Comparison-based ORA
 Later
applied to off-line BIST
 Fill FPGA with STARs
 Tests run concurrently
 Diagnostic resolution to STAR
 Easier
BIST development
 But more BIST configurations
EE141
System-on-Chip
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TPG
WUTs
ORA
STAR
T T T T T
FPGA
O O O O O
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Ch. 12 - FPGA Testing - P. 33
Testing Routing Resources

TPG
WUTs
parity
bit
ORA
Original parity-based BIST approach
 Parity bit routed over fault-free resources
– What is fault-free until you’ve tested it?

Modified parity-based approach
 N-bit up-counter with even parity, and
 N-bit down-counter with odd parity
– Gives opposite logic values for
 Stuck-on PIPs & bridging faults
 Parity used as test pattern
– N+1 wires under test
 Good for small PLBs
– like our simple PLB example

Make STARs as small as possible
 Better diagnostic resolution
 Easier BIST development
EE141
System-on-Chip
Test Architectures
parity-check
based-ORA
TPG
Par
C1
C0
WUTs
O
R
A
+
34
Ch. 12 - FPGA Testing - P. 34
Testing Routing Resources

Testing typically separated by routing resources
 Global - interconnects non-adjacent logic resources
 Local - interconnects adjacent logic resources and
connects logic resources to global routing

Additional test configurations swap positions of
TPGs and ORAs to reverse direction of signal flow
to test directional, buffered routing resources
 Multiplexer PIPs are a good example
=TPG
=ORA
global routing
EE141
System-on-Chip
Test Architectures
local routing
PLB feed-through
local routing
adjacent PLBs
35
Ch. 12 - FPGA Testing - P. 35
Reducing Test Time

Orient BIST architecture to configuration memory
 Align along rows/columns depending on FPGA structure

Downloading BIST configurations
 Compressed configuration for initial download
 Partial reconfiguration for subsequent downloads
– Reduce number of frames written between configurations



Keep routing constant between BIST configurations
Optimize order of BIST configuration application
Retrieving BIST results
 Partial configuration memory readback
– Eliminates ORA logic for scan chain

Allows concurrent testing of more resources
– Minimize number of frames to be read
 Dynamic partial reconfiguration
– Read BIST results after a series of BIST configurations
Slight loss in diagnostic resolution
EE141
System-on-Chip
Test Architectures

36
Ch. 12 - FPGA Testing - P. 36
Embedded Processor Based BIST
New area of R&D in FPGA testing
 Basic idea:

 Embedded processor core
– Hard or soft core
 Configures FPGA for BIST
– Via internal configuration access port (ICAP)

Alternative: download initial BIST configuration
 Executes BIST sequence
= BUT
= ORA
– May provide TPG functionality
 Retrieves BIST results
– May perform diagnostic procedure
 Reconfigures FPGA for subsequent BIST
configurations

Soft core requires two test sessions to
test area occupied by processor core
during first test session
EE141
System-on-Chip
Test Architectures
Processor core,
TPGs and interface
to ICAP circuitry
Test session #1
Processor core,
TPGs and interface
to ICAP circuitry
Test session #2
37
Ch. 12 - FPGA Testing - P. 37
Embedded Processor BIST

Overall reduction in total test time
 Algorithmic reconfiguration faster than external download
– 10 to 25 times faster
– Results below from actual implementation in commercial FPGA

Can be loaded into processor program memory for
on-demand BIST and diagnosis of FPGA
 Good for fault-tolerant applications where system function
is reconfigured around diagnosed fault(s)
Resource
Function
Download
Execution
Total time
Download
Routing
Execution
BIST
Total time
Total Test Time
EE141
System-on-Chip
Test Architectures
PLB
BIST
External
7.680 sec
0.016 sec
7.696 sec
20.064 sec
0.026 sec
20.090 sec
27.786 sec
Processor
Speed-up
0.101 sec
76.0
0.085 sec
0.2
0.186 sec
41.4
0.110 sec
182.4
0.343 sec
0.075
0.453 sec
44.3
0.639 sec
43.5 38
Ch. 12 - FPGA Testing - P. 38
Concluding Remarks
Growing use of FPGAs in systems and SOCs
 FPGA testing is necessary but difficult due to





Programmability
Complex programmable interconnect network
Constantly growing size and changing architectures
Incorporation of new and different specialized cores
Test & diagnosis allows fault-tolerant applications
 New FPGA capabilities assist in testing solutions

 Dynamic partial reconfiguration and readback
 Configuration/reconfiguration by embedded processor
cores
EE141
System-on-Chip
Test Architectures
39
Ch. 12 - FPGA Testing - P. 39