Transcript PARBIT - Partial Bitfile Configuration Tool

PARBIT
Partial Bitfile Configuration Tool
Edson L. Horta
([email protected])
Washington University, Applied Research Lab
August 15, 2001
Supported by: NSF ANI-0096052;
Xilinx Inc. and CNPq (Brazil)
PARBIT Tool
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Motivation
FPX
RECATS
Single
chip
ATM
Switch
VIRTEX FPGA
Mutual Need: tool to generate
VIRTEX FPGA
Partial Reconfigurable
partial configuration files for
Partial
Reconfigurable
VIRTEX
FPGA
Dynamic Hardware Plugin
www.lsi.usp.br/~recats
http://www.arl.wustl.edu/arl/projects/fpx
PARBIT
PARBIT Tool
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VIRTEX Architecture
• Resources
–
–
–
–
CLBs
IOBs
Block SelectRAMs
Clocks
• Configuration
– bitstream: configuration bitfile
– configuration columns
•
•
•
•
•
PARBIT Tool
Center
CLB
IOB
Block SelectRAM Interconnect
Block SelectRAM Content
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PARBIT Tool
CLB Column
CLB Column
2
IOBs
2
2
2
IOBs GCLKs IOBs
2
IOBs
Right IOB Column
Block SelectRAM Content
2
2
2
IOBs GCLKs IOBs
Block SelectRAM Interconnect
Center Column
2
IOBs
CLB Column
CLB Column
Block SelectRAM Interconnect
Block SelectRAM Content
Left IOB Column
VIRTEX Architecture
• Configuration Columns
2
IOBs
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PARBIT Tool - Introdution
• A Tool that transforms configuration bitfiles to generate
partial configuration bitfiles with hardware realocation
• Command-line interface
• Environment
– Windows (Cygwin)
– Unix
• Devices supported:
– XCV50E, XCV100E, XCV200E, XCV300E, XCV400E,
XCV405E, XCV600E, XCV812E, XCV1000E, XCV1600E,
XCV2000E,XCV2600E, XCV3200E.
• http://www.arl.wustl.edu/arl/projects/fpx/parbit/
PARBIT Tool
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PARBIT Tool - Introdution
User Parameters
Parameters
OK ?
Y
Write Header
N
FPGA Type
Error
Message
END
Coordinates
Shutdown
Configuration Port
Copy Config. Bits
Write Trailer
END
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PARBIT Tool - Introdution
• Utilization
– parbit option original partial target
• Input Files
– option: user parameters
– original: Dynamic Hardware Plugin (DHP)
bitstream
– target: infrastructure bitstream
• Output File
– partial: generated partial bitstream
• Generating the input bitstream files
– Xilinx Tools
– Constraints commands in the UCF file
PARBIT Tool
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PARBIT Tool - Introdution
• Original Bitstream File
– DHP User Module
– Locks the interface signals to the infrastrucuture
– Locks the area of user logic
• Target Bitstream File
– Infrastructure Logic
– Locks the interface signals to the DHP User
Module
– Allocate blank areas (targets) to download new
DHP Modules
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PARBIT Tool – Original Bitstream
Start Column = 8
End Column = 17
Top IOBs
Left IOB s
Right IOBs
DHP
Start Row = 7
End Row = 74
PARBIT Tool
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
Bottom IOBs
– Dynamic
Hardware
Plugin (DHP)
confined in a
rectangular
region
– PARBIT
parameters
• Start Row and
Start Col
• End Row and
End Col
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Original Bitstream - DHP Module
FD
dout
din
OUT GAS K
gask_out[1]
FD
FD
dout
din
FD
COL5
PARBIT Tool
FD
FD
INGAS K
dout
din
OUT GAS K
gask_out[3]
• Interface
signals and
flops
INGAS K
OUT GAS K
gask_out[2]
gask_cl k
gask_out[0]
INGAS K
gask_i n[3]
OUT GAS K
gask_i n[2]
DHP
gask_i n[1]
gask_i n[0]
GASK_DHP
FD
INGAS K
dout
din
FD
• DHP User
Module
COL8
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DHP User Module - Example
• 8 stages of combinatorial function, with registered outputs
• Connects to gas_dhp entity buses (din, dout)
• Consumes 32 CLBs
USER_DHP_V101
Stage 7
Stage 1
Stage 0
dout[0]
CK
CK
CK
QD
QD
QD
CK
QD
dout[3]
CK
CK
QD
CK
CK
QD
CK
QD
QD
QD
CK
CK
CK
din[1]
Function
QD
Function
dout[2]
QD
Function
dout[1]
din[0]
QD
din[2]
din[3]
clk
PARBIT Tool
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DHP Module - VHDL
library IEEE;
use IEEE.std_logic_1164.all;
architecture dhp_arch of dhp is
-- The User's Module Logic goes HERE
-- Top Level Entity of DHP also specifies
-- pins so that a FPGA can be routed and placed
entity gask_dhp is port(
gask_in: in std_logic_vector(3 downto 0);
gask_clk: in std_logic;
gask_out: out std_logic_vector(3 downto 0));
end gask_dhp;
signal stage0_sig: std_logic_vector (3 downto 0);
signal stage1_sig: std_logic_vector (3 downto 0);
signal stage2_sig: std_logic_vector (3 downto 0);
signal stage3_sig: std_logic_vector (3 downto 0);
signal stage4_sig: std_logic_vector (3 downto 0);
signal stage5_sig: std_logic_vector (3 downto 0);
signal stage6_sig: std_logic_vector (3 downto 0);
begin
library IEEE;
use IEEE.std_logic_1164.all;
USE ieee.std_logic_arith.ALL;
-- Entity of a Dynamic Hardware Plugin
entity dhp is port(
din: in std_logic_vector(3 downto 0);
clk: in std_logic;
dout: out std_logic_vector(3 downto 0));
end dhp;
PARBIT Tool
Stage0: process (clk)
begin
if(clk'event AND clk = '1') then
stage0_sig(0) <= NOT din(0) OR din(1);
stage0_sig(1) <= din(2) XOR din(0);
stage0_sig(2) <= NOT din(3) NOR din(2);
stage0_sig(3) <= din(1) AND din(0);
end if;
end process;
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DHP Module - VHDL
Stage1: process (clk)
…………………………………
…………………………………
Stage7: process (clk)
begin
if(clk'event AND clk = '1') then
dout(0) <= stage6_sig(2) NAND stage6_sig(0);
dout(1) <= NOT stage6_sig(3) NAND
stage6_sig(3);
dout(2) <= NOT stage6_sig(0) XOR
stage6_sig(2);
dout(3) <= stage6_sig(1) NAND stage6_sig(1);
end if;
end process;
end dhp_arch;
architecture gask_dhp_arch of gask_dhp is
component FD port( D: in std_logic;
C: in std_logic;
Q: out std_logic);
end component;
PARBIT Tool
-- The User's Module is the Main Component of
the Module design
component dhp is port(
din: in std_logic_vector(3 downto 0);
clk: in std_logic;
dout: out std_logic_vector(3 downto 0));
end component;
signal ding,doutg:std_logic_vector(3 downto 0);
begin
D: dhp port map(ding,gask_clk,doutg);
-- Specifies the same Flops in the same location
G: for i in 0 to 3 generate
INGASK : FD port map(
gask_in(i),
gask_clk,
ding(i));
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DHP Module - VHDL and UCF File
OUTGASK : FD port map(
doutg(i),
gask_clk,
gask_out(i));
end generate;
end gask_dhp_arch;
# gask_dhp.ucf
# PINS
NET gask_clk LOC=B8;
NET gask_in<0> LOC=C8;
NET gask_in<1> LOC=B7;
NET gask_in<2> LOC=A6;
NET gask_in<3> LOC=D8;
NET gask_out<0> LOC=F3;
NET gask_out<1> LOC=D1;
NET gask_out<2> LOC=G3;
NET gask_out<3> LOC=F5;
# Include Region for DHP User Module
INST /D* LOC=clb_r3c6:clb_r6c7;
#
FLOPS
INST /OUTGASK_0* LOC=clb_r3c5.s0;
INST /OUTGASK_1* LOC=clb_r4c5.s0;
INST /OUTGASK_2* LOC=clb_r5c5.s0;
INST /OUTGASK_3* LOC=clb_r6c5.s0;
INST /INGASK_0* LOC=clb_r3c8.s1;
INST /INGASK_1* LOC=clb_r4c8.s1;
INST /INGASK_2* LOC=clb_r5c8.s1;
INST /INGASK_3* LOC=clb_r6c8.s1;
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DHP Module – FPGA Editor (XCV50E)
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DHP Module – FPGA Editor (XCV50E)
ROW 3
DHP
User
Module
ROW 4
ROW 5
ROW 6
COL 5
PARBIT Tool
COL 6
COL 7
COL 8
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PARBIT Tool – Target Bitstream
TARGET 1
T1 (7,8)
TARGET 2
TARGET 3
T2 (7,20)
TARGET 4
T3 (7,68)
T4 (7,80)
Top IOBs
Left IOBs
Right IOBs
I
N
F
R
A
S
T
R
U
C
T
U
R
E
• Target
Locations
(Row, Col)
RAM
RAM
RAM
RAM
RAM
RAM
Bottom IOBs
PARBIT Tool
– Infrastructure
with target
regions
reserved for
DHP modules
insertions
– PARBIT
parameters
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Target Bitstream - Infrastructure Module
gask_clk
gask_in[3]
gask_in[2]
gask_in[1]
gask_in[0]
• I/O Pads
GASK_INF
G A SK _IO [0]
GAS KIN
GAS KOUT
gask_out[0]
FD
FD
G A SK _IO [1]
GAS KIN
GAS KOUT
gask_out[1]
FD
FD
G A SK _IO [2]
GAS KIN
GAS KOUT
gask_out[2]
FD
FD
G A SK _IO [3]
GAS KOUT
gask_out[3]
PARBIT Tool
• Interface
signals and
flops
GAS KIN
FD
FD
COL5
COL8
• On-chip
system
logic
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Infrastructure Module - VHDL
library IEEE;
use IEEE.std_logic_1164.all;
-- Top Level Entity of Infrastructure
entity gask_inf is port(
gask_in: in std_logic_vector(3 downto 0);
gask_clk: in std_logic;
gask_out: out std_logic_vector(3 downto 0));
end gask_inf;
library IEEE;
use IEEE.std_logic_1164.all;
-- Each gask_io module provides an input/ouput
-- interface between the infrastructure and
module
entity gask_io is port(
di: in std_logic;
clk: in std_logic;
qo: out std_logic);
end gask_io;
PARBIT Tool
architecture gask_io_arch of gask_io is
component FD port( D: in std_logic;
C: in std_logic;
Q: out std_logic);
end component;
signal q0 : std_logic;
-- Each gas_io module has two Flops, one
-- on each edge of DHP
begin
GASKIN : FD port map(D => di,
C => clk,
Q => q0);
GASKOUT: FD port map(D => q0,
C => clk,
Q => qo);
end gask_io_arch;
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Infrastructure Module - VHDL and UCF File
architecture gask_inf_arch of gask_inf is
component gask_io port(
di: in std_logic;
clk: in std_logic;
qo: out std_logic);
end component;
begin
G: for i in 0 to 3 generate
-- Bus contains an array of gask_io modules
GASK : gask_io port map(
gask_in(i),
gask_clk,
gask_out(i));
end generate;
# gask_inf.ucf
# PINS
NET gask_clk LOC=B8;
NET gask_in<0> LOC=C8;
NET gask_in<1> LOC=B7;
NET gask_in<2> LOC=A6;
NET gask_in<3> LOC=D8;
NET gask_out<0> LOC=F3;
NET gask_out<1> LOC=D1;
NET gask_out<2> LOC=G3;
NET gask_out<3> LOC=F5;
# Exclude Region for DHP User Module
CONFIG PROHIBIT=CLB_R3C6:CLB_R6C7;
# FLOPS
INST /GASK_0/GASKOUT*
INST /GASK_1/GASKOUT*
INST /GASK_2/GASKOUT*
INST /GASK_3/GASKOUT*
LOC=clb_r3c5.s0;
LOC=clb_r4c5.s0;
LOC=clb_r5c5.s0;
LOC=clb_r6c5.s0;
end gask_inf_arch;
INST /GASK_0/GASKIN*
INST /GASK_1/GASKIN*
INST /GASK_2/GASKIN*
INST /GASK_3/GASKIN*
PARBIT Tool
LOC=clb_r3c8.s1;
LOC=clb_r4c8.s1;
LOC=clb_r5c8.s1;
LOC=clb_r6c8.s1;
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Infrastructure – FPGA Editor (XCV50E)
PARBIT Tool
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Infrastructure – FPGA Editor (XCV50E)
Flops and Interconnect Signals
(Same location as in DHP Module)
ROW 3
Reserved
Area
(Target)
for DHP
Module
ROW 4
ROW 5
ROW 6
COL 5
PARBIT Tool
COL 6
COL 7
COL 8
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PARBIT Tool - Example
• Utilization
– parbit option original partial target
• Example
– Visit:
http://www.arl.wustl.edu/arl/projects/fpx/parbit
– In the Download Section, right click on
parbit-expl.tar
PARBIT Tool
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PARBIT Tool - Downloading
PARBIT Tool
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PARBIT Tool - Downloading
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PARBIT Tool - Downloading
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PARBIT Tool - Downloading
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PARBIT Tool - Downloading
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PARBIT Tool - Downloading
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PARBIT Tool - Downloading
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PARBIT Tool - Demonstration
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PARBIT Tool - Demonstration
• Example (Cygwin Window)
– Run parbit
• parbit parbit-gask.opt gask_dhp.bit gask-part.bit gask_inf.bit
• Compare the sizes of gask_dhp.bit and gask-part.bit
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PARBIT Tool - Exercises
Exercise 1
Change the user parameters and generate a new partial
configuration bitstream (gask-part2.bit) for one user
module confined in a rectangular area with:
– Start row = 2
– Start col = 5
– Height = 3 rows
– Width = 4 columns
– Target location = Row 10, Col 15
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PARBIT Tool - Exercises
Exercise 2
• Go to the PARBIT web page and get the project files for
the gasket example (gask-design.tar)
• Modify the UCF files in order to change the location of
the DHP user module two rows down
• Compile each project:
– xflow –p xcv50e-8-fg256
–implement gask-i gask_dhp
• Open each project with the FPGA Editor:
– fpga_editor gask_dhp.ncd
• Check the new logic locations
• Edit the file gask_dhp.ucf
– Add 2 to the row numbers (rX)
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Configuration Frames - Full Slice
TARGET BITS
ORIGINAL BITS
TARGET BITS
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