Transcript Lecture 14 Finite State Machine Implementation

Lecture 15
Finite State Machine Implementation
Prith Banerjee
ECE C03
Advanced Digital Design
Spring 1998
ECE C03 Lecture 15
1
Outline
•
•
•
•
Mapping FSM to random logic
Mapping FSM to ROMS
Mapping FSM to PLAs
Mapping FSM to Programmable Logic Devices
(Xilinx)
• READING: Katz 10.1.1, 10.1.2, 10.3, Dewey 9.5
ECE C03 Lecture 15
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FSM Implementation Strategies
• Discrete Gate Logic
Emphasis so far
• MSI Logic (e.g., Counters)
• Structured Logic (e.g., PLA/PAL, ROM)
• Field Programmable Gate Arrays (FPGAs)
Function can be configured "on the fly" or in the field
Flipflops/Registers plus discrete gates on the same chip
ECE C03 Lecture 15
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FSM Design with Structured Logic
Combinational
Logic
Registers
Output
Function
Inputs
Outputs
Block Diagram for
Synchronous Mealy Machine
Next State
Function
State
ROM-based Realization
ROM
A0
Registers
D0
Inputs
Outputs
An-1
Dk-1
An
Dk
• Inputs & Current State
form the address
• ROM data bits form the
Outputs & Next State
An+m-1 Dk+m-1
State
ECE C03 Lecture 15
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ROM-Based Implementation
Example: BCD to Excess 3 Serial Converter
Conversion Process
Bits are presented in bit serial fashion
starting with the least significant bit
Single input X, single output Z
ECE C03 Lecture 15
BCD Excess 3 Code
0000
0011
0001
0100
0010
0101
0011
0110
0100
0111
0101
1000
0110
1001
0111
1010
1000
1011
1001
1100
5
BCD to Excess-3 Converter
Present State
S0
S1
S2
S3
S4
S5
S6
Next
X=0
S1
S3
S4
S5
S5
S0
S0
Output
X=0 X=1
0
1
0
1
1
0
1
0
0
1
1
0
-1
State
X=1
S2
S4
S4
S5
S6
S0
--
State Transition Table
Reset
0/1
S1
0/1
S0
S2
0/0,
1/1
1/0
S3
0/1
0/0,
1/1
S5
0/0,
1/1
1/0
Derived State Diagram
S4
1/0
S6
0/1
ECE C03 Lecture 15
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ROM-Based Implementation
BCD to Excess 3 Converter
ROM Address
X Q2 Q1 Q0
0
0
0 0
0
0
0 1
0
0
1 0
0
0
1 1
0
1
0 0
0
1
0 1
0
1
1 0
0
1
1 1
1
0
0 0
1
0
0 1
1
0
1 0
1
0
1 1
1
1
0 0
1
1
0 1
1
1
1 0
1
1
1 1
ROM Outputs
Z D2 D1 D0
1 0
0 1
1 0
1 1
0 1
0 0
0 1
0 1
1 1
0 1
0 0
0 0
1 0
0 0
X X X X
0 0
1 0
0 1
0 0
1 1
0 0
1 1
0 1
0 1
1 0
1 0
0 0
X X X X
X X X X
1
CLK
1
0
X
converter ROM
X
Q2
Q1
Q0
Z
D2
D1
D0
1
0
9
13
12
5
4
CLK
D
C
B
A
QD
175 QD
QC
QC
QB
QB
1 CLR
\Reset
15
14
10
11
7
6
2
QA
3
QA
Circuit Level Realization
74175 = 4 x positive edge triggered D FFs
Truth Table/ROM I/Os
In ROM-based designs,ECE
noC03
need
to consider state assignment
Lecture 15
7
Z
ROM Based Implementation
BCD to Excess-3 Converter
LSB
MSB
Timing Behavior for input strings 0 0 0 0 (0) and 1 1 1 0 (7)
0
0
1
0000
LSB
0
1
0
0
1
0
1
0
1100
1110
1
1
0
0
1
0101
LSB
ECE C03 Lecture 15
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PLA Based Design
BCD to Excess 3 Converter
State Assignment with NOVA
0
1
0
1
0
1
0
1
0
1
0
1
0
S0
S0
S1
S1
S2
S2
S3
S3
S4
S4
S5
S5
S6
S1
S2
S3
S4
S4
S4
S5
S5
S5
S6
S0
S0
S0
1
0
1
0
0
1
0
1
1
0
0
1
1
S0 = 000
S1 = 001
S2 = 011
S3 = 110
S4 = 100
S5 = 111
S6 = 101
NOVA derived
state assignment
9 product term
implementation
NOVA input file
ECE C03 Lecture 15
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PLA Implementation
BCD to Excess 3 Converter
.i 4
.o 4
.ilb x q2
.ob d2 d1
.p 16
0 000 001
1 000 011
0 001 110
1 001 100
0 011 100
1 011 100
0 110 111
1 110 111
0 100 111
1 100 101
0 111 000
1 111 000
0 101 000
1 101 --0 010 --1 010 --.e
Espresso Inputs
q1 q0
d0 z
1
0
1
0
0
1
0
1
1
0
0
1
1
-
Espresso Outputs
ECE C03 Lecture 15
.i 4
.o 4
.ilb x q2 q1 q0
.ob d2 d1 d0 z
.p 9
0001 0100
10-0 0100
01-0 0100
1-1- 0001
-0-1 1000
0-0- 0001
-1-0 1000
--10 0100
---0 0010
.e
10
PLA Implementation
BCD to Excess 3 Converter
D2 = Q2 • Q0 + Q2 • Q0
D1 = X • Q2 • Q1 • Q0 + X • Q2 • Q0 + X • Q2 • Q0 + Q1 • Q0
D0 = Q0
Z = X• Q1 + X • Q1
1
CLK 9
1
0
X
conv erter PLA
X
Q2
Q1
Q0
Z
D2
D1
D0
1
0
13
12
5
4
CLK
175
D
C
B
A
1 CLR
\Reset
ECE C03 Lecture 15
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QD
14
QD
10
QC
11
QC
7
QB
6
QB
2
QA
3
QA
Z
11
PAL Implementation
BCD to Excess 3 Serial Converter
10H8 PAL: 10 inputs, 8 outputs, 2 product terms per OR gate
D1 = D11 + D12
D11 = X • Q2 • Q1 • Q0 + X • Q2 • Q0
D12 = X • Q2 • Q0 + Q1 • Q0
0 1 2 3
45
89
12 13 16 17 20 21 24 25 28 29 30 31
X
0. Q2 • Q0
1. Q2 • Q0
8. X • Q2 • Q1 • Q0
9. X • Q2 • Q0
16. X • Q2 • Q0
17. Q1 • Q0
24. D11
25. D12
32. Q0
33. not used
40. X • Q1
41. X • Q1
0
1
D2
8
9
D11
16
17
D12
24
25
D1
32
33
D0
40
41
Z
Q2
Q1
Q0
D11
D12
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PAL Implementation
BCD to Excess 3 Serial Converter
0 1 2 3
45
89
12 13 16 17 20 21 24 25 28 29 30 31
X
0
1
D2
8
9
D11
16
17
D12
24
25
D1
32
33
D0
40
41
Z
Q2
Q1
Q0
D11
D12
ECE C03 Lecture 15
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More Advanced PAL Architectures
Registered PAL Architecture
Buffered Input
or product term
CLK
OE
Q2 • Q0 + Q2 • Q0
Q2 • Q0
Q2 • Q0
D2
Q2+
Q2+
DQ
Q
Q2+
Q2 • Q0 + Q2 • Q0
X
Q2 Q2
Q0 Q0
Negative Logic
Feedback
D2 = Q2 • Q0 + Q2 • Q0
D1 = X • Q2 • Q1 • Q0 + X • Q2 + X • Q0 + Q2 • Q0 + Q1 • Q0
D0 = Q0
Z = X • Q1 + X • Q1
ECE C03 Lecture 15
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Advanced PAL Architectures
Programmable Output Polarity/XOR PALs
CLK
OE
Buried Registers: decouple
FF from the output pin
DQ
Q
Advantage of XOR PALs: Parity and Arithmetic Operations
AB
AB
AB
AB
AB
AB
AB
AB
C
C
C
C
C
C
C
C
D
D
D
D
D
D
D
D
A  B  C  D
AB
AB
A  B  C  D
CD
CD
ECE C03 Lecture 15
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Examples of XOR and Registered PALs
Example of XOR PAL
Example of Registered PAL
INCREMEN
T
INCREMEN
T
1
1
0
FIRST
FUSE
NUMBER
4
8
12
16
20
24
28
32
0
36
0
40
D
Q
23
80
120
FIRST
FUSE
NUMBER
S
Q
2
4
8
12
16
20
24
28
0
32
64
96
128
160
192
224
19
2
160
200
D
240
280
Q
22
256
288
320
352
384
416
448
480
Q
3
320
360
D
400
440
Q
21
512
544
576
608
640
672
704
736
4
D
560
600
Q
20
D
720
760
Q
18
Q
D
Q
17
Q
4
Q
768
800
832
864
896
928
960
992
5
640
680
Q
3
Q
480
520
D
19
Q
D
Q
16
Q
5
6
800
840
D
880
920
Q
1024
1056
1088
1120
1152
1184
1216
1248
18
Q
7
D
Q
15
Q
6
960
1000
D
Q
17
1280
1312
1344
1376
1408
1440
1472
1504
1040
1080
Q
8
1120
1160
D
Q
16
1536
1568
1600
1632
1664
1696
1728
1760
Q
9
D
Q
15
1360
1400
D
Q
1792
1824
1856
1888
1920
1952
1984
2016
14
1520
1560
Q
13
11
INCREMEN
T
0
4
8
12
16
20
24
28
32
14
Q
D
Q
13
Q
8
Q
10
1440
1480
Q
7
1200
1240
1280
1320
D
9
12
11
36
NOTE: FUSE NUMBER = FIRST FUSE NUMBER +
INCREMENT
ECE C03 Lecture 15
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FSM Design With Counters
Synchronous Counters: CLR, LD, CNT
0
Four kinds of transitions for each state:
(1) to State 0 (CLR)
CLR
(2) to next state in sequence (CNT)
(3) to arbitrary next state (LD)
(4) loop in current state
CNT
n+1
n
no
signals
asserted
LD
m
Careful state assignment is needed to reflect basic sequencing
of the counter
ECE C03 Lecture 15
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Implementation Strategies
FSM Design with Counters
Excess 3 Converter Revisited
Reset
0/1
1
0/1
0
4
1/0
0/0,
1/1
0/1
3
0/0,
1/1
Note the sequential nature
of the state assignments
5
2
0/0,
1/1
1/0
1/0
6
0/1
ECE C03 Lecture 15
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Implementation Strategies
FSM Design with Counters
Excess 3 Converter
Inputs/Current
Next
State
State
X Q2 Q1 Q0 Q2+ Q1+
0 0 0 0
0
0
0 0 0 1
0
1
0 0 1 0
0
1
0 0 1 1
0
0
0 1 0 0
1
0
0 1 0 1
0
1
0 1 1 0
0
0
0 1 1 1
X
X
1 0 0 0
1
0
1 0 0 1
1
0
1 0 1 0
0
1
1 0 1 1
0
0
1 1 0 0
1
0
1 1 0 1
1
1
1 1 1 0
X
X
1 1 1 1
X
X
Outputs
Q0+
1
0
1
0
1
1
0
X
0
1
1
0
1
0
X
X
Z CLR LD
1 1 1
1 1 1
0 1 1
0 0 X
1 1 1
0 1 0
1 0 X
X X X
0 1 0
0 1 0
1 1 1
1 0 X
0 1 1
1 1 1
X X X
X X X
EN
1
1
1
X
1
X
X
X
X
X
1
X
1
1
X
X
C
X
X
X
X
X
0
X
X
1
1
X
X
X
X
X
X
B
X
X
X
X
X
1
X
X
0
0
X
X
X
X
X
X
A
X
X
X
X
X
0
X
X
0
1
X
X
X
X
X
X
CLR signal dominates LD which dominates Count
ECE C03 Lecture 15
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Implementation FSM With Counters
Excess 3 Converter
.i 5
.i 5
Espresso Input File
.o 7
.o 7
.ilb res x q2 q1 q0
.ilb res x q2 q1 q0
.ob z clr ld en c b a
.ob z clr ld en c b a
.p 17
.p 10
1---- -0----0-001 0101101
00000 1111---0-01 1000000
00001 1111---11-0 1000000
00010 0111--0-0-0 0101100
00011 00-----000- 1010000
00100 0111---0--0 0010000
00101 110-011
0-10- 0101011
00110 10------11- 1000000
00111 -------11-- 0010000
01000 010-100
-1-1- 1010000
01001 010-101
.e
01010 1111--Espresso Output File
01011 10----01100 1111--01101 0111--01110 ------01111 ------ECE C03 Lecture 15
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.e
Implementing FSM with Counters
Excess 3 Converter Schematic
CLK
1
0
1
0
7
P
10
163
T
RCO15
2
CLK
6 D
QD 11
5 C
QC 12
4 B
QB 13
3 A
14
QA
9 LOAD
excess 3 PLA
X
Reset
X
Q2
Q1
Q0
Z
\CLR
\LD
EN
C
B
A
1
Z
D Q
C Q
CLR
Synchronous Output Register
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FSM Design with FPGAs
Programmable Logic Devices = PLD
PALs, PLAs = 10 - 100 Gate Equivalents
Field Programmable Gate Arrays = FPGAs
• Altera MAX Family
• Actel Programmable Gate Array
• Xilinx Logical Cell Array
100 - 1000(s) of Gate Equivalents!
ECE C03 Lecture 15
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Xilinx Logic Cell Arrays
CMOS Static RAM Technology: programmable on the fly!
All personality elements connected into serial shift register
Shift in string of 1's and 0's on power up
IOB
IOB
CLB
IOB
CLB
IOB
Wiring Channels
CLB
IOB
General Chip Architecture:
• Logic Blocks (CLBs)
• IO Blocks (IOBs)
• Wiring Channels
IOB
IOB
IOB
ECE C03 Lecture 15
CLB
23
Xilinx LCA Architecture
Inputs:
Tri-state enable
bit to output
input, output clocks
Outputs:
input bit
Internal FFs for
input & output paths
Program Controlled Options
OUT
INV
TS
INV
OUTPUT
SOURCE
Pull-up used with
unused IOBs
PASSIVE
PULLUP
Vcc
Enable
Output
PAD
MUX
Out
D
Q
Output
Buffer
R
Direct In
Fast/Slow outputs
5 ns vs. 30 ns rise
SLEW
RATE
Q
D
Registered In
TTL or CMOS
Input Buffer
R
Clocks
ECE C03 Lecture 15
Global Reset
24
Xilinx LCA Architecture
Configurable Logic Block: CLB
2 FFs
Reset
DIN
Mux
Any function of
5 Variables
Global Reset
Q1
A
B
C
D
E
Clock, Clock Enb
Independent DIN
F
Mux
X
Mux
Y
Combinational
Function
Generator
Q2
G
Mux
Clock
D RD
Q
CE
Mux
D RD
Q
CE
Clock
Enable
ECE C03 Lecture 15
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Xilinx CLB Function Generator
CLB Function Generator
A
B
Q1
A
B
Mux
C
D
E
F
Mux
C Mux
D
E
Q2
Q1
Function
of 5
Variables
Mux
Function
of 4
Variables
F
Function
of 4
Variables
G
Mux
Q2
G
Q1
A
B
Any function of 5 variables
C
D
E
ECE C03 Lecture 15
Mux
Mux
Mux
Q2
Two Independent Functions
of 4 variables each 26
Xilinx CLB Function Generator
Q1
A
B
Mux
C
Mux
Function
of 4
Variables
D
Certain Limited
Functions of 6 Variables
E
F
Q2
Mux
Q1
A
B
C
G
Mux
Mux
Function
of 4
Variables
D
Q2
ECE C03 Lecture 15
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Xilinx Interconnect Architecture
Interconnect
Direct
Connections
DI CE A
B
X
C CLB0
K
Y
E D R
Direct Connections
Global Long Line
Horizontal
Long Line
Switching
Matrix
Horizontal/Vertical
Long Lines
Switching Matrix
Connections
DI CE A
B
X
C CLB1
K
Y
E D R
Horizontal
Long Line
DI CE A
B
X
C CLB3
K
Y
E D R
DI CE A
B
X
C CLB2
K
Y
E D R
Vertical
Long Lines
ECE C03 Lecture 15
Global
Long Line
28
Implementing FSM with Xilinx LCA
Implementing the BCD to Excess 3 FSM
Q2+ = Q2 • Q0 + Q2 • Q0
Q1+ = X • Q2 • Q1 • Q0 + X • Q2 • Q0 + X • Q2 • Q0 + Q1 • Q0
Q0+ = Q0
Z = Z • Q1 + X • Q1
No function more complex than 4 variables
4 FFs implies 2 CLBs
Synchronous Mealy Machine
Global Reset to be used
Place Q2+, Q0+ in once CLB
Q1, Z in second CLB
maximize use of direct & general purpose interconnections
ECE C03 Lecture 15
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Implementing FSM with Xilinx LCA
Implementing the BCD to Excess 3 FSM
Clk
Clk
X
CE
CE
A
CE
DI
B
X
Q2
Q0
FG
DI
Q2
B
C
C
Y
K
Q0
Q0
FG
E
K
X
Q2
Q1
Q0
X
Q1
A
X
FG
Y
Q1
Z
FG
E
D
RES
D
RES
CLB2
CLB1
ECE C03 Lecture 15
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Summary
•
•
•
•
Mapping FSM to random logic
Mapping FSM to ROMS
Mapping FSM to PLAs
Mapping FSM to Programmable Logic Devices
(Xilinx)
• NEXT LECTURE: VHDL Language
• READING: Dewey 11.2, 11.3, 11.4, 11.5, 11.6,
12.2, 12.2
ECE C03 Lecture 15
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