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Virtex-6 Clocking Resources
Basic FPGA Architecture
Xilinx Training
Objectives
After completing this module, you will be able to:
Detail the clocking resources available in the Virtex-6 FPGA
Specify the resources available in the Clock Management Tile
(CMT)
Describe the basics of the PLL capabilities
Virtex-6 Clock Management
Global clock buffers
– High fanout clock distribution buffer
Regional clock distribution (low-skew)
I/O clock routing
– Each clock region is 40 CLBs high and
spans half the device
Clock
Buffers
Clock regions
MMCM
MMCM
Clock management tile (CMT)
– Two PLL-based Mixed-Mode Clock
Managers (MMCMs) in each Clock Management
Tile (CMT)
– Up to nine CMTs per device
– Performs frequency synthesis, clock
de-skew, and jitter-filtering
– High input frequency range (10-800 MHz)
Simple design creation through the
Clocking Wizard
Clock Wizard
Automatic HDL
code
MMCM Features
8 independently programmable
clock outputs (O0-O6 and CLKFBOUT)
MMCM_ADV
CLKIN1 CLKOUT<6:0>
CLKFBIN CLKFBOUT
– O0 to O3 and CLKFBOUT offer
complementary outputs
Additional MMCM_ADV features
– Clock input switching
– Phase shift port
MMCM_BASE
CLKIN1
CLKOUT<6:0>
CLKFBOUT
CLKFBIN
RST
CLKIN2
CLKINSEL
DRP
Phase Shift
RST
LOCKED
LOCKED
– Dynamic Reconfiguration Port (DRP)
– LOCK circuit enhanced to eliminate
possibility of false LOCK
Both are easily customized with the
Architecture Wizard
Each MMCM can be invoked with either
the MMCM_BASE or MMCM_ADV
primitive. SW takes care of unused
ports on MMCM_BASE.
MMCM able to implement both
DCM and PLL functionality
Die View
IO
Columns
Clock
Regions
BUFR
Clock
Spine and
Column
MMCM
Tiles
BUFIO
(Single or
Multi
Region)
HROWs
BUFH
Clocks in
“Leaf”
Region
BUFG in
Center of
Device
BUFH Mux
Areas
Virtex-6 FPGA Clock Distribution
Larger clock region
– 40 CLBs high, 40 I/Os high
– Same size as I/O bank
– Half width of device
– 6-18 regions per device
Resources per clock
region
– 12 global clock networks
• Driven by BUFH
– 6 regional clock networks
• Driven by BUFR
– 8 I/O clock networks per
I/O column
C
L
B
20
I
O
B
20
C
L
B
20
M
M
C
M
C
I
O L
B B
20 20
I
O
B
20
C
L
B
20
M
M
C
M
I
O
B
20
Global Clocking
32 BUFGs reside in the center of the device
Driven by 8 global clock pins
– There are also four clock-capable I/O pins per
I/O bank
• Four differential or single-ended
• Global clock pins are not the only clock input
resource
BUFGs can be driven by
–
–
–
–
–
–
–
Global clock inputs
Clock-capable inputs (inner I/O columns only)
MMCM outputs
Other BUFG
Interconnect
BUFR
GTX (recovered clock from GTX)
BUFG outputs can drive the vertical global
clock spine
BUFGCTRL component implements
– Glitch-free clock switching between two sources
– Clock enable for disabling clocks
BUFGCTRL
IGNORE1
CE1
S1
I1
O
I0
S0
CE0
IGNORE0
Horizontal Clocking
BUFH
12 BUFHs per clock region
– You should not have to instantiate this
BUFH drives logic via horizontal global clock lines
– BUFHs on left and right of vertical spine can
be driven by the same CCIO or MMCM output
Driven by…
– MMCM in the same region
– BUFG via vertical clock spine
– Clock-capable inputs in same horizontal row
– Interconnect
Provides control of clocks routed into regions
– Power saving by turning off or gating clocks to
specific regions
– Isolating logic into regions may require an Area
Constraint
BUFHCE
CE
I
O I
O
Regional Clocking
Up to 4 BUFRs per clock region (varies
by density)
– 2 per I/O bank
BUFR
CLR
CE
Driven by…
–
–
–
–
Clock-capable inputs
Interconnect
GTX
MMCM high-performance clocks
Can drive…
–
–
–
–
Logic
IO logic
MMCM
BUFG
For medium- and high-performance
clocks driving 1-3 regions (one above,
self, and one below)
BUFR frequency can be divided by 1…8
I
÷
O
I/O Clocking
2 single-region BUFIOs and 2 multiregion
BUFIOs in each I/O bank
Driven by…
– Clock-capable inputs in the same I/O bank
– MMCM outputs via high-performance paths
Can drive…
– I/O logic in the same and adjacent I/O
banks
– BUFIO can drive logic resources only in the
same I/O column
Intended for clocking high-speed I/O
logic
BUFIO
I
O
Source-Synchronous Interfaces
I/O and regional clock networks combined with
ISERDES/OSERDES provide powerful tools for creating source
synchronous interfaces
BUFR is set to ÷N if interface is SDR, or ÷(N/2) if DDR
– N can be 2 to 8 in SDR, and 2 to 10 in DDR
Data
ISERDES
IO
CLK
CCIO
CLK
BUFIO
BUFR
Conventional I/O (IO)
N
FPGA Fabric
CLKDIV
Clock-Capable I/O (CCIO)
I/O Clock Buffer (BUFIO)
Regional Clock Buffer (BUFR)
Performance Path Routing
4 performance paths driving
each inner/outer left/right IO column
Driven by…
– MMCM outputs O0-O3
IO
IO
IO
MMCM
Can drive…
– BUFIO
– BUFR
– GTX
Powered by a regulated supply within
each MMCM
– This isolates the clocks from noise on
Vccint
MMCM
– Cleanest path from MMCM to I/O
columns
– Lower jitter than any other routing
Software automatically places critical signals onto performance path
routing, so don’t worry about controlling this route
IO
GTX
Global Clocking Features
Global Clock Inputs
(IBUFG or IBUFGDS)
Flexibility
Performance
 8 total
– 8 differential (16 pins) or
– 8 single-ended (8 pins)
Global Clock Multiplexers
(BUFGCTRL)
 32 total
 Drive the global clock
networks
 Optional clock enable
 Guaranteed glitchless clock
switching
 Up to 800 MHz
 Differential for maximum performance
 High fanout (access to all clock loads in the FPGA)
 Low skew
 Short clock insertion delay
I/O and Regional Clocking
Clock-Capable I/Os
Flexibility
Performance
I/O Clocks
Regional Clocks
 Exist in all I/O columns
 4 CCIOs per I/O bank
– 4 differential (8 pins) or
– 4 single-ended (4 pins)
 Adjacent to HCLK row
– 2 CCIOs above and
below
 Exist in all I/O
columns
 4 BUFIOs per I/O
bank
 Up to 8 I/O clock
networks per I/O
bank
 Some clocks are
local only; some
can drive
neighboring
banks
 Exist in all I/O
columns
 2 BUFRs per I/O
bank
 6 regional clock
networks per region
 Span up to three
regions (one above
and below)
 Clock divider range
from 1 to 8
 800-MHz differential
 800-MHz
differential
 500 MHz
Virtex-6 Clock Network Summary
Clock regions are 40
CLBs tall
Clock regions
span one half the die
Clock regions
match I/O banks
40 I/Os per bank
Four differential or
single-ended clock
capable inputs
2 BUFRs per I/O bank
2 single region BUFIOs
2 multi-region BUFIOs
12 GCLKs (via BUFH)
per region
MMCM Features
Up to 9 CMTs per device
– 2 MMCMs per CMT
Two software primitives
MMCM_ADV
– MMCM_BASE has only the basic
ports
CLKIN1 CLKOUT<6:0>
CLKFBIN
CLKFBOUT
CLKIN2
CLKINSEL
– MMCM_ADV provides access to all
ports
8 independently programmable
clock outputs
– O0 to O6 plus CLKFBOUT
– O0 to O3 and CLKFBOUT true and
complement outputs
Additional MMCM_ADV features
– Clock input switching
– Phase shift port
DRP
Phase Shift
MMCM_BASE
CLKIN1
CLKOUT<6:0>
CLKFBOUT
CLKFBIN
RST
LOCKED
RST
LOCKED
MMCM Internals
Phase / frequency detector
compares CLKIN with CLKFB
– Accepts up to 650-MHz inputs
– Adjusts the charge pump output
voltage higher or lower
– Charge pump controls the VCO
frequency
Routing
CLKIN1
CLKIN2
– Fout = Fin * M / (D*O)
– One M and one D value per
MMCM
– Each MMCM output can have its
own O value
– M: 1…64; D: 1…80; O: 1…128
Lock
Detect
D
PFD
CP
Lock
LF
VCO
9
O0
O1
CLKFB
Many different output frequencies
can be generated
Clock
Switch
Stop
Detect
HOLD
CLKINSTOPPED
CLKFBSTOPPED
O2
O3
O4
O5
O6
M
CLKFBOUT
Extra MMCM Features
Fractional counters
– Ability to configure O0 and CLKFBOUT
as counters with 1/8th granularity (e.g.
2.125, 2.250, 2.375, etc.)
O0
O1
O2
O3
O4
– O5 output is disabled when using this
feature
O5
O6
CLKFBOUT
– Enables many more frequencies to be
synthesized
Two methods of shifting phase
– Static phase shift using time-shifted
VCO outputs
– Dynamic phase shift using the PS port
to change the phase on the fly in
increments of 1/56 of VCO period
VCO
Outputs
0
45
90
135
180
225
270
315
Additional MMCM Signals
Complement outputs
– O0-O3 of every MMCM have
both true and complement
outputs
Routing
CLKIN1
CLKIN2
Clock
Switch
Lock
Detect
D
PFD
CP
Lock
LF
VCO
9
O0
O1
CLKFB
– Provide 180 degree phase shift
LOCKED
Stop
Detect
HOLD
O2
CLKINSTOPPED
CLKFBSTOPPED
– Signal showing that the MMCM has
locked on to the input frequency
O3
O4
O5
O6
M
CLKFBOUT
CLKINSTOPPED/FBSTOPPED
– Status signals indicating that the input or feedback clocks have stopped
running
PWRDWN (not shown)
– Disable / Enable signal to the regulated supply of each MMCM
• Unused MMCMs draw power
MMCM Connectivity
Many possible inputs to each MMCM
– CCIO from inner I/O
columns
MMCM
– Global clock inputs
– BUFG
– GTX clocks
Clock capable IO
(Inner I/O Columns)
CLKIN1
CLKIN2
CLKFBIN
Clock capable IO
(Inner I/O Columns)
GTX clocks
MMCM outputs drive
– BUFG
HROW clock
HROW clock
To BUFG
To BUFG
From BUFG
Global Clock inputs
– Performance paths to
BUFIO and BUFR
(not shown)
To BUFG
To BUFG
– BUFH in same region
Clock Deskew
Use a BUFG on CLKFBOUT if a
precise phase relationship
between input clock and output
clock is required
– Most flexible solution but requires two
global clock buffers
IBUFG
BUFG
CLKIN
CLKOUT0
CLKFBIN
BUFG
Remove the BUFG on CLKFBOUT
if there is no need for a precise
phase relationship
– Frequency synthesis or jitter filtering
only
CLKFBOUT
MMCM-to-MMCM Connection
IBUFG
MMCMs in the same CMT can be
connected without the need for a
global clock buffer
CLKIN
BUFG
CLKFBIN
CLKOUT1
– Output clock will not be aligned to input
clock
More clock frequencies can thus be
generated
CLKOUT0
To
Logic
CLKFBOUT
BUFG
CLKIN
CLKOUT0
CLKFBIN
CLKFBOUT
To
Logic
MMCM-to-MMCM Connection
MMCMs in the same CMT can be
connected without the need for a
global clock buffer
IBUFG
CLKIN
CLKOUT0
BUFG
CLKFBIN
CLKOUT1
– Output of first MMCM connected to
CLKIN of second MMCM
BUFG
Enables more phase-aligned
clock frequencies to be
generated
To
Logic
CLKFBOUT
– BUFG inserted from CLKFBOUT to
CLKFBIN of the first MMCM to align
output clock with input clock
– CLKFBOUT of first MMCM can also
drive logic
To
Logic
BUFG
CLKIN
CLKOUT0
CLKFBIN
CLKFBOUT
To
Logic
Example
Requirement
– 33.3-MHz external oscillator controls
• 533-MHz data being generated by I/O logic
(BUFIO)
• Large amount of logic at 66 MHz (BUFG)
• Small design at 54 MHz (BUFH)
MMCM
CCIO
– Phase relationship between input clock and output
clock is irrelevant
CLKIN1
BUFH
CLKOUT0
BUFIO
CLKOUT1 Performance
Path
BUFG
CLKOUT2
Solution
– MMCM values
• M=16, D=1, O0=9.875, O1=1, O2=8
– Generates
• 54 MHz on clkout0
 O0 set to 9.875 using fractional counter
• 533 MHz on clkout1
• 66 MHz on clkout2
CLKFBIN
CLKFBOUT
Summary
Clock regions = 40 CLBs, 40 IOBs in height
– One or two I/O columns per region
32 global clock buffers (differential)
– 8 global clock input pins (differential)
– 12 global clocks per region
4 BUFIOs per I/O bank (differential)
– 2 can drive adjacent I/O banks, others are local only
2 BUFRs per I/O bank
– 6 regional clock networks
– Can drive adjacent clock regions
The Clock Management Tile (CMT) has two Mixed-Mode Clock
Managers (MMCMs)
– Each MMCM includes a PLL
– Jitter filtering and frequency synthesis capabilities
Where Can I Learn More?
User Guides
– Virtex-6 FPGA Clocking Resources User Guide
• Describes the complete clocking structures
Xilinx Education Services courses
– www.xilinx.com/training
• Designing with the Virtex-6 and Spartan-6 Families course
• Xilinx tools and architecture courses
• Hardware description language courses
• Basic FPGA architecture, Basic HDL Coding Techniques, and other Free
videos!
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