Transcript Digital Design

Introduction
• A digital circuit design is just an idea, perhaps drawn on
paper
• We eventually need to implement the circuit on a physical
device
– How do we get from (a) to (b)?
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IC
(a) Digital circuit
design
(b) Physical
implementation
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Manufactured IC Technologies
• We can manufacture our own IC
– Months of time and millions of dollars
– (1) Full-custom or (2) semicustom
• (1) Full-custom IC
– We make a full custom layout
• Using CAD tools
• Layout describes the location and size of
every transistor and wire
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Custom
layout
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– A fab (fabrication plant) builds IC for layout
– Hard!
• Fab setup costs ("non-recurring engineering",
or NRE, costs) high
• Error prone (several "respins")
• Fairly uncommon
Fab
months
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IC
– Reserved for special ICs that demand the very
best performance or the very smallest
size/power
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Manufactured IC Technologies – Gate Array ASIC
• (2) Semicustom IC
– "Application-specific IC" (ASIC)
– (a) Gate array or (b) standard
cell
• (2a) Gate array
– Series of gates already layed
out on chip
– We just wire them together
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(b)
(a)
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• Using CAD tools
s
– Vs. full-custom
• Cheaper and quicker to design
• But worse performance, size,
power
(d)
(c)
IC
Fab
weeks
(just wiring)
a
– Very popular
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Manufactured IC Technologies – Gate Array ASIC
• (2a) Gate array
– Example: Mapping a half-adder
to a gate array
Half-adder equations:
a
b
ab
a'b
s = a'b + ab'
co = ab
co
ab'
s
Gate array
a
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Manufactured IC Technologies – Standard Cell ASIC
• (2) Semicustom IC
– "Application-specific IC" (ASIC)
– (a) Gate array or (b) standard
cell
• (2b) Standard cell
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– Pre-layed-out "cells" exist in
s
library, not on chip
(a)
– Designer instantiates cells into
pre-defined rows, and connects
– Vs. gate array
• Better performance/power/size
• A bit harder to design
– Vs. full custom
• Not as good of circuit, but still
far easier to design
(b)
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Cell library
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cell row
cell row
cell row
(d)
(c)
IC
Fab
1-3 months
(cells and wiring)
a
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Manufactured IC Technologies – Standard Cell ASIC
• (2b) Standard cell
– Example: Mapping a half-adder
to standard cells
a
b
co = ab
s = a'b + ab'
ab
co
s
a'b
cell row
ab'
cell row
a
b
ab
a'b
co
ab'
cell row
a
s
Notice fewer gates and shorter wires
for standard cells versus gate array,
but at cost of more design effort
Gate array
a
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Programmable IC Technology – FPGA
• Manufactured IC technologies require weeks to
months to fabricate
– And have large (hundred thousand to million dollar)
initial costs
• Programmable ICs are pre-manufactured
– Can implement circuit today
– Just download bits into device
– Slower/bigger/more-power than manufactured ICs
• But get it today, and no fabrication costs
• Popular programmable IC – FPGA
– "Field-programmable gate array"
• Developed late 1980s
• Though no "gate array" inside
– Named when gate arrays were very popular in the 1980s
• Programmable in seconds
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FPGA Internals: Lookup Tables (LUTs)
• Basic idea: Memory can implement combinational logic
– e.g., 2-address memory can implement 2-input logic
– 1-bit wide memory – 1 function; 2-bits wide – 2 functions
• Such memory in FPGA known as Lookup Table (LUT)
F = x'y' + xy
4x1 Mem.
x
0
0
1
1
y
0
1
0
1
F
1
0
0
1
1
x
y
rd
a1
a0
4x1 Mem.
1
0
1
2
3
1
0
0
1
x=0
D
y=0
rd
a1
a0
0
1
2
3
(b )
x
1
0
0
1
D
(c)
a
4x2 Mem.
y
F G
0 0
1 0
0 1
0 0
1 0
0 1
1 1
1 0
1
x
y
rd 0 10
1 00
2 01
3 10
a1
a0 D1 D0
F=1
F
(a )
F = x'y' + xy
G = xy'
(d )
a
a
F G
(e ) a
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FPGA Internals: Lookup Tables (LUTs)
• Example: Seat-belt warning
light (again)
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(a)
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(c)
8x1 Mem.
0
0
1
0
2
0
3
0
a2
0
a1 4
0
a0 5
6
1
7
0
IC
(b)
k
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p
0
s
0
w
0
0
0
0
0
1
1
1
0
1
0
0
0
1
1
0
0
0
1
0
0
1
1
1
1
0
1
1
0
a
Programming
(seconds)
a
Fab
1-3 months
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FPGA Internals: Lookup Tables (LUTs)
• Lookup tables become inefficient for more inputs
– 3 inputs  only 8 words
– 8 inputs  256 words;
16 inputs  65,536 words!
• FPGAs thus have numerous small (3, 4, 5, or even 6-input) LUTs
– If circuit has more inputs, must partition circuit among LUTs
– Example: Extended seat-belt warning light system:
Sub-circuits have only 3-inputs each
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d
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3 inputs
1 output
x=kps'
(a)
5-input circuit, but 3input LUTs available
3 inputs
1 output
w=x+t+d
(b)
a
w
8x1 Mem.
0
0
1
0
2
0
3
0
a2
0
a1 4
0
a0 5
6
1
7
0
x
D
D
t
d
Partition circuit into
3-input sub-circuits
8x1 Mem.
0
0
1
1
2
1
3
1
a2
1
a1 4
1
a0 5
6
1
7
1
(c)
w
Map
to 3-input LUTs
a
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FPGA Internals: Lookup Tables (LUTs)
• Partitioning among smaller LUTs is more size efficient
– Example: 9-input circuit
a
b
c
d
e
f
g
h
i
F
(a)
Original 9-input circuit
a
b
c
d
e
f
g
h
i
512x1 Mem.
3x1
3x1
3x1
F
8x1 Mem.
3x1
(b)
Partitioned among
3x1 LUTs
(c)
Requires only 4
3-input LUTs
(8x1 memories) –
much smaller than
a 9-input LUT
(512x1 memory)
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FPGA Internals: Lookup Tables (LUTs)
• LUT typically has 2 (or more) outputs, not just one
• Example: Partitioning a circuit among 3-input 2-output lookup tables
a
b
c
d
8x2 Mem.
0
F
e
a
b
c
( a)
1
2
3
t
d
a
b
c
1
2
F
3
e
1
2
3
a2
a1 4
a0 5
6
7
00
00
00
00
00
00
00
01
0
1
2
3
a2
a1 4
a0 5
6
7
D1 D0
00
10
00
10
00
10
10
10
D1 D0
t
(b)
(Note: decomposed one 4input AND input two
smaller ANDs to enable
partitioning into 3-input
sub-circuits)
8x2 Mem.
a
d
e
F
(c)
First column unused;
second column
implements AND
a
Second column unused;
first column implements
AND/OR sub-circuit
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FPGA Internals: Lookup Tables (LUTs)
• Example: Mapping a 2x4 decoder to 3-input 2-output LUTs
d0
d1
d2
d3
0
i1
i0
8x2 Mem.
0 10
1 01
2 00
3 00
a2
a1 4 00
a0 5 00
6 00
7 00
0
8x2 Mem.
0 00
1 00
2 10
3 01
a2
a1 4 00
a0 5 00
6 00
7 00
D1 D0
i1
i0
a
(a)
d0 d1
D1 D0
a
(b)
d2 d3
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FPGA Internals: Switch Matrices
• Previous slides had hardwired connections between LUTs
• Instead, want to program the connections too
• Use switch matrices (also known as programmable interconnect)
– Simple mux-based version – each output can be set to any of the four inputs
just by programming its 2-bit configuration memory
Switch matrix
2-bit
memory
FPGA (partial)
P0
P1
P2
P3
8x2 Mem.
0 00
1 00
2 00
3 00
a2
a1 4 00
a0 5 00
6 00
7 00
D1 D0
8x2 Mem.
0 00
1 00
2 00
3 00
a2
a1 4 00
a0 5 00
6 00
7 00
o0
o1
m0
m1
m2
m3
Switch
matrix
P6
P7
s1 s0
i0
o0
i1 4x1
i2 mux d
i3
m0
m1
m2
m3
2-bit
memory
D1 D0
s1 s0
i0
o1
i1 4x1
i2 mux d
i3
P8
P9
P4
P5
(a)
(b)
a
a
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FPGA Internals: Switch Matrices
• Mapping a 2x4 decoder onto an FPGA with a switch matrix
0
0
i1
i0
8x2 Mem.
8x2 Mem.
0
1
2
3
a2
a1 4
a0 5
6
7
0
1
2
3
a2
a1 4
a0 5
6
7
10
01
00
00
00
00
00
00
D1 D0
10 o0
m0 11 o1
m1
m2
m3
Switch
matrix
00
00
10
01
00
00
00
00
10
d3
d2
s1 s0
i0
o0
i1 4x1
d
i2 mux
i3
m0
m1
m2
m3
11
D1 D0
s1 s0
i0
o1
i1 4x1
d
i2 mux
i3
d1
d0
i1
i0
These bits establish the desired connections
Switch matrix
FPGA (partial)
(b)
(a)
a
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FPGA Internals: Switch Matrices
• Mapping the extended seatbelt warning light onto an
FPGA with a switch matrix
0
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D1 D0
x
00 o0
m0 10 o1
m1
m2
m3
Switch
matrix
w
t
d
Switch matrix
FPGA (partial)
8x2 Mem.
0 00
1 01
2 01
3 01
a2
a1 4 00
a0 5 00
6 00
7 00
x
s
– Recall earlier example (let's ignore d input for simplicity)
8x2 Mem.
0 00
1 00
2 00
3 00
a2
a1 4 00
a0 5 00
6 01
7 00
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w
s1 s0
i0
o0
i1 4x1
d
i2 mux
i3
m0
m1
m2
m3
10
D1 D0
s1 s0
i0
o1
i1 4x1
d
i2 mux
i3
t
0
(a)
(b)
a
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FPGA Internals: Configurable Logic Blocks (CLBs)
• LUTs can only
implement
combinational logic
• Need flip-flops to
implement sequential
logic
• Add flip-flop to each
LUT output
– Configurable Logic
Block (CLB)
• LUT + flip-flops
– Can program CLB
outputs to come
from flip-flops or
from LUTs directly
FPGA
CLB
P0
P1
P2
P3
CLB output
flip-flop
1-bit
CLB
output
configuration
memory
8x2 Mem.
8x2 Mem.
0
1
2
3
a2
a1 4
a0 5
6
7
0
1
2
3
a2
a1 4
a0 5
6
7
00
00
00
00
00
00
00
00
D1
0
CLB
10
2x1 0
D0
00 o0
m0 00 o1
m1
m2
m3
Switch
matrix
10
D1
0
2x1
10
2x1 0
00
00
00
00
00
00
00
00
D0
10
2x1
P6
P7
P8
P9
P4
P5
a
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FPGA Internals: Sequential Circuit Example using CLBs
a
b
c
FPGA
d
CLB
w
x
y
0
0
a
b
z
(a)
Left lookup table
D1
8x2 Mem.
8x2 Mem.
0
1
2
3
a2
4
a1
a0 5
6
7
0
1
2
3
a2
4
a1
a0 5
6
7
11
10
01
00
00
00
00
00
D1
a2
a1
a0
0
a
b
0
0
0
1
1
0
0
1
1
0
0
1
0
0
1
0
1
1
0
0
CLB
D0
D0
10 o0
m0 11 o1
m1
m2
m3
Switch
matrix
00
01
10
11
00
00
00
00
D1
D0
10
10
w=a' x=b'
below unused
(b)
1
10
2 x1 1
10
1
2 x1
2 x1 1
2 x1
z
y
x
w
c
d
(c)
a
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FPGA Internals: Overall Architecture
• Consists of hundreds or thousands of CLBs and switch
matrices (SMs) arranged in regular pattern on a chip
Connections for just one
CLB shown, but all
CLBs are obviously
connected to channels
Represents channel with
tens of wires
CLB
CLB
SM
CLB
SM
CLB
SM
CLB
CLB
CLB
SM
CLB
CLB
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FPGA Internals: Programming an FPGA
FPGA
• All configuration
memory bits are
connected as
one big shift
register
Pin
Pclk
0
0
a
b
(a)
– Known as scan
chain
• Shift in "bit file"
of desired circuit
1
(b)
Pin
Pclk
a
CLB
8x2 Mem.
0 11
1 10
2 01
3 01
a2
4 00
a1
a0 5 00
6 00
7 00
D1
D0
2 x1 1
2x1
CLB
8x2 Mem.
0 01
1 00
2 11
3 10
a2
4 00
a1
a0 5 00
6 00
7 00
10 o0
m0 11 o1
m1
m2
m3
Switch
matrix
1
D1
D0
2 x1 1
2 x1
z
y
x
w
c
d
Conceptual view of configuration bit scan chain
is that of a 40-bit shift register
(c) Bit file contents for desired circuit: 1101011000000000111101010011010000000011
This isn't wrong. Although the bits appear as "10" above, note that the scan
chain passes through those bits from right to left – so "01" is correct here.
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