Transcript Xilinx Template (light) rev

Basic FPGA Architecture
(Spartan-6)
Slice and I/O Resources
Objectives
After completing this module, you will be able to:
Describe the CLB and slice resources available in Spartan-6
FPGAs
Describe flip-flop functionality
Anticipate building proper HDL code for Spartan-6 FPGAs
Spartan-6 CLB
COUT
CLB contains two slices
Connected to the
switch matrix for
resources
Switch
Matrix
routing to other FPGA
Carry chain runs
vertically in a column
from one slice to the
one above
– The Spartan-6 FPGA has a carry chain for the
Slice0 carry chain only
CIN
Routing
Spartan-6 FPGAs use a diagonally symmetric
interconnect pattern
– A rich set of programmable interconnections exist
between one switch matrix and the switch matrices
nearby
– Many CLBs can be reached with only a few “hops”
• A hop is a connection through an active connection
point
With the exception of the carry chain, all slice
connections are done through the switch
matrix
The mapping of logical connections to these
physical routing resources is guided by the
use of timing constraints
CLB
Direct
1 Hop
2 Hops
3 Hops
6-Input LUT with Dual Output
6-input LUT can be two
5-input LUTs with
common inputs
– Minimal speed impact to
a 6-input LUT
– One or two outputs
– Any function of six
variables or two
independent functions
of five variables
FPGA Slice Resources
Four six-input Look Up Tables
(LUT)
Four flip-flop/latches
LUT/RAM/SRL
Four additional flip-flops
– These are the new flip-flops
Carry chain
LUT/RAM/SRL
– This is supported on four of the
eight flip-flops
Wide multiplexers
The implementation tools will
choose how best to pack your
design
LUT/RAM/SRL
LUT/RAM/SRL
01
Wide Multiplexers
Each F7MUX combines the
outputs of two LUTs together
– This can make a 7-input function
or an 8-1 multiplexer
The F8MUX combines the
outputs of the two F7MUXes
LUT/RAM/SRL
LUT/RAM/SRL
– This can make an 8-input function
or a 16-1 multiplexer
MUX output can bypass the
flip-flop/latch
These muxes save LUTs and
improve performance
LUT/RAM/SRL
LUT/RAM/SRL
01
Carry Logic
Carry logic can implement fast
arithmetic addition and
subtraction
LUT/RAM/SRL
– Carry out is propagated vertically
through the four LUTs in a slice
– The carry chain propagates from
one slice to the slice in the same
column in the CLB above (upward)
LUT/RAM/SRL
• This requires bit ordering
Carry look-ahead
LUT/RAM/SRL
– Combinatorial carry look-ahead
over the four LUTs in a slice
– Implements faster carry cascading
from slice to slice
LUT/RAM/SRL
01
Flip-Flops and Latches
Each slice has four flip-flop/latches
(FF/L)
FF
FF/L
– Can be configured as either flip-flops or
latches
– The D input can come from the O6 LUT
output, the carry chain, the wide
multiplexer, or the AX/BX/CX/DX slice
input
Each slice also has four flip-flops (FF)
LUT/RAM/SRL
LUT/RAM/SRL
– D input can come from O5 output or the
AX/BX/CX/DX input
• These don’t have access to the carry chain,
wide multiplexers, or the slice inputs
LUT/RAM/SRL
• Only the O5 input is available in the
Spartan-6 FPGA
Note…if any of the FF/L are configured
as latches, the four FFs are not available
LUT/RAM/SRL
01
CLB Control Signals
D
CE
– This is referred to as the “control set” of the flip-flops
– CE and SR are active high
– CLK can be inverted at the slice boundary
– All four flip-flop/latches are configured the same
– All four flip-flops are configured the same
– SR will cause the flip-flop to be set to the state
specified by the SRVAL attribute
CK
D Q
CE
CE
CK
CK
SR
SRSR
●●●
 Set/Reset (SR) signal can be configured as
synchronous or asynchronous
Q
AFF/LATCH
DFF
D
Q
CE
CK
SR
●●●
 All flip-flops and flip-flop/latches share the same
CLK, SR, and CE signals
AFF
DFF/LATCH
D
Q
CE
CK
SR
SLICEM as Distributed RAM
Uses the same storage that is used
for the look-up table function
Single
Port
32x2
32x4
32x6
32x8
64x1
64x2
64x3
64x4
128x1
128x2
256x1
Dual
Port
32x2D
32x4D
64x1D
64x2D
128x1D
Simple
Dual Port
32x6SDP
64x3SDP
Quad
Port
32x2Q
64x1Q
Synchronous write, asynchronous
read
– Can be converted to synchronous read
using the flip-flops available in the slice
Various configurations
– Single port
• One LUT6 = 64x1 or 32x2 RAM
• Cascadable up to 256x1 RAM
– Dual port (D)
• 1 read / write port + 1 read-only port
– Simple dual port (SDP)
• 1 write-only port + 1 read-only port
Each port has independent
address inputs
– Quad-port (Q)
• 1 read / write port + 3 read-only ports
SLICEM as 32-bit Shift Register
Versatile SRL-type shift registers
–
–
–
–
–
Variable-length shift register
Synchronous FIFOs
Content-Addressable Memory (CAM)
D
Pattern generator
CLK
Compensate for delay / latency
Shift register length is determined
by the address
– Constant value giving fixed delay line
A
LUT
32-bit Shift register
32
5
MUX
Qn
– Dynamic addressing for elastic buffer
SRL is non-loadable and has no
reset
SRL Configurations
in one Slice (4 LUTs)
16x1, 16x2, 16x4, 16x6, 16x8
32x1, 32x2, 32x3, 32x4
Cascade these up to 128x1 shift
register in one slice
– Effectively, 32 registers with one LUT
Q 31
64x1, 64x2
96x1
128x1
Shift Register LUT Example
20 Cycles
64
Operation A
Operation B
8 Cycles
12 Cycles
Operation C
Operation D - NOP
3 Cycles
17 Cycles
64
Paths are Statically
Balanced
20 Cycles
Operation D - NOP must add 17 pipeline stages of 64 bits each
– 1,088 flip-flops (136 slices) or
– 64 SRLs (16 slices)
Three Types of Slices
Three types of slices
– SLICEM: Full slice (25%)
• LUT can be used for logic and
memory/SRL
• Has wide multiplexers and carry chain
– SLICEL: Logic and arithmetic only
(25%)
• LUT can only be used for logic
(not memory)
• Has wide multiplexers and carry chain
– SLICEX: Logic only (50%)
• LUT can only be used for logic (not
memory)
• No wide multiplexers or carry chain
Spartan-6 FPGA
SLICEX
SLICEX
or
SLICEM
SLICEL
I/O Bank Structure
– IOBs are grouped into banks
• 4 – 6 banks, depending on the density
BANK
BANK
– Every IOB contains registers for clocking data in
and out of the device
Spartan-6 FPGA
BANK
Spartan-6 I/Os are located on the periphery
• 30 ~ 83 I/O pins per banks
BANK
IOBs require compatible I/O standards to be
grouped into banks
• This is called the I/O Banking Rules
• Based on common VCCO, VREF
• More banks allows greater mixture of standards across
the chip
– Clocking resources are specific to each bank
• Global and/or regional clocking resources
I/O Versatility
Each I/O supports over 40+ voltage and protocol standards,
including
– LVCMOS
– LVDS, Bus LVDS
– LVPECL
– SSTL
– HSTL
– RSDS_25 (point-to-point)
Each pin can be input and output (including 3-state)
Each pin can be individually configured
– IODELAY, drive strength, input threshold, termination, weak pull-up or pulldown
– Based on the I/O Banking Rules (some standards not compatible within
the same bank)
I/O Electrical Resources
P and N pins can be configured as
singleended signals
…or as a differential pair
– Transmitter available only
in top and bottom banks (Bank0 and
Bank2)
• Receiver available in all banks
• Receiver termination available in all banks
Whether your pin is single-ended or
differential will affect your pin layout
Tx
P
Rx
LVDS
Termination
Tx
N
Rx
IOB Element
Input path
– Two DDR registers
Output path
– Two DDR registers
– Two 3-state enable
DDR registers
Separate clocks and
clock enables for I and O
Set and reset signals
are shared
I/O Logical Resources
– Master and slave
– Can operate independently or
be concatenated
Each IOLOGIC contains…
– IOSERDES
• Parallel to serial converter (serializer)
• Serial to parallel converter
(De-serializer)
– IODELAY
• Selectable fine-grained delay
– SDR and DDR resources
Interconnect to FPGA fabric
Two IOLOGIC blocks per I/O pair
Master IOLOGIC
IOSERDES
IODELAY
Slave
IOLOGIC
IOSERDES
IODELAY
Flip-Flop Details
Each flip-flop has four input signals
– D – data input
– CK – clock
– CE – clock enable (Active High)
– SR – async/sync set/reset (Active High)
• Either Set or Reset can be implemented (not both)
All eight flip-flops share the same control signals
– CK – clock
– CE – Clock Enable
– SR – Set/Reset
FF
D
CE
CK
Q
SR
Design Tips
FF1
Suggestions for faster and smaller designs
– Leverage the FPGAs Global Reset whenever possible
D
CE
CK
– Design synchronously
Q
SR
• Use synchronous Set/Reset whenever possible
• Don’t gate your clocks (use the CE, instead)
●●●
• Use the clock routing resources to minimize clock skew
FF8
– Use active-high CE and Set/Reset (no local inverter)
D
CE
CK
Q
SR
Software
Software intelligently packs logic
Design
FPGA
Slice
LUT
LUT
LUT
LUT
Related logic and flip-flops are coded
Software places the logic and flip-flop in the same
slice
Software packs slices for optimum performance
Control Signals
Different flip-flop configurations
– If coded registers do not map cleanly to the flip-flops, the software tools
will automatically implement the missing functionality by using LUT inputs
– Can increase overall LUT utilization, but can be helpful for fitting the
design
Case
CE active Low
Design
D
CE
CK
Q
FPGA
D
CE
Q
D
CK
Both Synchronous Set and
Reset are used
D
CK
Q
Sset
SReset
D
D
Sset
SReset
Software uses LUTs to map extra control functionality
SR
CK
Q
Control Set Reduction
Flip-flops with different control sets cannot be packed into the
same slice
Software can be instructed to reduce the number of control
sets by mapping control logic to LUT resources
– This results in higher LUT utilization, but a lower overall slice utilization
Design
Q
D
3 Slices
CK
CK
D
Q
CK
Sset
D
Q
D
Sset
D
CK
Q
D
SReset
D
CK
Q
Q
CK
SReset
1 Slice
D
FPGA
Using the Slice Resources
Three primary mechanisms for using FPGA resources
– Inference
• Describe the behavior of the desired circuit using Register Transfer
Language (RTL)
• The synthesis tool will analyze the described behavior and use the required
FPGA resources to implement the equivalent circuit
– Instantiation
• Create an instance of the FPGA resource using the name of the primitive and
manually connecting the ports and setting the attributes
– CORE Generator™ tool and Architecture Wizard
• The CORE Generator software and Architecture Wizard are graphical tools
that allow you to build and customize modules with specific functionality
• The resulting modules range from simple modules containing few FPGA
resources or highly complex Intellectual Property (IP) cores
Inference
All primary slice resources can be inferred by XST and
Synplify
– LUTs
• Most combinatorial functions will map to LUTs
– Flip-flops
• Coding style defines the behavior
– SRL
• Non-loadable, serial functionality
– Multiplexers
• Use a CASE statement or other conditional operators
– Carry logic
• Use arithmetic operators (addition, subtraction, comparison)
Inference should be used wherever possible
– HDL code is portable, compact, and easily understood and maintained
Instantiation
For a list of primitives that can be instantiated, see the HDL
library guide
– Provides a list of primitives, their functionality, ports, and attributes
Use instantiation when it is difficult to infer the exact resource
you want

Help  Software
Manuals 
Libraries Guides
CORE Generator and Architecture Wizard
The CORE Generator tool and Architecture Wizard can help
you create modules with the required functionality
– Typically used for FPGA-specific resources (like clocking, memory, or
I/O), or for more complex functions (like memory controllers or DSP
functions)
Summary
All slices contain four 6-input LUTs and eight registers
– LUTs can perform any combinatorial function of up to six inputs or two
functions of five inputs
– Four of the eight registers can be used as flip-flops or latches; the
remaining four can only be used as flip-flops
– Flip-flops have active high CE inputs and active high synchronous or
asynchronous Set/Rest inputs
SLICEL slices also contain carry logic and the dedicated multiplexers
– The MUXF7 multiplexers combine LUT outputs to create 8-input
multiplexers
– The MUXF8 multiplexers combine the MUXF7 outputs to create 16-input
multiplexers
– The carry logic can be used to implement fast arithmetic functions
The LUTs in SLICEM slices can also SRL and distributed memory
functionality
Manage your control set usage to reduce the size and increase the
speed of your design
Where Can I Learn More?
Software Manuals
– Start  Xilinx ISE Design Suite 13.1  ISE Design Tools 
Documentation  Software Manuals
– This includes the Synthesis & Simulation Design Guide
• This guide has example inferences of many architectural resources
– XST User Guide
• HDL language constructs and coding recommendations
– Targeting and Retargeting Guide for Spartan-6 FPGAs, WP309
– Spartan-6 FPGA User Guides
Xilinx Education Services courses
– www.xilinx.com/training
• Xilinx tools and architecture courses
• Hardware description language courses
• Basic FPGA architecture, Basic HDL Coding Techniques, and other Free
Videos!
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