Transcript No Slide Title

Host/Memory/User Interface
Interfacing with the host computer,
external memory, and user
ESU: Extended Parallel Port, Smart
Media Card, and User Interfaces
ESU Memory Mapped Registers
0
1
2
3
Tds
4
5
6
Twh
EPP Data
7
Tdh
SMC Data
SMC Command
(0 – F Hex)
SMC
SMC
EPP EPP
ready
/notbusy
Data
(from
card)
Data
in
reg
Spare
8
9
10
11
12
Trc
13
14
No wait
15
X
ADDR
NAME
Unused
0x2000
0x2001
Timing
EPP Data
Unused
0x2002
SMC Data
Front Panel soft touch buttons
0x2003
Command
and status
ESU: Memory Mapped Register
Descriptions
• Timing
Programmed by software (probably the boot routine) this register sets parameters for all of the critical timing
between the DSP and the Smart Media Card. Each of the timing blocks is a 3 bit number which will be used as a
index to a counter. Therefore the smallest number we can count for is our cycle time (10ns). This 3 bit limitation
means that the longest we can hold a signal for is 70ns. The longest requirement for our SMC is 50ns.
• Data
The data register is a bi-directional register which can be written and read by the SMC, the EPP, and the Data Bus.
The first byte of the data register is designated for the SMC (which has an 8 bit I/O bus), and the second for the EPP.
• Command/Status
The command/status register takes care of all other functions. It is polled and written regularly by both software and
the host. Additionally the last byte of this register can be written by eight external buttons (user controls). The first
four bits specify the SMC operation that software wants to perform and are read by the SMC_SIG_GEN unit to carry
out that operation. Bit four is the SMC R/nB, which indicates if a SMC operation is running. Bit 5 is the SMC data
read bit, which goes hi when there is valid data from the SMC in the data register. Bit six is the EPP status bit, it
indicates if there is data in the data register. This bit can be written by both the host and the software, and therefore
must be polled before the data register is written by either.
SMC Commands
NOP
0000
Do Nothing
CMD
0001
Send Command to SMC*
Addr1
0010
Load First Address of a two or three byte address word*
WRITE
0011
Load a byte of data*
READ1
0100
Store the first byte from SMC into Data register
READ
0101
Store a successive byte from SMC to Data register
Wait
0110
Wait (only used in erase between address write and erase command)
Reset
0111
Stops any current operation (e.g. READ) and SMC returns control of the data bus.
WAKE
1000
OPEN
1001
Wake the SMC up after reset. SMC takes over the data bus.
NOTE: NO OTHER OFF CHIP OPERATIONS ARE ALLOWED UNTIL NEXT RESET.
Unused
OPEN
1010
Unused
OPEN
1011
Unused
OPEN
1100
Unused
OPEN
1101
Unused
OPEN
1110
Unused
OPEN
1111
Unused
* Data must be valid in the Data register before the command is programmed in the cmd/status register
Example operations
• READ:
Commands: CMD  Addr1  Addr2  Addr3  Read1  Read  … Reset
Data:
<00h> <a1>
<a2>
<a3> <Din> <Din> …<XX>
• Write:
Commands: CMD  Addr1  Addr2  Addr3  Write  Write  … Write  CMD  CMD  Read1
Data:
<80h> <a1>
<a2>
<a3> <Dout> <Dout> … <Dout> <10h> <70h> <stat>
• Erase:
Commands: CMD  Addr1  Addr2  Wait  CMD  CMD  Read1
Data:
<00h> <a1>
<a2>
<XX> <D0h> <70h> <stat>
Boot Memory Interface(BMI)
BMI Pin Description
Signal
Function
Attr.
DATA[0:3] &
ADDR[0:12]
BMS_B
BM
DATA_RDY
DATA[8:15]
PMDAK
BMA0_SEL
BMA1_SEL
BMS_SEL
BMS_EN
Address to Boot Memory
Out
Chip Enable signal to Boot Memory
1= Boot Mode, 0= Normal
1= Data from Boot Memory is valid
Data from Boot Memory
1= enable BMI to drive PMD bus
1= Data from DMD bus to BMADDR0 register
1= Data from DMD bus to BMADDR1 register
1= Data from DMD bus to BMSTS register
1= enable Data in BMSTS register dump to DMD
bus
1= enable Data in BMDATA register dump to DMD
bus
System Clock
Reset signal
Data Memory Data bus
Program Memory Data bus
Out
Out
Out
In
In
In
In
In
In
BMD_EN
CLK
RESET
DMD[0;15]
PMD[0;23]
In
In
In
In/Out
In/Out
To I-UNIT
To I-UNIT
From I-UNIT
From I-UNIT
From I-UNIT
From I-UNIT
From I-UNIT
From I-UNIT
Boot Mode Process Flow
Boot
Memory
Contents
Memory Mapped Register(1)
Memory Mapped Register(2)
Off-chip SRAM Interface(OSI)
OSI Pin Description
Signal
Function
Attr.
ADDR[0:12]
DMS_B
PMS_B
EWE_B
ERE_B
EDMD_RDY
EPMD_RDY
DMA[0:13]
PMA[0:13]
WE_B
Address to Off-Chip SRAMs
Chip Enable signal to Off-chip DM
Chip Enable signal to Off-chip PM
Write Enable signal to Off-chip SRAMs
Read Enable signal to Off-chip SRAMs
1= Data in EDMD Register is valid
1= Data in EPMD Register is valid
Data Memory Address bus
Program Memory Address bus
0= write Data to Memory
1= read Data from Memory
0= Chip Enable to Data Memory
0= Chip Enable to Program Memory
System Clock
Reset signal
Data from/to Off-chip SRAMs
Data Memory Data bus
Program Memory Data bus
Out
Out
Out
Out
Out
Out
Out
In
In
In
DCE_B
PCE_B
CLK
RESET
DATA[0:23]
DMD[0:15]
PMD[0:23]
To I-UNIT
To I-UNIT
From I-UNIT
In
From I-UNIT
In
From I-UNIT
In
In
In/Out
In/Out
In/Out
Off-chip SRAM Access Flow
Off-chip SRAM Write Timing
Off-chip SRAM Read Timing