Transcript Lab07-Power

CS 4101 Introduction to Embedded Systems
LAB 7: WDT+ and
Low-Power Optimization
Chung-Ta King
National Tsing Hua University
• In this lab, we will learn
– WDT+ as the interval timer
– Configuring the low-power mode of MSP430
• Watchdog timer+ (WDT+) is a 16-bit timer that
can be used as a watchdog or interval timer
• Watchdog timer:
– Performs a system restart after a software
problem occurs, e.g., unintended infinite loop
– Counts up and resets system when it reaches limit
– The program must keep clearing the counter
before the limit is reached to prevent a reset
Control of WDT+
• Control register: WDTCTL
– Password protected: to guard against accidental
writes by requiring writing password WDTPW =
0x5A in upper byte  reset if password incorrect
– But, reading WDTCTL returns 0x69 in upper byte
– The lower byte of WDTCTL contains the bits that
control the operation of the watchdog timer
WDT+ as Interval Timer
• Set WDTTMSEL bit in WDTCTL to 1
• Set WDTSSEL bit in WDTCTL to select clock
source: SMCLK or ACLK
– Default clock is SMCLK derived from DCO at 1 MHz
 default period is 32768 counts, or about 32 ms
• Set WDTISx bits in WDTCTL to select interval
– Clock source divided by 64, 512, 8192, or 32,768
• Set WDTCNTCL bit in WDTCTL to clear counter
WDT+ Control Register
WDT+ Interrupt
• WDT+ uses two bits in the Special Function
Registers (SFRs) for interrupt control
– WDT+ interrupt flag, WDTIFG, located in IFG1.0
– WDT+ interrupt enable, WDTIE, located in IE1.0
• WDTIFG is set when time interval expired
• WDTIFG will request an interrupt if
– WDTIE in IE1.0 and GIE in SR are enabled
– WDTIFG can be automatically set/reset
Sample Code (MSP430G2xx1 _wdt_01)
• Toggle P1.0 using interval from WDT+ at about
32ms based on default DCO/SMCLK
void main(void) {
// Enable WDT interrupt
P1DIR |= 0x01;
// Set P1.0 to output
_BIS_SR(LPM0_bits + GIE); // LPM0 w/ interrupt
// Watchdog Timer interrupt service routine
#pragma vector=WDT_VECTOR
__interrupt void watchdog_timer(void) {
P1OUT ^= 0x01;
// Toggle P1.0
Low-Power Mode
CPU and Clocks
CPU active. All enabled clocks active
CPU, MCLK disabled. SMCLK, ACLK active
CPU, MCLK disabled. DCO disabled if not used for SMCLK. ACLK active
CPU, MCLK, SMCLK, DCO disabled. ACLK active
CPU, MCLK, SMCLK, DCO disabled. ACLK active
CPU and all clocks disabled
Power Saving in MSP430
• The most important factor for reducing power
consumption is using the MSP430 clock
system to maximize the time in LPM3
“Instant on” clock
Sample Code (MSP430G2xx1 _ta_01)
• Toggle P1.0 using TA_0 every 50000 cycles
void main(void) {
P1DIR |= 0x01;
// P1.0 output
// CCR0 interrupt enabled
CCR0 = 50000;
TACTL = TASSEL_2 + MC_2; // SMCLK, contmode
_BIS_SR(LPM0_bits + GIE); // LPM0 w/ interrupt
Use _BIC_SR_IRQ(LPM0_bits)
to exit LPM0
#pragma vector=TIMERA0_VECTOR
__interrupt void Timer_A (void) {
P1OUT ^= 0x01;
// Toggle P1.0
CCR0 += 50000;
// Add Offset to CCR0
Basic Lab
(This lab is an extension from Lab 4)
• Flash green LED at 1 Hz using interrupt from
Timer_A, driven by SMCLK sourced by VLO.
While green LED flashing at 1 Hz, pushing the
button flashes red LED at 2Hz and releasing
the button turns off red LED. Use low-power
mode as much as possible.
– Hint: PORT1_VECTOR as interrupt type, WDT+ to
control the flashing of red LED
– Hint: Use P1IES to change the trigger mode (“High
to Low” or “Low to High”)
Timer_A, driven by SMCLK sourced by VLO.
• Flash green LED at 1 Hz using interrupt from
Timer_A, driven by ACLK sourced by VLO in
LPM3. While pushing the button, change from
LPM3 to LPM0, stop flashing green LED, and
flash red LED at 2 Hz using interrupt from
Timer_A, driven by SMCLK sourced by VLO.
Releasing the button returns the system to
LPM3 and stops red LED flashing.