Transcript Frequency and Time Synthesis-a Tutorial

Frequency and Time Synthesis
A Tutorial
Victor S. Reinhardt
June 6, 2000
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 1
Frequency and Time Synthesis
Tutorial Organization
• Basic Concepts
– What is a Synthesizer?
– Basic Concepts of Frequency and Time Synthesis
• Direct Analog Synthesis
– Analog Building Blocks
– (Digital Building Blocks used to Generate Frequencies)
– No VCO’s
• Indirect Synthesis
– Uses Phase or Frequency Locked VCOs
• Direct Digital Synthesis
– Uses Digital Processing Techniques to Generate Output
– Digital Circuits used to Process Numbers
– No VCO’s
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 2
Basic Concepts
What is a Synthesizer?
One or
fr1
..
More
.
Reference
frN
Sources
Synthesizer
Output fo
• One or More Input Reference Sources fr1…frn
• Translation to New Frequency fo
• Phase or Frequency Coherent With References
• Basic Properties
– Frequency Range
– Frequency Resolution
– Switching Rate/Settling Time
– DC Power, Weight, Cost, etc.
– Phase/Frequency Stability (Time
Domain, Environmental Effects)
– Spectral Purity (Frequency
Domain, Spurs, Noise)
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 3
Ideal Periodic Waveform
Positive Zero Crossings
at tn=nTo
Fn=2n
Amplitude A
t
F
Sine Wave
V
• Periodic Function F(F)
V = A F(F)
F = Phase of Function
F(F + 2) = F(F)
• In Time Domain F = wot
wo = Angular Frequency
wo = 2fo
Period To
F=2
fo = 1/To = Frequency
V
• F not a True Observable
Amplitude A
Pulse
t
F
– Measurement Depends on
Inverting F(F)
– Must Keep Track of Number of
Cycles for Multiples of 2
– Best Determined at Zero Crossings
where Slope Large
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 4
Non-Ideal Waveform
V
• Amplitude and Frequency
Now Function of Time
Peak
Variation
Amplitude
Error
t
Zero Crossing
Variation
Time or Phase Error
• Force Nearly-Periodic
Waveform into Periodic
Form
V = ( A + a(t) )·F[ wot + f(t) ]
• Angular Frequency Error
w
w = df/dt
• Frequency Error f
f = w/2
• Fractional Frequency
Error y
a(t) Amplitude Error
f(t) Phase Error
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
y = w/wo = f/fo
y = (df/dt) / wo
Synthesizer Tutorial V. S. Reinhardt Page 5
Additive Noise and Phase &
Time Error
For Sine Wave
Near Zero
V
V = A(wot+f(t))
• Additive Noise V Generates
Phase Error
F, t
V
f, t
For Non-Sine Wave: Effective A is
Determined by Slope Near Zero
Complex Representation
VQ
f
A
VI
f(t) = V(t)/A
– f in Radians Equivalent to
Noise/Signal Ratio
– dB(f) Equivalent to dBc
• Time Error in Positive Zero
Crossing
t = -f/wo = -V/(Awo)
– Note Minus Sign
– Positive V
VI = VQ = V
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Negative t
Positive f
Synthesizer Tutorial V. S. Reinhardt Page 6
Clock Reading vs Time Error
• A Basic Clock Contains a
Frequency Reference and a
Cycle Counter
Basic Clock
fo
Frequency
Reference
• Zero Crossing Time Error
t = -f/wo
Cycle
Counter
– Compares Equivalent Zero Crossings
at Different Times
x
x
t
Ideal Source
• Clock Reading Error
x = f/wo
– Compares Cycle Counts or
Normalized Phases at Same Time
• Note That x =  y dt
But
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
t = - y dt
Synthesizer Tutorial V. S. Reinhardt Page 7
Ideal Coherent Synthesizer
fr
Ideal
Coherent
fr Synthesizer
Frequency
Reference
fo= Kfr
fo= Kfr
wo Kwr wr
yo =
wo = Kwr = wr = yr
fo
Kfr
fr
xo =
wo = Kwr = wr = xr
• Coherent Frequency
Translation by Factor K
– Multiplies the Input Frequency fr
by a Factor K
– Ideal: Doesn’t Add Noise
• Input Phase Error fr Also
Multiplied by K
– The Phase Error Integral of the
Angular Frequency Error
• The y and x of a Reference
Oscillator are Independent
of the Final Output
Frequency
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 8
Spectral Density Review
Important Property of S(f)
U(f)
Filter
H(f)
V(f) =
H(f)U(f)
Sv(f) = |H(f)|2Su(f)
y(t) = dx
dt
• A Random Variable u(t) is
Wide Sense Stationary if the
Autocorrelation Function R
is only a Function of t
Ru(t) = T-1T u(t+t)u(t) dt
• The Spectral Density is the
Fourier Transform of Ru(t)
Su(f) =  ej2ft Ru(t) dt
• For Frequency Translation
K
Sf-output(f) = K2 Sf-input(f)
df
-1
y(t) = wo
dt
Sy-output(f) = Sy-input(f)
w2
Sx-output(f) = Sx-input(f)
Sy(f) = 2 Sf(f)
wo
Sy(f) = w2Sx(f)
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 9
Spurs in Time Domain
• Spurious Signal Rotates
around Main Phasor at 2f
Phasor Diagram
2f
wo
f
Spur at
fo+f
x
Discrete Samples When
Phasor Crosses Real Axis
Phase Error Plot
• Time Domain Measurements
are Sampled at Multiples of
tn = nTo
• Generates Regular Pattern at
Aliases of 1/f
s(t) Allan Variance
Counter Histogram
t
Spur
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Noise
Synthesizer Tutorial V. S. Reinhardt Page 10
Direct Analog Synthesis
Multipliers
xN
f
Mixers
Nf
fa
Dividers
÷M
f
f/M
• Multiplicative Devices
fa  fb
Filters
fb
Switches
f1
f2 .
.
.
.
fn
fb
fo
Amplifiers
• Directly Generates fo
Frequency without VCO
fa+fb+fc
– Multipliers
– Dividers
– x Conserved
f
f
x
Nf
f/M
x
• Additive Devices
– Mixers
f
• Others
x
– Filters
– Switches
– Amps
f
x
f
fin
fout x
f
x
• Also Add Their Own Noise
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 11
Typical Direct Analog
Synthesizer: Divide & Mix
fo = f1+ f2/10+f3/100
• Two Parts of Synthesizer
• Switched Reference Section
– Generates References 0, fr,…9fr
– Switch Refs to LO’s f1, f2,, f3 …
fk=Nkfr
(Nk = 0 to 9)
f3 ... f2 f1
f1=N1fr
+ 10
Switch
Matrix
f2+f3/10
9fr ... 2fr fr
Reference
Generator
fr
f3/10
+ 10
f3=N3fr
f2=N2fr
• Divide and Mix Section (3
Stages Shown)
– Divide f3=N3fr by 10
– Mix with f2=N2fr and Filter to Produce
f2+f3/10 (Bypass Mixer if N2=0)
– Repeat Divide, Mix, and Filter with
f3=N3fr
• End Result
fo = [N1+ N2/10+N3/100 + …]fr
– Each N Selects Digit of Output
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 12
Component Design Parameters
Phase Noise
Characterization of Devices
S(f)
1/f
Noise
White Noise
Floor
1/f Knee
f
1/f Knees
Si
GaAs, InP
1-10 KHz
0.1-1 MHz
Cascaded Multipliers & Dividers
xN1
xN2
xN3
÷N3
÷N2
÷N1
• These Most Critical for Sf(f)
• Make Lowest Noise and Highest N
• All x Contributions the Same
• General Parameters
– Frequency Response
– Speed (Switches)
– DC Power
– Cost, Weight, & Size
• Phase Noise (See Left)
• Phase Stability (Time,
Environment)
– Filters: Phase Shift over
Temperature Critical Issue
• Spurs
– Mixing IM’s
– Switches: On/Of Loss Ratio
Determines Spurs
– Unwanted Multiplier Orders
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 13
Frequency Dividers (Counters)
Asynchronous Counter
fin
FF
FF ... FF
fout
Clean-up Circuit
f’out
fout One fin
Shot
Synchronous Counter
FF
FF ... FF
fin
Regenerative
Delay-t Divider
Set
R-S Q
fin
FF
Delay
t
Reset
fout
• Asynchronous (Ripple)
– Lowest Power
– Most Phase Variation (Cascading Delays)
– Can Use Clean-up Circuit
• Synchronous
– High Power
– Lowest Phase Variation
• Dual-Modulus
– Almost Lowest Power
– Low Phase Variation
– Limit on Divide Number
• Regenerative & Analog Dividers
fout
– Can be Very Simple & Low Noise
– Limited Frequency Range
– Susceptible to Cycle Slips
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 14
Dual Modulus Counter
• Dual Modulus Counter
fin
Dual
Modulus
Counter
÷
Out
÷ P/P+1
P/P+1
Control
Reset
Reset
÷A
A
Counter
M
Counter
÷M
fout
– High Speed Dual Modulus (÷ P/P+1)
Prescaler
– 2 Low Speed (÷M, ÷A) Counters
– fout = fin/(MP+A)
M  P, A = 0 to P-1
– Minimum Divide Ratio = P(P-1)
• Operation
– Prescaler Starts with ÷(P+1)
– Prescaler Switches to ÷P when A Count
Reached
– A and M Counters Reset when M Count
Reached (Thus Must Have M  A)
– Prescaler Switches Back to ÷(P+1)
– For Contiguous Divide Numbers
A = 0 to P-1 (so Must Have M  P-1)
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 15
Frequency Multipliers
f
Nonlinear
Device
Filter
Nf
Sharpness of Distortion
Features (t) Determine
Amplitude of High Harmonics
t
Good Efficiency
Limit Nf  1/t
Device Degradation Due
to Overdrive
• 1. Resistive Diode and Mixer
– Broadband & Loss
– Low Efficiency for High Harmonics
• 2. Step Recovery Diode &
Varactor
– Narrowband (to Match 5  Input Z)
– Higher Efficiency for High
Harmonics
• 3. Transistor
– Highest Efficiency (Gain)
– Too High Drive Can Cause Slow
Damage from Avalanche Breakdown
• 2 & 3 Susceptible to
Parametric Oscillations
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 16
Mixers
fR
• Many Types of Mixers
fLO
– Single Device
– Single, Double, Triple Balanced
– SubHarmonic (Doubles LO Input)
– Single Sideband
fIF
Harmonics of fLO
Harmonics of fR
0
0
1
2
3
4
5
6
7
24
64
81
88
99
99
99
1
29
0
71
73
91
86
99
99
2
20
35
62
85
99
99
99
99
3
32
11
70
69
92
95
97
99
4
24
42
63
85
90
99
99
99
5
29
19
70
68
95
99
99
99
6
27
50
61
85
87
99
99
99
7
30
39
62
64
94
90
99
99
8
29
49
64
87
87
99
99
99
• Higher Order Mixers
Suppress Spurious Mixing
Products
– fspur = NflO - MfR
– (N,M) = Spur Order
• Major Issue: Keeping Spurs
Away From fIF
IF to Spur Ratios (dB)
(WJ-M9E)
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 17
Indirect Synthesis
Loop
Filter
Freq
Control
VCO
fo = T-1(fr)
Frequency
Translation
Error
Signal
Phase or
Frequency
Discriminator
T(fo)
fr
Indirect Synthesis
Loop
Filter
VCO
fo = Nxfr
÷N
Error
Signal
fr
fo/N
Example: Divider Loop
• Utilizes Phase or Frequency
Locked VCO to Act as:
• Operation Inverter
– VCO Output fo Goes Through
Frequency Translation T(fo)
– Phase or Frequency Discriminator
Compares fr to T(fo) and Generates
Error Signal
– Through Loop Filter and VCO
Frequency Control, Error Signal
Driven to Zero so
fr= T(fo)
– Thus VCO Output is Inverse of T
fo= T-1(fr)
• Tracking Filter
– Uses Bandwidth Properties of Loop
to Filter Reference Signal
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 18
Basic Phase Locked Loop
• Definitions
Idealized PLL
f = fo- Vo/s
Vi = fr- f
f
VCO
G(f)
Vo
fr
Vi
– Open Loop Gain G(f)
– Output Phase Error f
– Reference Phase Error fr
– VCO (Free Running) Phase Error fo
f
• Closed Loop Response
H(f) = f/fr = G(f)/(s + G(f))
– H(f) has Low Pass Response with
Knee at fn
– 1-H(f) has High Pass Response with
Knee at fn
Vo = G(f) Vi
H(f)
1-H(f)
1
• Output Phase Error
1
f
fn
f
fn
f = H(f)fr + (1-H(f))fo
– Reference Characteristic f << fn
– VCO Characteristic f >> fn
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 19
Optimum Loop Bandwidth
• Free Running VCO:
– Higher Near In Noise
– Lower White Noise Floor
Sf(f)
Free Running VCO Sf(f)
• Reference
– Lower Near In Noise
– Higher White Noise Floor
Reference Sf(f)
• Optimum Loop Bandwidth fn
for Integrated Noise is Where
Curves Cross
Optimum
PLL Sf(f)
f
• May Have Other Reasons not
to Choose this fn Such as
Settling Time Requirement
Optimum fn
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 20
Oscillator Noise Characteristics
Resonator
Loss = L
Loaded Q = QL
Near Resonance
fR = -2QL·y
• Simple Oscillator Model
• Amp Noise
Sa(f) = (FkT/Pin)·(1 + ff/f)
• Leeson’s Equation
Oscillation Conditions
|GaL| = Loop Gain > 1
S f Around Loop = 0
Pin
Noise
Density =
FkT
Amp
Gain = Ga
Noise Figure = F
Flicker Knee = ff
– Net Phase Around Loop = 0
fR = -fa = -2QL·y
– Note Resonator fR vs y slope Controls
Oscillator Frequency
– Thus Amp Phase Noise is Converted
to Oscillator Frequency Noise
Sy(f) = 1/(2QL)2 Sa(f)
– Since Sy(f) = (f2/fo2)Sf(f) We Obtain
Leeson’s Equation
Sf(f) = (fo/(2QLf))2+1)(FkT/Pin)(1+ ff/f)
Converted Noise + Original Amp Noise
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 21
Oscillator Noise Spectrum
• Oscillator Noise
Spectrum
Oscillator Noise Spectrum
Sf(f)
– Sf(f) = K3/f3 + K2/f2 + K1/f + K0
– Some Components May Mask
Others
K3/f3
QL
• Converted Noise
Converted
Noise
K2/f2
Amp Noise
K1/f
K0
– K3/f3 and K2/f2
– Varies with (fo/(2QL)2 and
FkT/Pin
• Amp Noise
f
– K1/f and Ko
– Only Function of FkT/Pin
Leeson’s Equation
Sf(f) = (fo/(2QLf))2+1)(FkT/Pin)(1+ ff/f)
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 22
Multiplied Oscillator vs Higher
Oscillator Frequency
• Multiplied Oscillator
Multiplied Oscillator
Sf(f)
fo
xN
N2
N2
Nfo
f
Sf(f) = N2(fo/(2QLf))2+1)(FkT/Pin)(1+ ff/f)
Oscillator at fo vs Nfo (Same QL)
Sf(f)
fo
vs
Nfo
N2
– Whole Curve xN2
– Higher Near-in Noise
– Higher Far-out Noise
• Oscillator foNfo
– Only Converted Noise xN2 (Same
QL)
– Higher Near-in Noise
– Same Far-out Noise (Same
FkT/Pin)
• This is Why Indirect
Synthesis is Attractive
– For Lower VCO QL than Ref QL
Bump in Curve
Sf(f) = (Nfo/(2QLf))2+1)(FkT/Pin)(1+ ff/f)
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 23
Classification of Loops
• Loop Order (1st, 2nd, etc.)
• Phase vs Frequency Lock
– PLL Lower Near in Phase Noise
• PLL: Loop Noise Converted to White Phase Noise
• FLL: Loop Noise Converted to White Frequency Noise
– FLL Settles Faster
• Implementation
– Analog Loops
• Analog Phase Discriminator
• Digital Phase Discriminator
– Digital Loop (Filter)
• Phase/Frequency Error Quantization
– Contininuous (or Near Continuous)
– Bang-Bang (Sign of Error)
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 24
1st & 2nd Order PLLs
1st Order PLL
fr
2nd Order PLL
f
fr
VCO
1-H = s for s << wn
H=
f
VCO
wn = G
Damping
z = Factor
wn
2szwn+wn2
s + wn
1-H =
s2
for s << wn
H=
s2+2szwn+wn2
• DC Open Loop Gain Set by
wn (= 2fn)
• DC Open Loop Gain Virtually
Infinite
• VCO Drift will Eventually Cause
Loop to Unlock
• VCO Drift No Problem
• Doesn’t Completely Suppress
Near-in VCO Noise (1/f3)
• Completely Suppresses Near-in
VCO Noise (1/f3)
• Fastest Settling Time for Same wn
• Slower Settling Time for Same wn
• Injection Locked Oscillators
equivalent to 1st Order PLL
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 25
Analog (Loop Filter) PLLs
VCO
Analog
Loop
Filter
fo
Analog
Frequency
Translation
Voltage Output
Phase Detector
fo/N
fr
÷N
fo
Multiplier Loop
fr
xN
frxN
– Mixers - Need Locking Circuit
– Phase-Frequency Det. - Self-Locking
– Loops with PFDs Also Called
“Digital” Loops
• Divider Loop
Divider Loop
fr
• Phase Detectors
fo
– Easy Lock
– ASIC Implementation with PFD
– Mixer & Loop Noise xN
• Multiplier Loop
– False Lock & Spur Issues
– Mixer & Loop Noise Not Multiplied
– Sampling Phase Detector This Type
• Can Also Have Multiple
Conversions (Mixers)
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 26
Digital (Loop Filter) PLLs
Digital
Loop
Filter
fo
D/A
VCO
fr1
..
Analog
DownConversions
fIF1.. fIFk
Averaging
frk
Digital
Frequency
Translations
Counters
fc from VCO
TIF = 1/fIF
tnk
Tc = 1/fc
fIFk = 2 ( n - fIFk tnk )
f = 2 Tc / TIF = 2 fIF / fc
• Can Lock to Many fr’s: fr1 ... frk
– Weighted Averages, Separate
Frequency Offsets, Error Correction
• Digital Phase Detection
– Mix each frk to Lower fIFk = K(frk-K’fo)
– Counters Measure Zero Crossings tnk
of fIFk with Resolution 1/ fc
– Used to Calculate fIFk = K(frk-K’fvco)
– Single Measurement Resolution
f = 2fIF /fc Must be < Ref Noise to
Avoid Spurs
• Digital Loop Filter & D/A
Control VCO
– Loop Filter Sampled at Rate fIF
– D/A LSB Must be < Ref Noise in Time
1/fIF to Avoid Spurs (Note: Frequency
Resolution is Not Set by D/A LSB)
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 27
Example of Digital PLL
10.23 MHz + 
fo
VCXO
VCXO
fo
100 Hz
fIF1
AFS fr1 Down1
D/A
Converter
13.4 MHz
AFS’s
Event Clock
AFS fr2 Downf
2
Converter IF2 & PLL Processor
AFS
3.17 MHz
4
180 KHz
10.23 MHz
from VCXO
98 ns
Event Clock
+
Compute
Phase
S
-
f Offset
+
S
Integrate
Event Clock &
PLL Processor
x 2zwn
2nd Order
Loop Filter S
Integrate
x wn2/s
f Offset
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
3.53 KHz Cs
2.76 KHz Rb
To D/A
From D/C
76
N
N= 3800 Cs
N= 4858 Rb
~100 Hz
Downconverter
(Reinhardt, 1999)
Synthesizer Tutorial V. S. Reinhardt Page 28
Fast Settling Loop Techniques
• Pretune VCO Voltage
2nd
PLL
Ping fo
Pong
Switch
– Approximate New Frequency
• Precharge Loop Integrator
– Preset for New VCO Frequency
• Adaptive Loop Filter
Pretune
÷N
• Reclock & Clear Divider
Adaptive
Loop
Filter
PreCharge
– Dynamically Adjust Bandwidth
fr
Reclock
& Clear
Divider
– When Frequency Changes, Old
Nozero State is Phase Error that
Must be Slewed Out in PLL
– Reclocking and Clearing Eliminates
this Phase Slew
• Ping-Pong Switch & Second
PLL
– Presettle 2nd PLL before Switching
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 29
Effect of Precharge on
Transient Response
Clock Reading - ns
3.5
3
Without Precharge
With Precharge
2.5
2
1.5
1
Loop TC = 0.1 s
0.5
0
0
(Reinhardt, 1999)
0.5
1
1.5
2
2.5
Time - seconds
• Precharge Pre-loads Integrator at Each New Frequency
Command
• Generates More Ideal Stepped Frequency Response
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 30
Cycle Slipping
• Becomes Problem at Low
SNR within the Loop BW
Mechanical Model of
PLL with Noise
Energy
Average
Noise
Noise Burst
Causes
Cycle
Slip
f
• Phase Detectors are Periodic
in Phase
• Finite Probability of Noise
Burst Large Enough to Cause
Slip to Next Cycle
– Mean Time to Cycle Slip Exponential
Function of 1/SNR in Loop BW
• Especially Problem with
Sampling Phase Detectors
(Kroupa, 1973)
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 31
Post-Tuning Drift
Response to Voltage Step
VCO Frequuency
Post-Tuning Drift
• Post-Tuning Drift is Further
Settling of VCO Frequency
After Main Exponential
– Can Last s to Hours
– Can Have Multiple time Constants
Single
Exponential
• Causes
– Thermal Effects in Semiconductors
– Surface Charging and Traps in
Semiconductors
– Bias Circuits and Regulators
• Problems/Issues
Equivalent Circuit of a
Diffusion Process
– Varactor Tuner Prime Source
– GaAs Devices are Especially Prone
to Post-Tuning Drift
– Semiconductor Effects are Very Lot
Dependent
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 32
Direct Digital Synthesizers
• DDSs also called Numerically Controlled Oscillators
• Directly Synthesize a Selectable Output Frequency
from a Clock Using Digital Techniques
• Types of DDSs
– Pulse Output
– Sine Output
– Fractional Divider
– Fractional Divider Phase Interpolation
– Other
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 33
Pulse Output DDS
Accumulator Used as DDS
Pulse Out fo
A Carry
N-Bit
N-Bit
Rout Adder
Register
B A+B
fc Rin
“Square”
MSB
Wave Out
Clock
Frequency
Word K
R
Carry
Carry
Timing
Jitter
Carry
Tc
Clock
Cycles
1 2 3 4 5 6 7 8 9
Pulse
Out
• DDS is N-Bit Accumulator
– For Each Clock Period 1/fc
Rin + K  Rout in N-bit arithmetic
– Can Write as Frac(rin + F)  rout
– Fractional Frequency Word F = K/2N
– Fractional Register Value r = R/2N
• Carry (or MSB) Output
– On Average fo = F fc
– RMS Jitter (No Output Filter)
• Period Jitter  Tc/(12)0.5
• Phase Jitter  F/(3)0.5
• Example F=3/8, (To=(8/3)Tc)
– r = 0(C), 3/8, 6/8, 1/8(C), 4/8, 7/8,
2/8(C), 5/8, 0(C), …..
– Period Errors (T/To): 1/3, 1/3, -2/3
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 34
Typical Pulse Output DDS
Frequency Spectrum
fo = 0.1225 Hz
0
• Large Spurs Very
Close to Carrier
fc = 1 Hz
• Nature of Spurs
Changes Drastically
with fo
Carrier
-20
-40
-60
-80
0
0.2
0.4
0.6
0.8
Frequency (Hz)
1.0
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
• Filtering Doesn’t
Necessarily Reduce
Phase Jitter (When
Nearby Spurs
Present)
• In General Closest
Spur 2-Nfc
Synthesizer Tutorial V. S. Reinhardt Page 35
Sine Output DDS
fc
K
W
Bits Sine
N-Bit
Table
Accumulator
J-Bits
fo
Filter
DAC
M-Bits
• Reduces Spurs by Adding
Sine Table and DAC
– N Determines Frequency Resolution
– Argument of Sine Table = W Bits out
of N Bit Accumulator
– Sine Table Value = J Bits
– DAC M Bits
• Nyquist Theorem: No (InBand) Spurs if
– Sine Table and DAC Perfect
– fo < 0.5 fc (Must LP Filter Output)
• Spur Levels
Stepped DDS Output
– 6 dBc per bit for W & J
– 6-8 dBc per bit for M (Use Effective
Number of Bits not Actual Bits)
– Worst Case Determines Spurs
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 36
Typical Sine Output DDS
Frequency Spectrums
5-Bit DAC
11-Bit DAC
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
dBc
fo=333.25 KHz fc=1 MHz Span=10 KHz RBW=10 Hz
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 37
High Speed DACs
Spur Levels vs Speed
dBc
Spurious/Harmonics
STEL-2373,[1]
Raytheon [2]
-19
Plessey(4) SP2002,[3]
-29
Rockwell,[4]
-39
TI / Lincon Labs LDDS,[5]
Sciteq DCP-1A,[7]
-49
Sciteq ADS-43x[7]
-59
Sciteq (5) ADS-63x [7]
-69
Hughes Space[8],[9]
-79
Philips Microwave
Limeil,Thomson CNI[10]
TRW DDS/HDAC-1,[11]
DAC Triquent SC-0806C,(1)[21]
Output Frequency (MHz)
(Essenwanger & Reinhardt, 1998)
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 38
Sine Table Compression
Algorithms
Compression
Algorithm
None
Unmodified
Sunderland
Modified
Sunderland
ROM Compression
Req’ed
Ratio
214x12
1:1
28x11
51:1
28x4
Raytheon
Taylor
Series
28x9
28x4
28x9
28x3
27x14
27x9
25x3
27x14
27x11
25x7
Cordic
(none)
IIR Filter*
(Presti, et. Al.)
(none)
Nicholas
Conventional
Taylor Series
Logic
Circuits
(none)
adder
Algorithm
Error (dBc)
-97.23
12-bits
±2 LSB
59:1
adder
-86.91
128:1
adder/subtract
-88.94
64:1
2 adders
multiplier
-97.04
multiplier
13-bits
67:1
multiplexer,
±1 LSB
adder
N/A 14 pipelined stages -84.25
18 Bits Wide
3 pipelined stages
Requires 1 calc
N/A
No Limit
of Sinf & Cosf per Freq
(*Modified from Essenwanger & Reinhardt, 1998)
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 39
Fractional Divider or Pulse
Swallowing DDS
fc
Dual
Modulus
Prescaler
÷n/n+1
fo
K
N-Bit
Accumulator
÷n/n+1
Control
Carry
• Dual Modulus Prescaler
– Normally ÷ n
– Output Clocks Accumulator
– On Accumulator Carry ÷ (n+1)
Next Cycle
• N-Bit Accumulator
R+KR
– Carry on Overflow
R
Carry
• Output on Prescaler
Carry
Clock
Cycles
– On Average fo = fc/(n+F)
– RMS Jitter (No Output Filter)
• Period Jitter  Tc/(12)0.5
• Phase Jitter  /(n+F)(3)0.5)
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 40
Phase Interpolation Fractional
Divider (in PLL)
• Fractional Dividers Utilized
Most Often in PLLs
Linear
Phase
Detector
fr
K
R
• Can Reduce Phase Jitter by
Utilizing R Value
DAC
N-Bit
Accumulator
Carry
Output
n/n+1
Control
Divide by
n/n+1
Loop
Amp
– At Carry rTc = Period Error
– Utilize DAC & Linear Phase
Detector to Correct for Error
Represented by R
• Spur Levels Limited by
– Linearity of Phase Detector
– DAC Resolution
fo
VCO
• Without Interpolation Can
Reduce Spurs if 2-Nfc
>>Loop Bandwidth
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 41
Spur Generation in DDSs
Accumulator
Samples v(r)
at rn=fotn
Stepped
Output
Hold Function
•Quantized Sine Wave (Sine
DDS)
•v(fot) Translates mth
Harmonic to mfo
•Stepping Adds HoldFunction Filter
•Square Wave (Pulse DDS)
•Sampling at tn Causes
Aliasing at f=mfo - m’fc
•Spectrum of Hold
Function Sinc2(f/fc)
t-Space Sampled
Spectrum
Output Spectrum
Look-Up
Table
v(r)
•v(r) Periodic in r (Period=1)
•Discrete r-Space Harmonics
r-Space Spectrum
Harmonics
1
1
3
3
5 5
7
1 3 5 7
r-Space Frequency
0
7
fo
2fc
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
0
fc
2fc
Synthesizer Tutorial V. S. Reinhardt Page 42
DDS Spur Algebra
• Time Domain Properties of rn = Frac(nF)
– Produces Periodic Sequence
– In Irreducible form F can be Written as a/b (a and b Relatively Prime)
– Time Domain Sequence Permutation of 0, 1/b, 2/b, …. (b-1)/b
– So Period of Sequence bTc and Number of Unique Values b
• Frequency Domain Properties
– Since Period bTc Sequence has Harmonic Exdpansion
kfc/b = 0, fc/b, 2 fc /b, …. (b-1) fc /b, ....
kfc/b = mfo - m’fc = [m(a/b) - m’]fc
– Thus
• There are b Spurs from 0 to fc
• The Spur Spacing is fc/b
• There is a Large (Principal) Spur at fc-fo that is an Alias of the
(Negative) Fundamental Frequency
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 43
Destroying Coherence With
Register Jitter
N-Bit
Accumulator
r
Fractional
Frequency F
S
r+p
p
v(r + p)
v(r)
Random
Number
Generator
Heuristic Explanation
Sf(f)
Spur Height Reduced
Because of Larger
Jitter
Jitters
Output at fo
by sf
fo
Jitters spur from
mth Harmonic of
v(r) by msf
fspur
f
• Spurs Occur
Because Uniformly
Stepped Sequences
Periodic
– Introducing Jitter
Destroys Periodicity
– Jitter More Efficient
with Spurs from High
Harmonics of v(r)
Expansion
• Converts Spur
Energy to
Broadband Phase
Noise
Converts Spurs to Broadband Spectrum
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 44
Wheatley Jitter Injection
fo = 0.1225 Hz
0
fc = 1 Hz
fo = 0.1225 Hz
0
Carrier
Carrier
-20
-20
-40
-40
-60
-60
-80
-80
0
0.2
0.4
0.6
0.8
Frequency (Hz)
fc = 1 Hz
1.0
0
Without Jitter Injection
0.2
0.4
0.6
0.8
1.0
With Jitter Injection
• Used with Pulse Output DDS
• Destroys Spurs but Produces High Degree of Broadband
Noise
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 45
Randomized DAC DDS
Experimental Results
5-Bit DAC No Jitter
5-Bit DAC With Jitter
0
0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
dBc
dBc
fo=333.25 KHz fc=1 MHz Span=10 KHz RBW=10 Hz
11-Bit DAC No Jitter
(Reinhardt,1993)
• Used with Sine Output DDS
• Less Efficient at Reducing Spurs but with Lower
Broadband Noise
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 46
Frequency and Time Synthesis
Final Summary
• The Basic Concepts Basic Outlined Here are Provide a
Framework for Both the Design & Specification of
Frequency and Time Synthesizers
• The 3 Types of Approaches Outlined Here Are
– Analog Synthesis
– Indirect Synthesis
– Direct Digital Synthesis
• The Above Architectures Used in Combination are
Often the Best Design Approach
• A List of References Follows
Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source
reference is listed on each page, section, or graphic utilized.
Synthesizer Tutorial V. S. Reinhardt Page 47