Transcript Lab 3: ADC - Network and Systems Lab

Network and Systems Laboratory
nslab.ee.ntu.edu.tw
Network and Systems Laboratory
nslab.ee.ntu.edu.tw
Produce a
proper output
voltage level
Signal Path
Sensors
• Light
• Temperature
• Acceleration
• Humidity
• Pressure
• etc.
• Resistance
• Capacitance
• Current
• Voltage
• etc.
Signal Conditioning
(if necessary)
• Amplification
• Filtering
Convert to
voltage
Analog to
Digital
Conversion
(ADC)
10011101
Converts
voltage to
digital number
Today’s labs
Network and Systems Laboratory
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General View
Positive/Negative
voltage reference: define
the upper and lower
limits of the conversion
12 input channels
available
Software configurable
sample-and-hold
period
16 conversion result
storage registers
Each storage register
associated with a
control register
4 clock sources
available for ADC12
clock
Network and Systems Laboratory
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Conversion Formula
 This is a conversion formula of ADC
N ADC  (2
n bit
 Vin  Vref  
 1)  

V

V
 ref 
ref  

 For MSP430 ADC12 module
 It is a 12-bit ADC
N ADC
 Vin  Vref  
 (4095)  

V

V
 ref 
ref  

 If Vin > Vref+ => output 4095 (max)
 If Vin < Vref- => output 0 (min)
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Input Channels
 12 input channels available
 8 external input pins: A0 ~ A7
 2 external voltage reference pins: VeREF+, VeREF 1 internal temperature sensor
 1 supply voltage monitor
 Multiplexed with P6 GPIO
 Setting P6SEL to choose the
function you want
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Internal Voltage Reference Generator
 Voltage references are used as a base of the conversion
 Input voltage compares to the voltage reference to
generate the conversion result
 Vin  V

ref 
N ADC  (2 n bit  1)  

Vref   Vref  
 A stable voltage reference is crucial to an accurate
conversion
 Usually we use a special circuit to generate stable voltage
reference
 MSP430 has a built-in voltage reference generator
 It has two selectable voltage levels

1.5V and 2.5V
Network and Systems Laboratory
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Voltage References Options
 3 positive reference sources
 AVcc – Positive supply voltage
 VREF – internal voltage reference

Can be 1.5V or 2.5V, depends on your selection
 VeREF+ – external positive voltage reference
 2 negative reference sources
 AVss – Negative supply voltage (GND)
 VeREF- -- external negative voltage reference
 6 combinations in total
Network and Systems Laboratory
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ADC12 Conversion Modes
 Single channel single-conversion
 A single channel is converted once
 Sequence-of-channels
 A sequence of channels is converted once
 Repeat-single-channel
 A single channel is converted repeatedly
 Repeat-sequence-of-channels
 A sequence of channels is converted repeatedly
Network and Systems Laboratory
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Conversion Memory
 16 ADC12MEMx memory registers to store conversion
results
 Each ADC12MEMx is configured with an associated
ADC12MCTLx control register.
 EOS: End of sequence, indicates last conversion
 SREFx: Select voltage reference
 INCHx: Select Input Channel
 CSTARTADDx bits define the first memory used for
conversion
 This bit is in ADC12CTL1 control register
Network and Systems Laboratory
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ADC12MCTLx
Use in sequence of
channels mode
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Example
 Depends on the setting of conversion mode,
ADC12MCTLx and CSTARTADDx, the ADC will have
different behavior
Sequence of Channels
Single-channel
CSTARTADDx
= 0000
You need to set
ADC12MCTL0
(choose the input
channel and voltage
reference). And the
conversion result
will store in
ADC12MEM0
CSTARTADDx
= 0100
You need to set
ADC12MCTL8
(choose the input
channel and voltage
reference). And the
conversion result
will store in
ADC12MEM8
CSTARTADDx
= 0000
If you need 5
input channels
You need to set ADC12MCTL0
to ADC12MCTL4 (choose the
input channel and voltage
reference for each
ADC12MEM). You need to set
the EOS bit in ADC12MCTL4
to 1, indicates the sequence of
conversion end here. And the
conversion results will store in
corresponding ADC12 memory
registers
CSTARTADDx
= 0100
If you need 7
input channels
You need to set ADC12MCTL8
to ADC12MCTL14 (choose the
input channel and voltage
reference for each
ADC12MEM). You need to set
the EOS bit in ADC12MCTL14
to 1, indicates the sequence of
conversion end here. And the
conversion results will store in
corresponding ADC12 memory
registers
Network and Systems Laboratory
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Conversion Clock
 4 clock sources available
 ADC12OSC: ADC12 internal oscillator
 MCLK
 SMCLK
 ACLK
 For simplicity, we use ADC12OSC in our lab
 Independent of the system clock
Network and Systems Laboratory
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ADC12 Core
 Two phases for a conversion
 Sample-and-hold
 A/D conversion
 Conversions in MSP430 ADC12
 Triggered by a SHI signal
 Two sample modes

Extended Sample Mode
SHI signal triggers a conversion and
controls the length of sample-andhold period

Pulse Sample Mode
SHI signal triggers a conversion, the
length of the sample-and-hold
period is controlled by other register
Network and Systems Laboratory
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The SHI Signal
 Four selectable sources for SHI
 ADC12SC bit
A single bit in ADC12 control register, set this bit to high will
trigger a conversion
 Timer_A output unit 1 (TA1)
 Timer_B output unit 0 (TB0)
 Timer_B output unit 1 (TB1)

Lab_2 slide
Network and Systems Laboratory
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Sample And Hold Revisit
 There is a sample and hold circuit before A/D
conversion
 Mostly integrated with the ADC chip
 When no conversion, switch S1 is open
 When a conversion start
 S1 closed
 Input signal charge C1
 S1 open, C1 holds the value of input signal
 A/D conversion
 Sample and hold time
 Time between S1 close and re open
 If it is too short

C1 will not fully charged (error)
Network and Systems Laboratory
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Sample Timing Considerations
 For an accurate conversion, the sample-and-hold time
must be long enough to charge up CI to Vs
 Rs will affect the sample-and-hold time (tsample)
 For MSP430F1611, RI = 2K ohm (max); CI = 40 pF (max)
 Minimum tsample for 12-bit conversion
=>
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Setting tsample
If we use ADC internal
oscillator (ADC12OSC) as
ADC12 clock source. Frequency
of ADC12OSC is about 5MHz, if
you set SHT0x to 0100, then the
sample-and-hold time is
64*(1/5000000) second = 12.8 μs
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Rs: Source Resistance
 Many devices didn’t specify their source resistance
(source impedance/output impedance)
 Measuring source impedance is not an easy task
 For most of the case, set the SHTx bit to 0001 or 0010
should work
 use ADC12OSC as clock source
 My suggestion is
 it’s only 16 possible setting, just try it out!
Network and Systems Laboratory
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ADC12 Interrupts
 ADC12 has 18 interrupt sources:
 ADC12IFG0-ADC12IFG15 flag

Associated with each ADC12MEMx, indicates a conversion of
this memory is complete
 ADC12OV: ADC12MEMx overflow

A conversion result is written to any ADC12MEMx before its
previous conversion result was read
 ADC12TOV: conversion time overflow

Another conversion is requested before the current conversion
is completed
Network and Systems Laboratory
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ADC12IV, Interrupt Vector Generator
 All ADC12 interrupts are source to a single interrupt
vector
 Similar to Timer_A3
 The highest priority enabled ADC12 interrupt
generates a number in the ADC12IV register
 Highest priority interrupt generates a number

Branch to the ADC ISR, read ADC12IV, process the associate
sub-routine, leave the ADC ISR
 And then, second highest priority interrupt generates
another number

Branch to the ADC ISR again, ……….
Network and Systems Laboratory
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Reset of Interrupts
 Overflow interrupts (memory overflow and conversion
time overflow) will reset automatically when
 Any access, read or write, of the ADC12IV register
 ADC12IFG0-ADC12IFG15 flag will reset when
 Accessing their associated ADC12MEMx register
Network and Systems Laboratory
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Interrupt Enable Register
Enable the interrupt of corresponding ADC12
memory (ADC12MEM). Usually, you only
need to enable one of the source.
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ADC12 Configuration
Network and Systems Laboratory
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ADC12 Configuration
Enable/disable internal
voltage reference
generator, set the
voltage reference to
1.5/2.5 V
Enable/disable
overflow interrupt
Network and Systems Laboratory
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ADC12 Configuration
For example, if
CSTARTADDx =
We use this bit in ADC12CTL0 register to
trigger a conversion. You can try out the
other source of trigger. The benefit of using
Timer_A or Timer_B trigger sources is you
don’t need CPU to handle the trigger
Network and Systems Laboratory
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ADC12 Configuration
Use Pulse Sample Mode
We use ADC12
internal oscillator
as clock source
Depends on your
requirement, choose the
proper conversion
sequence mode
Network and Systems Laboratory
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Example: Single Channel, single conversion
 Only one input channel, one conversion at a time
Initialization
Turn-on ADC12
Enable Conversion
Trigger a Conversion
An ADC interrupt
generated when the
conversion complete. The
conversion result is
available at the memory
register you choose
Set ADC12ON to 1
Set ENC to 1
Configure the ADC:
ADC12CTL0
1. setting SHTx
2. setting voltage reference generator
ADC12CTL1
1. setting CSTARTADDx (pointed to one memory)
2. setting SHSx
3. SHP = 1
4. setting ADC12 clock source
5. select single channel, single conversion mode
ADC12MCTLx
1. depends on the conversion mode you choose,
and the input channel and voltage reference you
want, set proper ADC12MCTLx register
You can use a timer to trigger a
conversion, in the timer ISR, set the
ADC12SC bit to 1
You need to enable the
corresponding interrupt. The
one selected by CSTARTADDx
Network and Systems Laboratory
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Example: Sequence of Channels
 Multiple input channels, a sequence of conversions
Initialization
Turn-on ADC12
Enable Conversion
Trigger a Conversion
An ADC interrupt
generated when the last
conversion complete. The
conversion results are
available at the memory
registers you choose
Set ADC12ON to 1
Set ENC to 1
Configure the ADC:
ADC12CTL0
1. setting SHTx
2. setting voltage reference
3. set MSC bit to 1 (multiple conversion automatically start)
ADC12CTL1
1. setting CSTARTADDx (pointed to one memory)
2. setting SHSx
3. SHP = 1
4. setting ADC12 clock source
5. select Sequence-of-channels mode
ADC12MCTLx
1. depends on the conversion mode you choose, and the
input channel and voltage reference you want, set proper
ADC12MCTLx register
2. depends on the number of channels you want, set the
EOS bit to 1 in the proper ADC12MCTLx register
You can use a timer to trigger a
conversion, in the timer ISR, set the
ADC12SC bit to 1
You need to enable the interrupt of
the last conversion memory.
Network and Systems Laboratory
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Today’s Labs
 Lab 1: Light Sensor
 use the sample code on website
 choose a light sensor on Taroko
 configure the ADC to take samples from the light sensor
 when the light sensor is covered by hand, turn on a LED;
when the hand remove, turn off the LED

set a threshold
Network and Systems Laboratory
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Lab2: Infrared Proximity Sensor
 Connect the sensor to Taroko
 configure the ADC to take
samples from the sensor
 use an obstacle(hand, paper, etc.)
to approach the sensor
 if distance < 10 cm, Red LED on
 if distance > 20 cm, Green LED
on
 else, Yellow LED on
Signal
GND
Vcc
Network and Systems Laboratory
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Lab 3: Accelerometer
 Connect the accelerometer module to Taroko
 Configure a GPIO pin as a supply voltage source for the
accelerometer module
 configure the ADC to take samples from multiple input
channels
 Configure the LEDs
 when accelerate in +X direction, turn on Red LED; accelerate
in -X direction, turn off Red LED
 when accelerate in +Y direction, turn on Green LED;
accelerate in -Y direction, turn off Green LED
 when accelerate in +Z direction, turn on Yellow LED;
accelerate in -Z direction, turn off Yellow LED