Transcript Document

Computer Architecture I: Digital Design
Dr. Robert D. Kent
Logic Design
Registers
Review
• We have introduced registers previously.
• Registers are constructed using flip-flops and
combinational circuits that enable one to:
– Load (Store) data
– Clear storages (change all bits to 0)
– Increment storages binarily
– Complement storages
– Select individual bits
Goals
• Previously, we studied Combinational circuits, or
networks.
– These are time independent because the inputs,
once provided, immediately establish what the
outputs will be.
• Sequential circuits, including all flip-flops, are
time dependent and require time to stabilize.
– Registers are used to store data and also
manipulate the data they hold.
Review of Characteristic Equations
We will derive register
descriptions in terms of these
basic flip-flops.
D flip-flop
D
Q
C
SR latches are not used since they
are not stable.
Q’
Q+ = D
JK flip-flop
T flip-flop
J
Q
C
K
T
Q
C
Q’
Q+ = JQ’ + K’Q
Q’
Q+ = TQ’ + T’Q
= T xor Q
Registers
• A register is a collection of flip-flops taken as a single
entity.
• Since flip-flops are memory units for single bits, then
registers are the equivalent, multi-bit storage units.
– Since registers are comprised of a finite number, N, of
flip-flops, the total number of 0 and 1 combinations is 2N.
– Each of these combinations is known as the content or
state of the register.
Registers & Memories
• A simple storage, for either registers or memory units, based on the
Master-Slave D flip-flop is constructed by chaining n of them as
shown. The entire memory unit is controlled by the Clock (C)
pulse.
D0
D
Q
Q0
C
Q’
D1
D
Q
Q0
Q0’
Q1
Q1’
D1
Q0 ’
.
.
.
Q1
Dn-1
C
C
D0
Q’
Q1 ’
Qn-1
Q’n-1
C
(See Fig. 2-6 in Mano)
Registers
• CPU registers used in the textbook (Mano):
– PC
– IR
:: Program counter
:: Instruction register
– AR
– DR
:: Address register
:: Data register
(also called MBR – Memory Buffer Reg.)
–
–
–
–
AC :: Accumulator
INR :: Input buffer register
OUTR :: Output buffer register
SCR :: Sequence counter register
An aside …… 0 and 1 circuits
• Oftentimes, it is useful to be able to apply an input of
either 0 or 1 selectively to a circuit.
– This can be done using fuses
– Or, using basic combinational circuits
• 0 circuit is based on XX’ = 0
0
X
• 1 circuit is based on X+X’=1
1
X
Serial versus parallel
• CPU register operations should be among the
fastest of hardware operations
– All instructions are executed in CPU
– Few registers implies more complex circuits may be
employed
– Modern CPU’s also encompass special cache memories
that are constructed using higher cost flip-flops and which
often permit additional operations besides simply read
and write, and which support parallel access to wordlength units of storage
• We will not discuss this interesting topic
Register – Parallel Load
• Register flip-flops should refresh or load simultaneously.
• In the following discussions we shall consider 2-bit
registers, for simplicity.
– Students must read the more complicated cases of 4-bit
registers discussed in the textbook (Mano).
Register – Parallel Load
• Register flip-flops should refresh or load simultaneously.
Load
D Q
I0
C
D Q
I1
Clk
P0
C
P1
Register – Parallel Load
• Register flip-flops should refresh or load simultaneously.
0 = REFRESH
Load
1
P0
0
D Q
I0
C
1
0
I1
Clk
P0
P1
D Q
C
P1
Register – Parallel Load
• Register flip-flops should refresh or load simultaneously.
1 = LOAD
Load
0
I0
1
D Q
I0
C
0
1
I1
Clk
P0
I1
D Q
C
P1
Register – Shifting
• Register shifting is a standard operation.
• Shifting refers to the sequenced movement of stored
bit values from one flip-flop to an adjacent flip-flop
Register – Shifting
• Register shifting is a standard operation.
High (Low)
Low (High)
Serial
Serial
Input
Output
D Q
D Q
D Q
D Q
C
C
C
C
Clk
Unidirectional shifting
- high to low order
- low to high order
Register – Shifting
Input may
bestandard
supplied from
an external
• Register shifting
is
a
operation.
source (Mano’s E-bit) or directly from the
wrap-around bit position (eg. the High bit
input is loaded from the Low bit output)
High (Low)
Low (High)
Serial
Serial
Input
Output
D Q
D Q
D Q
D Q
C
C
C
C
Clk
Unidirectional shifting
- high to low order
- low to high order
Register – Shift/Load/Refresh
• Bi-directional shifting can be combined with parallel load and
refresh operations. This requires use of multiplexers.
Function Table
Mode
Control
S1
S0
Register Operation
0
0
Refresh – no change
0
1
Shift left
1
0
Shift right
1
1
Parallel load
Register – Shift/Load/Refresh
• Bi-directional shifting can be combined with parallel load and
refresh operations.
Register – Shift/Load/Refresh
• Bi-directional shifting can be combined with parallel load and
refresh operations.
S0
S1
Serial in
S0
D Q
S1
0
4x1
1
MUX
A0
C
2
I0
3
S0
D Q
S1
Serial in
I1
Clk
0
4x1
1
MUX
A1
C
2
3
(See Fig. 2-9 in Mano)
Register – Shift/Load/Refresh
• REFRESH OPERATION
0
0
Serial in
S0
D Q
S1
0
4x1
1
MUX
A0
C
2
I0
3
S0
D Q
S1
Serial in
I1
Clk
0
4x1
1
MUX
2
3
C
A1
Register – Shift/Load/Refresh
• PARALLEL LOAD
1
1
Serial in
S0
D Q
S1
0
4x1
1
MUX
A0
I0
A1
I1
C
2
I0
3
S0
D Q
S1
Serial in
I1
Clk
0
4x1
1
MUX
2
3
C
Register – Shift/Load/Refresh
• SHIFT RIGHT (DOWN)
1
0
EH - Serial in
S0
D Q
S1
0
4x1
1
MUX
A0
EH
A1
A0
C
2
I0
3
S0
D Q
S1
EL - Serial in
I1
Clk
0
4x1
1
MUX
C
2
Serial
3
Output
Register – Shift/Load/Refresh
• SHIFT LEFT (UP)
0
1
EH - Serial in
Serial
Output
S0
D Q
S1
0
4x1
1
MUX
A0
A1
A1
EL
C
2
I0
3
S0
D Q
S1
EL - Serial in
I1
Clk
0
4x1
1
MUX
2
3
C
Register – Count/Load/Clear
• Combine counting, loading and synchronous clearing.
Register – Count/Load/Clear
• Recall the properties of the J-K flip-flop
J
K
Q(t+1)
Action
0
0
Q(t)
Leave alone
0
1
0
Reset (Clear)
1
0
1
Set
1
1
Q’(t)
Complement
Register – Count/Load/Clear
• Combine counting, loading and synchronous clearing.
C
L
Inc
I0
J Q
A0
C
K
J Q
I1
C
K
Clk
A1
Carry
Out
(See Fig. 2-11 in Mano)
Register – Count/Load/Clear
• CLEAR - Synchronous.
C=1
0
L=0
Inc=0
0
0
0
J Q
I0
0
A1
0
C
1
0
0
0
0
1
K
0
J Q
I1
C
1
0
Clk
A0
0
1
K
Carry
Out
Register – Count/Load/Clear
• PARALLEL LOAD.
C=0
0
0
L=1
Inc=0
1
J Q
I0
I0
I0’
1
1
0
1
Clk
I1’
I0
A1
I1
C
K
J Q
I1
I1
A0
C
K
Carry
Out
Register – Count/Load/Clear
• PARALLEL LOAD.
C=0
0
0
L=1
Inc=0
I0
I1
1
Note
that J = I and
K = I’. Since J and
K1 are opposite
values, then if I=0,
K= 1 and the value
0 is stored. If I=1,
then J = 1 and the
1
value 1 is stored,
as required.
0
1
Clk
J Q
I0
I0’
I1’
I0
A1
I1
C
K
J Q
I1
A0
C
K
Carry
Out
Register – Count/Load/Clear
• COUNT (Increment by 1)
Register – Count/Load/Clear
• COUNT (Increment by 1)
C=0
1
L=0
1
Inc=1
J Q
I0
C
1
K
J Q
I1
A0
C
K
Clk
A0
A1
Carry
Out
Register – Count/Load/Clear
• Consider a 2-bit incrementer truth table
• First, it is obvious that the final value of A0 must be the
complement of the initial value.
Before
A1
0
0
A0
0
1
After
A1
0
1
A0
1
0
Carry
0
0
1
0
1
1
0
1
1
0
0
1
A0+ = A0’
Achieved by setting
J=K=1
on first flip-flop.
Register – Count/Load/Clear
• Next, if A0 = 0 initially, then A1 does not change. This is
reflected in J = K = 0 on the second flip-flop.
Before
After
A1
A0
A1
A0
Carry
0
0
0
1
0
0
1
1
0
0
1
0
1
1
0
1
1
0
0
1
Register – Count/Load/Clear
• Now consider A0 = 1.
If A1 = 0, then A1 changes to 1. If A1 = 1, then A1 changes
to 0.
But, this is just the complement of A1 and this is achieved
by setting J = K = A0 = 1.
Before
After
A1
A0
A1
A0
Carry
In both cases one
sets:
0
0
0
1
0
J = K = A0
0
1
1
0
0
on the second flipflop.
1
0
1
1
0
1
1
0
0
1
Register – Count/Load/Clear
• Finally, it is obvious that the Carry out is determined by
the product of A0 and A1.
Before
After
A1
A0
A1
A0
Carry
0
0
0
1
0
0
1
1
0
0
1
0
1
1
0
1
1
0
0
1
The Carry out uses a
single AND gate.
Register – Count/Load/Clear
• COUNT (Increment by 1)
C=0
1
L=0
1
Inc=1
J Q
I0
A0 A0’
C
1
K
0/A1
J Q
I1
A0
C
K
Clk
A1 1/A1’
Carry
Out
Memory
• Volatile memories, or RAMs, are typically constructed
using D flip-flops since they are used only for
– Reading from memory
– Writing to memory
– NO other operations are generally permitted
• Read-Only Memories (ROMs) are non-volatile. These
are usually constructed using fuses that can be set to
– Single values only at the time of burning the fuses
– Multiple values by re-burning the fuses (PROM, EPROM)
Memory
• RAM storages are typically constructed as a single unit
called a byte.
• Although the standard storage unit for data is 8-bits
(flip-flops), additional bits are used for a variety of
purposes
– especially error checking (Hamming Codes)
• Each byte is located at a fixed address
– Starts at address 0 and increases contiguously up to a
maximum address, usually a power of 2
– Review lecture on multiplexers as address selectors
enabling data transfer from selected bytes
• The byte is called the smallest unit of addressable
memory.
Summary
• We considered registers as conceptual extensions of the
basic flip-flops.
• By adding additional combinational circuit interfaces we
were able to define register circuits with multiple
capabilities:
–
–
–
–
–
Parallel Load
Counter/Incrementer
Bidirectional Shift using Serial Input/Output
Clear (Reset)
By using T flip-flops, simple complementer registers can be
defined (not discussed)
• Finally, we discussed briefly memories.