Transcript Document

Course: High-Speed and LowPower VLSI (97.575)
Professor: Maitham Shams
Presentation: True SinglePhase Adiabatic Circuitry
By
Ehssan Hosseinzadeh
Special Student
Outline
Introduction
Adiabatic – Switching Circuits
True Single-Phase adiabatic Circuit
Results
Conclusion
References
Introduction
Importance of Reducing Power Dissipation
Techniques
=>Parallelism
=> Pipeline
=> Transformation
=> Reduce the Chip wide Supply voltage
=> Energy Recovery
Adiabatic - Switching
Circuits
Conventional Energetic
Swinging voltage on
capacitor:
- Zero => V
-V => Zero
Engergy dissipation
per transition
E= ½ CV2
Adiabatic - Switching
Circuits
Recovery Energy
Ediss= P. T = I2 . R .T
= (RC/T) CV2
True Single-Phase adiabatic
Circuit
Different Approaches:
Signal voltage swing > Vt of CMOS
=> Adiabatic Amplification
Dynamic logic families
=> 2N2P, 2N-2N2P,
=> True Signle-Phase Energy-Recovery Logic
(TSEL)
=> Source–Coupled Adiabatic Logic (SCAL)
True Single-Phase adiabatic
Circuit
True Single-Phase Energy-Recovery Logic
(TSEL)
Cascades are composed of alternating PMOS
and NMOS gates
TSEL GATES
PMOS
DP:
Vpc: H-L
Vpc  VRP - |vtp|
EP:
•Vin: H , Vpc:L
•Vpc < VRP - |vtp|
•Ddp > |Vtp|
•Vpc  VRP - |vtp|
NMOS
EN:
•Vpc > VRN + |vtn|
CN:
•Vpc  VRN + |vtn|
TSEL Cascades
TSEL Cascades are built by stringing
together alternating PMOS and NMOS gates
SCAL Gates
Single Phase power Clock
Operation
Tunable Current Source at each
Gate
Vbp
DP:
Vpc: H-L
Adiabatlically till
Vpc > |Vtp|
EP:
Vpc: L-H
Vbp increase
Vdd - |Vbp| > |Vtp|
Vpc < Vxp - |Vtp|
Dpp > |Vtp|
Vpc > Vxp - |Vtp|
Vpc
Vbn
SCAL Cascades
Results
8-bit Carry-Lookahead adder (CLAs)
Developed in Static CMOS, PAL, 2N2P,
TSEL, SCAL (0.5um)
Freq: 10 –200 MHz
SCAL CLA => 1.5 – 2.5 times more efficient than
PAL, 2N2P
SCAL CLA => 2 – 5 times less dissipative than
purely combinational or pipelined CMOS
Conclusion
True Single-phase adiabatic logic family:
TSEL, SCAL
Source-coupled variant of TSEL => Increase
energy efficiency by using tunable current
source
Avoid the problems:
Multiple Power-clock schemes
- Increased energy dissipation
- Layout Complexity in clock distribution,
- Clock Skew
- Multiple power–clock generator
References
True Single Phase Adiabatic Circuitry,
Suhwan Kim and Mario Papaefthymiou
Energy Recovery For Low Power CMOS, WC
Athas and N. Tzartanis
Low Power Digital Systems Based on
Adiabatic-Switching Principles, William C.
Athas