Coarse Grain Reconfigurable Architectures

Transcript Coarse Grain Reconfigurable Architectures

Enabling Technologies for Reconfigurable Computing November 21, 2001, Tampere, Finland Reiner Hartenstein University of Kaiserslautern

Enabling Technologies for Reconfigurable Computing Part 4:

FPGAs: recent developments

Wednesday, November 21, 16.00 – 17.30 hrs.

Schedule

Xputer Lab University of Kaiserslautern

time slot 08.30 – 10.00 Reconfigurable Computing (RC) 10.00 – 10.30 coffee break 10.30 – 12.00 Stream-based Computing for RC 12.00 – 14.00 lunch break 14.00 – 15.30 Resources for RC 15.30 – 16.00 coffee break 16.00 – 17.30 FPGAs: recent developments © 2001, [email protected]

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>> Configware Market

Xputer Lab University of Kaiserslautern

• Configware Market • FPGA Market • Embedded Systems (Co-Design) • Hardwired IP Cores on Board • Run-Time Reconfiguration (RTR) • Rapid Prototyping & ASIC Emulation • Evolvable Hardware (EH) • Academic Expertise • ASICs dead • Soft CPU • HLLs • Problems to be solved 3 http://www.fpl.uni-kl.de

Configware heading for mainstream

Xputer Lab University of Kaiserslautern

• Configware market taking off for mainstream • FPGA-based designs more complex, even SoC • No design productivity and quality without good configware libraries (soft IP cores) from various application areas. • Growing no. of independent configware houses (soft IP core vendors) and design services • AllianceCORE & Reference Design Alliance • Currently the top FPGA vendors are the key innovators and meet most configware demand. © 2001, [email protected]

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bleeding edge designs

Xputer Lab University of Kaiserslautern

• Infinite amount of gates not yet available on a chip • 3 mio gates (10 mio in 2003 ?) far away from "infinite" • Bleeding edge designs only with sophisticated EDA tools • Excessive optimization needed • Hardware epertise is inevitable for the designer.

• improve and simplify the design flow the user • provide rich configware libraries of soft IP cores, • control appl., networking, wireless telecommunication, data communication, embedded and consumer markets. © 2001, [email protected]

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Configware (soft IP Products)

Xputer Lab University of Kaiserslautern

• For libraries, creation and reuse of configware • To search for IPs see: List of all available IP • The AllianceCORE program is a cooperation between Xilinx and third-party core developers • The Xilinx Reference Design Alliance Program • The Xilinx University Program • LogiCORE soft IP with LogiCORE PCI Interface.

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Xputer Lab University of Kaiserslautern

EDA as the Key Enabler

(major EDA vendors) • Select EDA quality / productivity, not FPGA architectures • EDA often has massive software quality problems • Customer: highest priority EDA center of excellence – collecting EDA expertise and EDA user experience – to assemble best possible tool environments – for optimum support design teams – to cope with interoperability problems – to keep track with the EDA scene as a rapidly moving target • being fabless, FPGA vendors spend most qualified manpower in development of EDA, IP cores, applications , support • Xilinx and Altera are morphing into EDA companies. © 2001, [email protected]

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OS for FPGAs

Xputer Lab University of Kaiserslautern

• Cadence, Mentor, Synopsys just jumped in. • < 5% Xilinx / Altera income from EDA SW • Changing EDA Tools Market • Major configware EDA vendors – Altera – Cadence – Mentor Graphics – Synopsys – Xilinx © 2001, [email protected]

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EDA Software for Xilinx

Xputer Lab University of Kaiserslautern

•Full design flow from Cadence, Mentor, & Synopsys •Xilinx Software AllianceEDA Program: –Alliance Series Development System.

–Foundation Series Development Systems.

–Xilinx Foundation Series ISE (Integrated Synthesis Environment) –free WebPOWERED SW w. WebFitter & WebPACK-ISE –StateCAD XE and HDL Bencher –Foundation Base Express –Foundation ISE Base Express © 2001, [email protected]

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Foundation ISE Base Express

Xputer Lab University of Kaiserslautern

• ModelSim Xilinx Edition (ModelSim XE) • Forge Compiler • Modular Design • Chipscope ILA • The Xilinx System Generator • XPower • JBits SDK • The Xilinx XtremeDSP Initiative • MathWorks / Xilinx Alliance • System Generator • Wind River / Xilinx alliance © 2001, [email protected]

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Altera EDA

Xputer Lab University of Kaiserslautern

• Altera was founded in June 1983 • EDA: synthesis, place & route, and, verification • Quartus II: APEX, Excalibur, Mercury, FLEX 6000 families • MAX+PLUS II: FLEX, ACEX & MAX families • Flow with Quartus II: Mentor Graphics, Synopsys, Synplicity deliver a design design software to support Altera SOPC solutions. • Mentor: only EDA vendor w. complete design environment f. APEX II incl. IP, design capture, simulation, synthesis, and h/s co verification • Configware: Altera offers over a hundred IP cores • Third party IP core design services and consultants © 2001, [email protected]

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Cadence

Xputer Lab University of Kaiserslautern

• FPGA Designer: top-down FPGA design system, • high-level mapping, architecture-specific optimization, • Verilog,VHDL, schematic-level design entry. • Verilog, VHDL to Synergy (logic synthesis) and FPGA Designer • FPGAs simulated by themselves using Cadence's Verilog XL or Leapfrog VHDL simulators and • simulated w. rest of the system design w. Logic Workbench board/system verification env‘ment. • Libraries for the leading FPGA manufacturers.

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Mentor Graphics

Xputer Lab University of Kaiserslautern

• System Design and Verification. • PCB design and analysis: • IC Design and Verification • shifts ASIC design flow to FPGAs (Altera, Xilinx) – by FPGA Advantage with IP support – by ModuleWare, – Xilinx CORE Generator – Altera MegaWizard integration, © 2001, [email protected]

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Synopsys

Xputer Lab University of Kaiserslautern

• FPGA Compiler II • Version of ASIC Design Compiler Ultra • Block Level Incremental Synthesis (BLIS) • ASIC <-> FPGA migration • Actel, Altera, Atmel, Cypress, Lattice, Lucent, Quicklogic, Triscend, Xilinx © 2001, [email protected]

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>> FPGA Market

Xputer Lab University of Kaiserslautern

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FPGA market 1998 / 1999

Xputer Lab University of Kaiserslautern Source: IC Insights Inc. Meanwhile, Xilinx acquired Philips' MOS PLD business, Lattice purchased Vantis.

1999 rank Xilinx Altera Lattice Actel Lucent Cypress Quicklogic Atmel 17 global sales (mio $) 1998 1999 654 206 154 100 41 30 32 837 410 172 120 43 40 38 http://www.fpl.uni-kl.de

.... into every application

Xputer Lab University of Kaiserslautern

• [Dataquest] PLD market > $7 billion by 2003. • „ fastest growing segment of semiconductor market.“ • IP reuse and "pre-fabricated" components for the efficiency of design and use for PLDs • FPGAs are going into every type of application. © 2001, [email protected]

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Xputer Lab University of Kaiserslautern

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Xilinx

Xputer Lab University of Kaiserslautern

•fabless FPGA semi vendor, San Jose, Ca, founded 1984 •key patents on FPGAs (expiring in a few years) •As designs get larger, Xilinx losed its advantage (bugfixes did not require to burn new chips) •meanwhile, weeks of expensive debug time needed © 2001, [email protected]

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Xilinx Flexware

Xputer Lab University of Kaiserslautern

• Virtex, Virtex-II, first w. 1 mio system gates. – Virtex-E series > 3 mio system gates. • Virtex-EM on a copper process & addit. on chip memory f. network switch appl.

• The Virtex XCV3200E > 3 million gates, 0.15-micron technology, • Spartan, Spartan-XL, Spartan-II – for low-cost, high volume applications as ASIC replacements – Multiple I/O standards, on-chip block RAM, digital delay lock loops – eliminate phase lock loops, FIFOs, I/O xlators , system bus drivers • XC4000XV, XC4000XL/XLA, CPLD: low-cost families – rapid development, longer system life, robust field upgradability – support In-System Programming (ISP), in-board debugging, – test during manufacturing, field upgrades, full JTAG compliant interface • CoolRunner: low power, high speed/density, standby mode.

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Altera Flexware

Xputer Lab University of Kaiserslautern

• Newer families: APEX 20KE, APEX 20KC, APEX II, MAX 7000B, ACEX 1K, Excalibur, Mercury families. – Apex EP20K1500E (0.18-µ), up to 2.4 mio system gates, – APEX II (all-copper 0.13-µ) f. data path applications, supports many I/O standards. 1-Gbps True-LVDS performance – wQ2001, an ARM-based Excalibur device • Altera mainstream: MAX 7000A, 3000A; FLEX 6000, 10KA, 10KE; APEX 20K families. • Mature and other : Classic, MAX 7000, 7000S, 9000; FLEX 8000, 10K families. © 2001, [email protected]

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Triscend CSoC

Xputer Lab University of Kaiserslautern

Configurable system logic

Digital Filter Display Interface

ARM

Viterbi A/D Interface

CSI Socket Configurable System Interconnect (CSI) Bus Memory Other System Resources [Kean]

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>> Embedded Systems (Co-Design)

Xputer Lab University of Kaiserslautern

[à la S. Guccione]

Goal: away from complex design flow

Schematics/ HDL Netlister Netlist Place and Route Bitstream HLL Compiler

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Xputer Lab University of Kaiserslautern

Overcome traditional separate design flow

[à la S. Guccione]

HLL Compiler Schematics/ HDL Netlister Netlist Place and Route .

Bitstream User Code Compiler Executable

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Xputer Lab University of Kaiserslautern

Overcome traditional co-processing design separate flow -> JBits Design Flow

[à la S. Guccione]

JBits

API User Java Code Java Compiler Executable Schematics/ HDL Netlister Netlist Place and Route .

Bitstream User Code Compiler Executable

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Xputer Lab University of Kaiserslautern

Embedded hardw. CPU & memory cores on chip.

HLL Compiler

HLL

Compiler FPGA core CPU core Memory core

http://www.fpl.uni-kl.de

Xputer Lab University of Kaiserslautern

new directions in application development

• new directions in application development. • aut. partitioning compilers: designer productivity • like CoDe-X (Jürgen Becker, Univ. of Karlsruhe), • supports Run-Time Reconfiguration (RTR), a key enabler of error handling and fault correction by partial re-routing the FPGA at run time, as well as remote patching for upgrading, remote debugging, and remote repair by reconfiguration - even over the internet. © 2001, [email protected]

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>> Run-Time Reconfiguration (RTR)

Xputer Lab University of Kaiserslautern

CPU use for configuration management

Xputer Lab University of Kaiserslautern

HLL

Compiler

http://www.fpl.uni-kl.de

Xputer Lab University of Kaiserslautern

hard CPU & memory core on same chip

HLL

RTR System Design

Compiler

HLL

Compiler FPGA core CPU core Memory core

http://www.fpl.uni-kl.de

Converging factors for RTR

Xputer Lab University of Kaiserslautern

• Converging factors make RTR based system design viable • 1) million gate FPGA devices and co-processing with standard microprocessors are commonplace • direct implementation of complex algorithms in FPGAs.

• This alone has already revolutionized FPGA design. • 2) new tools like Xilinx Jbits software tool suite directly support coprocessing and RTR.

User Java Code

JBits

API Java Compiler Executable

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RTR

Xputer Lab University of Kaiserslautern

• divides application into a series of sequentially executed stages, each implemented as a separate execution module. • Partial RTR partitions these stages into finer-grain sub-modules to be swapped in as needed. • Without RTR, all conf. platforms just ASIC emulators. • needs a new kind of application development environments. • directly support development and debugging of RTR appl.

• essential for the advancement of configurable computing • will also heavily influence the future system organization • Xilinx, VT, BYU work on run-time kernels, run-time support, RTR debugging tools and other associated tools. • smaller, faster circuits, simplified hardware interfacing, fewer IOBs; smaller, cheaper packages, simplified software interfaces.

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Run-time Mapping

Xputer Lab University of Kaiserslautern

• run-time reconfigurable are: Xilinx VIRTEX FPGA family • RAs being part of Chameleon CS2000 series systems • Using such devices changes many of the basic assumptions in the HW/SW co-design process: • host/RL interaction is dynamic, needs a tiny OS like eBIOS, also to organize RL reconfiguration under host control • typical goal is minimization of reconfiguration latency (especially important in communication processors), to hide configuration loading latency, and, • Scheduling to find ’best’ schedule for eBIOS calls (C~side).

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>> Rapid Prototyping & ASIC Emulation

Xputer Lab University of Kaiserslautern

ASIC emulation: a new business model ?

• ASIC emulation / Rapid Prototyping: to replace simulation • Quickturn (Cadence), IKOS (Synopsys), Celaro (Mentor) • from rack to board to chip (from other vendors, e. g. Virtex and VirtexE family (emulate up to 3 million gates) • Easy configuration using SmartMedia FLASH cards • ASIC emulators will become obsolete within years • By RTR: in-circuit execution debugging instead of emulation © 2001, [email protected]

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>> Evolvable Hardware (EH)

Xputer Lab University of Kaiserslautern

EH, EM, ...

Xputer Lab University of Kaiserslautern

• "Evolvable Hardware" (EH), "Evolutionary Methods" (EM), „digital DANN“, "Darwinistic Methods", and biologically inspired electronic systems • new research area, also a new application area of FPGAs • revival of cybernetics or bionics: stimulated by technology • „evolutionary“ and „DNA“ metaphor create awareness • EM sucks, also thru mushrooming funds in the EU, in Japan, Korea, and the USA • EM-related international conference series are in their stormy visionary phase, like EH, ICES, EuroGP, GP, CEC, GECCO, EvoWorkshops, MAPLD, ICGA © 2001, [email protected]

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EH, EM, ...

Xputer Lab University of Kaiserslautern

• Shake-out phenomena expected, like in the past with „Artificial Intelligence“ • should be considered as a specialized EDA scene, focusing on theoretical issues. • Genetic algorithms suck - often replacable by more efficient ones from EDA • It is recommendable to set-up an interwoven competence in both scenes, EM scene and the highly commercialized EDA scene • EH should be done by EDA people, rather than EM freaks.

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>> Academic Expertise

Xputer Lab University of Kaiserslautern

BRASS (1)

Xputer Lab University of Kaiserslautern

• UC Berkeley, the BRASS group: Prof. Dr. John Wawrzynek • The Pleiades Project, Prof. Jan Rabaey, ultra-low power high performance multimedia computing through reconfiguration of heterogeneous system modules, reducing energy by overhead elimination, programmability at just right granularity, parallellism, pipelining, dynamic voltage scaling. • Garp integrates processor and FPGA; dev. in parallel w. compiler - software compile techniques (VLIW SW pipelining): simple pipelining schema f. broad class of loops. • SCORE , a stream-based computation model - a unifying computational model. Fast Mapping for Datapaths: by a tree parsing compiler tool for datapath module mapping © 2001, [email protected]

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BRASS (2)

Xputer Lab University of Kaiserslautern

• HSRA . new FPGA (& related tools) supports pipelining, w. retiming capable CLB architecture, implemented in a 0.4um DRAM process supporting 250MHz operation • OOCG.

Object Oriented Circuit-Generators in Java • MESCAL (GSRC), the goal is: to provide a programmer's model and software development environment for efficient implementation of an interesting set of applications onto a family of fully-programmable architectures / microarchitectures. © 2001, [email protected]

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Berkeley claiming (1)

Xputer Lab University of Kaiserslautern

• SCORE, a stream-based computation model: the BRASS group claims having solved the problem of primary impediment to wide-spread reconfigurable computing, by a unifying computational model. • Remark: clean stream-based model introduced ~1980: Systolic Array • 1995: Rainer Kress. Introduces reconfigurable stream-based model • Fast Mapping for Datapaths (SCORE): BRASS claims having introduced 1998 the first tree-parsing compiler tool for datapath module mapping ." Further, it is the first work to integrate simultaneous placement with module mapping in a way that preserves linear time complexity." © 2001, [email protected]

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Berkeley claiming (2)

Xputer Lab University of Kaiserslautern

• Remark: The DPSS (Data Path Synthesis System) using tree covering simultanous datapath placement and routing „radical rethink of the ASIC design flow aimed at arrays.“ [published in 2000] • Remark: the KressArray, a scalable rDPU array [1995] is stream-based © 2001, [email protected]

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.... Stream Processors - MSP-3

Xputer Lab University of Kaiserslautern

• 3rd Workshop on Media and Stream Processors (MSP-3) • http://www.pdcl.eng.wayne.edu/msp01 •

in conj. w. 34th Int‘l Symp. on Microarchitecture (MICRO -34)

• http://www.microarch.org/micro34 • Austin, Texas, December 1-2, 2001 • Topics of interest include, but are not limited to: – Hardware/Compiler techniques for improving memory performance of media and stream-based processing – Application-specific hardware architectures for graphics, video, audio, communications, and other media and streaming applications – System-on-a-chip architectures for media & stream processors – Hardware/Software Co-Design of media and stream processors – and others ....

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Berkeley: „Chip-in-a-Day“ Bee Project

Xputer Lab University of Kaiserslautern

• Chip-in-a-Day Project. Prof. Dr. Bob Broderson, BWRD: targeting a radical rethink of the ASIC design flow aimed at shortening design time. Relying on stream-based DPU arrays (not rDPU and related EDA tools. Davis: „ „... 50x decrease in power requ. over typical TI C64X design.“ • New design flow to break up the highly iterative EDA process, allowing designers to spend more time defining the device and far less time implementing it in silicon. „... developers to start by creating data flow graphs rather than C code,„ • It is stream-based computing by DPU array (hardwired DPA) • For hardwired and reconfigurable DPU array and rDPU array © 2001, [email protected]

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Stanford thru BYU

Xputer Lab University of Kaiserslautern

• Stanford: • no activities seen other than YAFA (yet another FPGA application) • UCLA: algorithms. 9 projects, mult. sponsors under California MICRO Program • Prof. Majid Sarrafzadeh directs the SPS project: "versatile IPs„, a new routing architecture, architecture-aware CAD, IP-aware SPS compiler • USC: computing: MAARC project, DRIVE project and Efficient Self Reconfiguration. - Prof. Dubois: RPM Project, FPGA-based emulation of scalable multiprocessors. • DEFACTO proj.: compilation - architecture-independent at all levels • MIT. Prof. Flynn went emeritus, Oskar Menzer moved to Bell Labs.

Prof. Jason Cong, expert on FPGA architectures and R& P Prof. Viktor Prasanna (EE dept.) works 20% on reconfigurable MATRIX web pages removed `99. „RAW project“: a conglomerate • VT. Prof. Brad Hutchings, BYU on programming approaches for RTR Systems • BYU. © 2001, Prof. Athanas: Jbits API f. internet RTR logic ($2.7 mio DARPA). w. Prof. Brad Hutchings works on the JHDL (JAVA Hardware [email protected]

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Toronto thru Karlsruhe

Xputer Lab University of Kaiserslautern

• U. Toronto. Prof. J.Rose, expert in FPGA architectures and R & P alg. • The group has dev. Transmogrifier C, a C compiler creating netlist for Xilinx XC4000 and Altera's Flex 8000 and Flex 10000 series FPGAs.

• Founder of Right Track CAD Corporation acquired by Altera in 1999 • Los Alamos National Laboratory, Los Alamos, New Mexico (Jeff Arnold) – Project Streams-C: programming FPGAs from C sources.

• Katholic University of Leuven , and IMEC: Prof. Rudy Lauwereins, methods for MPEG-4 like multimedia applications on dynamically reconfigurable platforms, & on reconf. instruction set processors. • University of Karlsruhe . Prof. Dr.-Ing. Juergen Becker: hardware/software co-design, reconfigurable architectures & rel. synthesis for future mobile communication systems & synthesis w.

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>> ASICs dead ?

Xputer Lab University of Kaiserslautern

• Configware Market • FPGA Market • Embedded Systems (Co-Design) • Hardwired IP Cores on Board • Run-Time Reconfiguration (RTR) • Rapid Prototyping & ASIC Emulation • Evolvable Hardware (EH) • Academic Expertise • ASICs dead ? • Soft CPU • HLLs • Problems to be solved 50 http://www.fpl.uni-kl.de

Xputer Lab University of Kaiserslautern

My Position

[ Jonathan Rose ]

(When) Will FPGAs Kill ASICs?

[ Jonathan Rose ]

ASICs Are Already Dead

They Just Don’t Know It Yet!

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Why?

[ Jonathan Rose ] Xputer Lab University of Kaiserslautern

1. You have to fabricate an ASIC



Very hard, getting harder

2. An FPGA is pre-fabricated

 

A standard part immense economic advantages

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Xputer Lab University of Kaiserslautern

Making ASICs is Damn Difficult

[ Jonathan Rose ]

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Did I Mention Inventory?

[ Jonathan Rose ] Xputer Lab University of Kaiserslautern

• ASIC users must predict # parts

– 2 or 3 months in advance!

• Never guess the Right Amount

[ Jonathan Rose ]

http://www.fpl.uni-kl.de

[ Jonathan Rose ]

FPGAs Give You

Xputer Lab University of Kaiserslautern

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FPGAs: “Too Pricey & Too Slow ?”

Xputer Lab University of Kaiserslautern [ Jonathan Rose ]

• 9 Times Out of 10 – You make can the thing fast by breaking it into multiple parallel slower pieces • Custom IC Designer Can Make Logic – 20x Faster, – 20x Smaller than Programmable © 2001, [email protected]

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Xputer Lab University of Kaiserslautern

What About PLD Cores on ASICs ?

What’s Wrong with This Picture?

Embedded FPGA Fabric

[ Jonathan Rose ]

3. Have No Idea What to Connect the PLD Pins to – Chances Are, You Are Going to Get It Wrong!

2001, [email protected]

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Xputer Lab University of Kaiserslautern

What’s Right with This Picture!

Embedded CPU Serial Link, Analog, “etc.”

1. Pre-Fabricated 2. One CAD Tool Flow!

[ Jonathan Rose ]

3. Can Connect Anything to Anything

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>> Soft CPU

Xputer Lab University of Kaiserslautern

Free 32 bit processor core

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Xputer Lab University of Kaiserslautern

Processors in PLDs: Excalibur

Dual-Port RAM Single-Port RAM ARM 922T Core General Purpose PLD [ Jonathan Rose ]

http://www.fpl.uni-kl.de

Xputer Lab University of Kaiserslautern

Soft CPU: new job for compilers

HLL Compiler FPGA Memory core soft CPU FPGA

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Some soft CPU core examples

Xputer Lab University of Kaiserslautern

core MicroBlaze 125 MHz 70 D-MIPS Nios Nios 50 MHz Nios architecture 32 bit standard RISC 32 reg. by 32 LUT RAM based reg.

16-bit instr. set 32-bit instr. set 8 bit platform Xilinx up to 100 on one FPGA Altera Mercury Altera 22 D-MIPS Altera – Mercury REGIS Reliance-1 1Popcorn-1 architecture SPARC platform gr1040 gr1050 My80 DSPuva16 16-bit 32-bit i8080A 16 bit DSP © 2001, [email protected]

FLEX10K30 or EPF6016 Spartan-II core Leon 25 Mhz ARM7 clone uP1232 8-bit Acorn-1 YARD-1A xr16 63 ARM CISC, 32 reg.

8 bits Instr. + ext. ROM 12 bit DSP 8 bit CISC 16-bit RISC, 2 opd. Instr.

RISC integer C 200 XC4000E CLBs 2 XILINX 3020 LCA Lattice 4 isp30256, 4 isp1016 Altera, Lattice, Xilinx 1 Flex 10K20 old Xilinx FPGA Board SpartanXL http://www.fpl.uni-kl.de

Xputer Lab University of Kaiserslautern

Nios Architecture (Altera)

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free DSP or Processor Cores

Xputer Lab University of Kaiserslautern

CPU core Reliance 1 PopCorn 1 Acorn 1 16-bit DSP Free-6502 DLX DLX2 GL85 AMD 2901 AMD 2910 i8051 i8051 Description 12bit DSP and peripherals small 8 bit CISC small 8 bit CISC A 16-bit Harvard DSP with 5 pipeline stages.

6502 compatible core Generic 32-bit RISC CPU Generic 32-bit RISC CPU i8085 clone AMD 2901 4-bit slice AMD 2910 bit slice 8-bit micro-controller another i8051 clone Language Schematic Verilog VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL VHDL Implementation Viewlogic 7 Lattice CPLDs 1 Lattice CPLD isp3256-90 Max2PlusII+ 1 Altera 10k20 Xilinx XC4000 Synopsys Synopsys Mentor Graphics © 2001, [email protected]

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Xputer Lab University of Kaiserslautern

• UCSC: 1990!

• Märaldalen University, Eskilstuna, Sweden • Chalmers University, Göteborg, Sweden • Cornell University • Gray Research • Georgia Tech • Hiroshima City University, Japan

FPGA CPUs in teaching and academic research

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Xputer Lab University of Kaiserslautern

Xilinx 10Mg, 500Mt, .12 mic

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Xputer Lab University of Kaiserslautern

Soft rDPA feasible ?

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Xputer Lab University of Kaiserslautern Performance 1000 100 10 1 1980 1990

CPU DRAM

µProc 60%/yr

Processor-Memory Performance Gap: (grows 50% / year) 2000 DRAM 7%/yr..

Array I/O examples

http://www.fpl.uni-kl.de

HLL 2 Soft Array

Xputer Lab University of Kaiserslautern HLL Compiler miscellanous soft CPU Memory

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HLL 2 „flex“ rDPA

Xputer Lab University of Kaiserslautern HLL Compiler miscellanous CPU Memory

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>> HLLs

Xputer Lab University of Kaiserslautern

HLLs for Hardware Design vs. System Design vs. RTR System Design

HLL

System Design

Compiler

HLL

RTR System Design 73

Compiler

http://www.fpl.uni-kl.de

Xputer Lab University of Kaiserslautern HLL Compiler

HLLs for Hardware Design vs. System Design vs. RTR System Design

HLL

System Design

Compiler

HLL

RTR System Design 74

Compiler

http://www.fpl.uni-kl.de

CPU and memory on Chip

Xputer Lab University of Kaiserslautern HLL

RTR System Design

Compiler

HLL

Compiler FPGA core CPU core Memory core

http://www.fpl.uni-kl.de

Xputer Lab University of Kaiserslautern

[à la S. Guccione]

RTP Core

Library

JRoute

API

Jbit Environment

JBits

API User Code

XHWIF BoardScope

Debugger

Device Simulator

http://www.fpl.uni-kl.de

Xputer Lab University of Kaiserslautern HLL Compiler

HLLs for Hardware Design vs. System Design vs. RTR System Design

HLL

System Design

Compiler

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Embedded System Design

Xputer Lab University of Kaiserslautern FPGA core HLL Compiler

CPU core Memory core HLL

Compiler FPGA Memory core soft CPU FPGA

http://www.fpl.uni-kl.de

>> Problems to be solved

Xputer Lab University of Kaiserslautern

Why Can’t Reconfig. Software Survive?

Xputer Lab University of Kaiserslautern

• Resource constraints/sizes are exposed: – to programmer – in low-level representation (netlist) • Design revolves around device size – Algorithmic structure – Exploited parallelism © 2001, [email protected]

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Xputer Lab University of Kaiserslautern

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