Transcript Document
Modeling TSV Open Defects in 3D-Stacked DRAM Li Jiang†, Liu Yuxi†, Lian Duan‡, Yuan Xie ‡, and Qiang Xu† Presenter: Qiang Xu † CUhk REliable Computing Laboratory Department of Computer Science & Engineering The Chinese University of Hong Kong ‡ hk l i a b l e C o m pu t i n g L a b o r a t o r y Department of Computer Science & Engineering Pennsylvania State University, USA Purpose New test challenges for 3D-stacked DRAM Massive amount of TSVs that are prone to open defects and coupling noises Conduct extensive simulation to study the faulty behavior of TSV open defects Outline Introduction Motivation Simulation Methodology Simulation Results Conclusion Why 3D-Stacked DRAM? Ever-increasing performance gap between processor and memory Excessive latency Limited bandwidth 3D-stacking is a promising solution to tackle this “Memory Wall” problem 3D-Stacked DRAM is Already Here … NEC: 4Gb, 8 Layers SamSung: 8Gb, 4 Layers TSV DRAM 4 Gbit density TSV Interposer Peripherals 8 strata 3 Gbps/pin RD/WR I/O Buffer PCB “True” 3D-Stacked DRAM One rank in multiple layers Separate peripheral logic layer Loh ISCA’08 Much better performance when compared to using TSVs only for buses TSV density is extremely high Motivation TSVs are prone to open defects Contamination O2 trapped in bonding surface Miss Alignment/dislocation Mechanical failures in TSVs Contact resistances Voids during filling M. Kawano, et al. IEDM’06 Motivation Separation Cvc (fF) (um) 1 1.16 3 0.60 5 0.42 7 0.31 9 0.25 Cgc (fF) 0.87 0.97 1.05 1.04 1.04 I. Savidis et.al. ISCAS08 Capacitive coupling between adjacent TSVs is NOT negligible! 3D Memory Model DRAM Layer 1 BL d 0 Peripheral Layer V ref Enable 0 0 c BL 1 To Decoder Write Operation Read Operation TSV 1 b 1 1 a 0 Sensing Circuit Precharge Circuit Simulation Setup SPICE simulation Open defect represented by a very large resistance Vdd 1.8v, Vth 0.6v Coupling capacitance is set according to previous work Simulation Schematic for Wordline Open Cw WL2 C0 Ropen Cell0 WL0 Cw C1 WL1 Vsig Cell1 Cw + - BL X BL Cb SE Cb SA Output Wordline Open C0 C1 C3 C4 C5 C6 C7 C8 C9 WL0 WL1 WL2 WLn BLi-1 BLi-1 BLi BLi BLi+1 BLi+1 Access the open wordline Access the neighboring wordline of open wordline Vary wordline load capacitance Vary trapped charges in pass-transistor 10 Cell0 Wordline Write No Access to open wordline Access its neighboring wordline of the (WL1) Cell1 Cell4 Cell5 Cell7 Cell8 Cell3 WL0 WL1 Cell6 WL2 Cell9 WLn Write 1 to Cell4 Write 0 to Cell4 10 01 BLi-1 BLi-1 BLi BLi BLi+1 BLi+1 Strong write 0 (1w0),Weak write 1 (0w1) V(1w0) Middle V(0w1) Border V-Cell0 1.2 0.8 Multiple Write Single Write 0.4 0 0 1 2 3 4 5 6 ns 7 0 10 20 30 40 ns 50 0 0 Cell 01Cell 1 0 4 0Cell7 Wordline Read Multiple Access Two scenarios: Cell in the same bitline Cell in Complemented bitline Cell1 Cell5 Cell8 Cell3 WL0 WL1 Cell6 WL2 Cell9 WLn 01 0 BLi-1 BLi-1 BLi BLi BLi+1 BLi+1 (Cload=200fF) V(BLi-1) V 1.2 V(Cell4) Cell Access SA 0.8 C4 C7 0.4 0 0 5 10 15 20 25 30 ns (Vtrap>0.7V) V(Cell0) V(Cell7) V Cell Access 1.6 SA 1.2 0.8 0.4 0 0 5 10 15 20 25 30 ns (Vtrap>1V) Simulation Schematic for bitline Open Ropen SA Cb Cb SA Cb SA Cb Cb Cb SE + - Cc Cc Cc Cc Cc Vdd BLi-1 BLi-1 BLi Aggressor Victim BLi BLi+1 BLi+1 Aggressor Bitline Read Access WL0,No Error 0C4 1 C7 C0 C1 C5 0C6 C8 C9 WL0 C3 WL1 WL2 C1 BLiBLi Access WL1, C6BLi+1BLi C4BLi-1BLi-1 BLi Driving force determine the output of open bitline V 1.6 1.2 0.8 0.4 0 BLi-1 BLi-1 BLi BLi BLi+1 BLi+1 Vref V V(BLi) 1.6 BLi-1=1,BLi+1=0 BLi-1=0,BLi+1=0 1.2 0.8 BLi-1=0,BLi+1=1 0.4 BLi-1=1,BLi+1=1 0 10 15 20 25 30 ns 5 10 15 20 25 30 ns Compatible Coupling Competitive Coupling V(BLi) 5 WLn Coupling from Multiple Layer More complicated coupling effect Interference from other layer Memory Block Layer1 C(Ta,Tc) Tc Layer2 Layer3 w Tb TSV Peripheral s C(Ta,Tb) Ta H Fault Modeling No Access Multiple Access Coupling by neighbor Conclusion The massive amount of TSVs used in “True” 3D-stacked DRAM are prone to open defects and coupling noises We model the faulty behavior of open TSVs and show their effects through extensive simulation Thank you for your attention !