Transcript Document

Testing of ROM.
Faults in ROMs and their classification
Functional faults:
1.
Main SAF;
2.
Amplifier SAF;
3.
R/W line SAF;
4.
Selection CS SAF;
5.
Data line SAF;
6.
Data line interruption;
7.
Data line short-circuit;
8.
Data line cross-talk;
9.
Address line SAF;
10. Address line interruption;
11. Address line short-circuit;
12. Interruption in decoder;
13. Selection of the wrong address;
14. Turning to several addresses;
15. Faults in transition (0 to 1and vice versa);
16. Dependence of data between slots.
Classification of faults:
1.
SAF stuck at 0/1 faults 1-6;
2.
CF coupling faults faults 7,8 and 16;
3.
TF transition faults fault 15;
4.
AF address decoder faults faults 9-14.
Possible causes of faults in ROMs.
Constant faults:
1.
Connection faults;
2.
Broken components;
3.
Faults in manufacturing;
4.
Faults in design.
Unstable faults:
1.
Environment (temp. humidity, pressure ...);
2.
Vibration;
3. Feed;
4.
Electromagnetic field, static electricity, ground;
5.
Bad connections;
6.
Timing;
7.
Changes in resistance and capacity,
8.
Noise;
9.
Ageing.
Mask-programmed ROM
0
A0
DC
A3
1
2
3
1
1
b1
b2
Programmable ROM
+v
+v
Fuse
A0
0
1
0
1
1
1
2
1
1
3
1
1
0
DC
A3
0
b1
0
b2
1
Programming of EPROM
The only fuse that falls under the
voltage of 2U resulting in its melting
.
+v
+v
tension 0
A0
0
1
0
tension U1
1
1
1
tension U1
2
1
1
3
1
1
0
DC
A3
tension U1
0
b1
tension 2U1
b2
tension 0
EPROM- Erasable PROM
Gate
Vgg
Silicon fixed gate
Vss
Vdd
Silicon floating gate
Source
n
Drain
n
p
EPROM array
WLi
Wli+1
0
Vdd
Vdd
Vdd
Vdd
BLi
0
Bli+1
Functional model of ROM
Address
Column address
decoder
Line address
decoder
Address register
Refresh Logic
Transition
logic
Memory array
Transition
amplifiers
Simplified model
Data register
Data
output
Data
input
Address
Address decoder
Memory array
Transition logic
Data
Chip Select
Behavioral test
Functioning
ROM
Address generator
(Counter)
Testified
ROM
Comparison
scheme
Functioning/
Nonfunctioning
Presupposes the existance of a functioning (golden) object (ROM).
Functional Testing
Parity check
All words must have even/odd number on 1-s.
0110 0
0001 1
1110 1
Parity
bits
Detecting faults:
1. Cell stuck – depends on data (If there is a fault
at cell 0 and 0 is being programmed to the slot,
it does not detect. Detects usually odd number
in s-a-1/0 faults in words..
2. Data line stuck –depends on data.
3. Address decoder fault – does not detect
It is not necessary to know how memory has been programmed
(content of the memory).
Check sum.
Memory ends with the sum of all memory words
The number of memory words necessary for preserving the sum
depends on the memory capacity
Preserving part of the sum (newer/older) some information is lost.
Detecting faults:
1. Cell stuck – depends on data (If there is a fault at cell 0 and 0 is
being programmed to the slot, it does not detect). Does not detect
anything if all words in the memory are 0-s. Bits that have changed
in different directions (faulty) mask in different words.
2. Data line stuck – depends on data (if some data line is s-a-0/1 and in
all words the value of the respective bit is also 0/1, does not detect;
otherwise detects).
3. Address decoder fault –detects if the values of all words are not
similar or are not similar at least the wrongly chosen words are not
similar.
It is necessary to know a only where the check sum is
preserved. It is not necessary to know the content of
the memory.