Transcript No Slide Title

STEREO/SECCHI Consortium Meeting
CCD Camera
July 2001
1
Dr N R Waltham
Space Science and Technology Department
Rutherford Appleton Laboratory
Key Players:
RAL
James King
Andy Marshall
Bill Duell
(prototyping/Development)
Lawrence Jones
Duncan Drummond
Jim Lang
Birmingham
Chris Eyles
David Hoyland
Mark Cooke
Clive Longstaff
Helen Mapson-Maynard
Camera electronics (analogue)
Camera electronics (digital)
Camera electronics
CDS/ADC ASIC Design (RAL Inst. Dept)
Camera test software
RAL Management
UK Management / HI
Camera Interface electronics
EGSE Software
CEB enclosure design
Thermal
CCD Detector
2
Marconi Applied Technologies (EEV) CCD42-40
Standard Package
•
2048 x 2048 pixel full-frame imager.
•
13.5 m pixel size.
•
Full Well:
•
Back illuminated: Peak QE ~ 90% @ 500 nm.
•
Dark current: 1 nAcm2s at 20 C (11,000 e-/pixel/s).
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Low noise output amplifiers: 6 e- rms at 1 MHz.
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Number of outputs: 2
•
Output node capacity:
100 k e- (min), 150k e- (typ.) (not MPP).
OG2 low 200 keOG2 high 1000 ke-
•
Gated dump drain on output register.
‘the chip that Dan ‘acquired’ for
free !
CCD42-40 Image
‘the chip that Dan ‘acquired’ for free !
3
CCD Detector – Package Development
4
Solar-B Package
10cm flexi connection to 25-way Micro-D
connector
CCD Detector
5
CCD Operation
Readout rate:
1 Mpixels/s through one output port (possibly two - TBC).
Number of output ports:
Both ports available, and connected to a dual channel CDS/ADC.
Readout noise:
< 7 e- rms.
CCD Clear:
via gated dump drain.
Dark current:
1 nAcm2s
Dither clocking:
at -40 C
at -60 C
1.2
at -80 C
0.04
to reduce dark current - up to x 100 reduction depending on dither
rate and temperature.
Optional (recommend no more than four windows. Baseline is no
more than two windows).
Windowing:
Pixel Binning:
at 20 C
11,000 e-/pixel/s.
20.7
Optional (recommend no more than 2 x 2 pixel binning).
CCD Lab Test System
2-stage Peltier cooling - achieves ~ -30C
6
CCD Lab Test System
7
SECCHI CCD Camera
Design Requirements and Philosophy
8
Requirements and Design Philosophy as developed during
Phase-A
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Control of up to three CCDs from one electronics box.
One camera box for SCIP, and another for HI.
Each CCD to have its own dedicated programmable waveform generator
and sequencer ASIC (as employed in the SMEI CCD cameras).
1 Mpixel/s readout rate through either of two CCD output ports, each port
employing a purpose-designed, low power CDS/ADC video processor
ASIC.
Dual readout through both ports at 1Mpixel/s may be possible (TBC).
14 bit digitisation - programmable video offset, and video gain.
Interface to the SECCHI computer via the SpaceWire adaptation of
IEEE1355.
PCB fabrication using SMT technology, ASICs, and FPGAs for glue logic.
Camera enclosure to be as small and light weight as possible.
SECCHI CCD Camera System
9
SECCHI CCD Camera Architecture
10
SECCHI CCD Camera
Key Developments Required
11
• Design of a single-chip CDS/ADC video processing ASIC.
•
•
•
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Readout with 14 bit precision at 1Mpixels/s.
Programmable video gain and video DC offset level.
Radiation tolerant, low power design in 0.35um CMOS.
COTS CDS/ADC video processing ASIC as a back-up.
• SpaceWire Camera Interface.
• Interface to the SECCHI computer via the SpaceWire
adaptation of IEEE1355.
• EGSE systems to employ a commercial SpaceWire PC-card.
SECCHI CCD Camera Target Resource
Requirements as developed for Phase A
12
•
Volume (SCIP):
 195mm x 126mm x 85mm (assumes 160 x 100mm eurcocards),
including mounting feet, connector, and fixing screw protrusions.
•
Volume (HI):
 195mm x 126mm x 70mm.
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Mass:
1.7kgs for SCIP camera unit, and 1.55kgs for HI
(including 15% reserve).
•
Power:
9 W for the SCIP camera electronics, and,
7 W for HI (including 15% reserve).
•
Power Connector:
9-way MDM Micro-D connector.
•
TC/TM Hardware standard:
SpaceWire adaptation of IEEE1355,
employing LVDS data transmission.
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TC/TM Data rate:
TC/TM connector:
CCD Connector:
Synchronisation:
Up to 100Mbits/s (TBC).
9-way MDM Micro-D connector.
31-way MDM Micro-D connector.
DC-DC converter synchronised to n x 50kHz - baseline 250kHz.
SECCHI CCD Camera
Current Estimated Resource
Requirements 13
 195mm x 126mm x 85mm (assumes 160 x 100mm eurcocards),
including mounting feet, connector, and fixing screw protrusions.
 195mm x 126mm x 70mm.
•
Volume (SCIP):
•
Volume (HI):
•
Mass:
1.88kgs for SCIP camera unit, and 1.6kgs for HI
(including 5% reserve).
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Power: (inc. 15% reserve).
•
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Power Connector:
TC/TM Hardware standard:
SCIP
10.6 W standby,
13.0 W readout.
HI
7.9 W standby,
10.0 W readout.
9-way MDM Micro-D connector.
SpaceWire adaptation of IEEE1355,
employing LVDS data transmission.
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•
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TC/TM Data rate:
TC/TM connector:
CCD Connector:
Synchronisation:
Up to 100Mbits/s (TBC).
9-way MDM Micro-D connector.
31-way MDM Micro-D connector.
DC-DC converter synchronised to n x 50kHz - baseline 250kHz.
SECCHI CCD Camera
Power Budget Drivers
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Serial Register Clock Drivers.
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HS-OP470 is radiation hard, low noise, but requires 2.5mA per amplifier. (~90mW per bias amplifier
from 35V).
SMEI used the OP-490 (which is much lower power, but radiation soft).
SpaceWire SMCSLite chip.
•
•
Each CCD output port requires a 2.5 to 5.0 mA load which at 30V supply equates to 75 to 150mW.
The recommendation is to add FET buffers to improve cable driving capability (at 1Mpixels/s over
40cms of cable). One FET on its own does not increase the loading. However . . .
The recommendation is to add differential FET buffers (i.e. two FETs per CCD output port) to allow a
differential input to the camera, and hence improved noise rejection characteristics.
In this case, each CCD, with two output ports, presents a load of 600mW (at 5mA current).
Use of radiation tolerant op-amps (Intersil HS-OP470) for CCD bias voltage generation.
•
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CCD presents a high capacitance load driving at 1Mpixels/s during CCD readout.
In addition, 1nF load capacitors are added to each CCD clock phase to improve clock ‘shape’ by
minimising the crosstalk from the CCD’s inter-phase capacitance.
Power demand during CCD readout ~ 600mW from a 10V supply, or 900mW from the camera’s 15V
supply.
FET Buffers at Focal Plane Assembly.
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14
Consumes 300mW (standby), and ~ 450mW during CCD readout.
Also need to account for DC-DC converter losses, and charge pump losses for the CCD bias.
SECCHI CCD Camera
CCD Driver Card
15
Design Features.
•
Programmable Waveform Generator and Sequencer ASIC clocked at 20
MHz (existing qualified RAL design).
•
All CCD Clock drivers and bias voltage generators to allow dual-split
readout through two output ports.
•
Dual CDS/ADC video processor channels (14 bits precision at 1
Mpixels/s readout).
•
CDS/ADC video processor to be implemented in custom radiation
tolerant design.
•
CCD Bias voltage circuitry (updated version of SMEI design).
•
Latch-up protection where necessary.
SECCHI CCD Camera Architecture
CCD Driver Card - Flight Model
BACKPLANE
I2C
20 MHz CLOCK
2
I2C
I2C
20MHz
CLK
TABLE-ACTIVE
WGA
CCD WAVEFORM
GENERATOR
ASIC
IO, DG
4
HO, OR
CONFIG
31-WAY
MICRO-D
BIPOLAR
HO
CLOCK RATE
4
IO, DG
4
4
CDS CLKS
TABLE-ACTIVE
END OF FRAME
HS-4424
IO, DG
16
HO
5
BIPOLAR
SW
RESET
SW
2
VIDEO DATA
8
ADC
DATA
BUFFERS
AD9814 AND MODE CONTROL VIA WGA
EXTERNAL MEMORY BUS OR I2C?
MODE AND GATING CONTROL
54SX ACTEL FPGA
ADC DATA INPUTS
BIPOLAR
OR
EN
OG2
OR
OG2
CDS/
ADC PROG
Vref
CURRENT
TRIP
5V
HS-OP470
5V (T)
OD, RD, SS,
DD, OG1
5
5V
3.3V VOLTAGE
REGULATOR
CURRENT
TRIP
3.3V (T)
OS(L)
5V
2.5V VOLTAGE
REGULATOR
CURRENT
TRIP
8
RAL
CDS/ADC
ASIC
8
RAL
CDS/ADC
ASIC
2.5V (T)
35V
CURRENT
TRIP
35V (T)
15V
CURRENT
TRIP
15V (T)
DOS(L)
OS(R)
15V
15V
IMAGE CLOCKS
VOLTAGE
REGULATOR
IO. DG
DRIVER
SUPPLIES
OUTPUT REGISTER
CLOCKS VOLTAGE
REGULATOR
CURRENT
TRIP
DOS(R)
C L R C R u th e r fo r d Ap p le to n L a b o r a to r y
Pr o je c t:
So la r Te r r e s tr ia l R e la tio n s O b s e r v a to r y ( STER EO )
In s tr u me n t:Su n Ea r th C o n n e c tio n C o r o n a l H e lio s p h e r ic Ima g e r ( SEC C H I)
HO. SW. OR
DRIVER
SUPPLIES
Su b s y s te m:
C a me r a C o n tr o lle r / Blo c k D ia g r a ms
Sc h e ma tic Title :C C D D r iv e r C a r d
R AL D o c u me n t N u mb e r :3 - KE- 0 1 4 8 - 0 1 0 - 0 1 - 2
R e v .: 1 .0
D r a w n By : J .M. Kin g / N .R . W a lth a m
C h e c k e d By :<C h e c k e d :>
R e le a s e d By :<R e le a s e d :>
Sh e e t Siz e : A3
D a te : Su n d a y , J u ly 0 8 , 2 0 0 1
D a te : <C h e c k e d D a te >
D a te : <R e le a s e D a te >
Sh e e t: 1
of 2
Programmable Waveform Generator
and Sequencer ASIC
• Fabrication on Rad Hard
TEMIC DMILL process.
• Now qualified in SMEI
and ROSETTA Flight
models.
17
SECCHI CCD Camera System
CDS/ADC Video Processor ASIC
18
Requirements.
•
14 bit correlated double sampling (CDS) and digitisation.
•
Readout rate of 1Mpixel/s.
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Programmable video gain and video DC offset level.
•
Ideally, a differential input amplifier to maximise noise rejection between the
FPAs and Camera electronics (very successfully demonstrated on SMEI).
•
Radiation tolerant, low power, compact solution.
RAL CDS/ADC Video Processing ASIC
19
SECCHI CCD Camera System
CDS/ADC Video Processor ASIC
20
Progress:
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Design in ASIC Design Group within RAL Instrumentation Department.
Block diagram and architectural design completed.
Selection of AMS 0.35um CMOS process for fabrication.
Extensive modelling of ADC architectures, and performance – optimised for low DNL.
Extensive modelling of op-amp amplifiers, transistor noise levels, and necessary
operating currents.
Detailed design of CDS amplifier completed – modelling predicts 15 bit performance at
1Mpixels/s.
Submission of prototype CDS chips (6th June 2001).
Detailed design of DACs (for video gain/offset adjust) and I2C interface complete.
Detailed design of ADC currently on-going.
Submission of final design – target date: 15th August 2001.
Packages already procured for prototype chips.
But what about the COTS back-up solution ?
Burr Brown CDS/ADC
Burr Brown VSP3100 CDS/ADC ASIC Evaluation
21
COTS CDS/ADC ASIC Evaluation
Burr Brown and Analog Devices
CDS/ADC ASIC Evaluation
•
•
•
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Purchased Burr Brown Evaluation cards, and
made an equivalent PCB for the Analog
Devices part.
Designed a prototyping card adapter to allow
an evaluation card to be inserted into our
SMEI CCD camera (next slide).
An ACTEL FPGA provides serial
programming of the CDS/ADC internal
registers.
EGSE limitations restrict to operation at
100Kpixels/s readout.
Burr Brown PCB
Analog Devices AD9814 PCB
22
COTS CDS/ADC ASIC Evaluation
23
CDS/ADC ASIC Evaluation System
Employs a new prototyping card plugged into the SMEI CCD camera
system
COTS CDS/ADC ASIC Evaluation
SMEI CCD in SMEI Camera System
24
COTS CDS/ADC ASIC Evaluation
25
Burr Brown VSP3100 CDS/ADC ASIC Evaluation - Linearity
VSP3100 with SMEI CCD - Linearity
16000.0
14000.0
Mean Signal - DC underscan (adu)
12000.0
10000.0
8000.0
6000.0
4000.0
2000.0
0.0
0
500
1000
1500
2000
2500
Exposure time (ms)
3000
3500
4000
4500
5000
COTS CDS/ADC ASIC Evaluation
26
Results of AD9814, AD9826 and VSP31000 Evaluation.
Do they work ?
Yes.
Are they linear ?
Yes.
Do the video offsets work ?
Yes.
Do the programmable gains work ?
Yes
Readout noise (i/ps connected to 0V, 0dB gain):
Burr Brown VSP3100 (14 bit)
Analog Devices AD9814 (14 bit)
Analog Devices AD9826 (16 bit)
Radiation testing:
Burr Brown VSP3100
Analog Devices AD9814
2.2 adu rms (2V i/p range)
1.7 adu rms (3V i/p range)
0.75 adu rms (4V i/p range)
3.6 adu rms (4V i/p range)
Spec = 0.5
Spec = 0.55
Spec = 0.75
18Krads (RAL DCIXS programme)
TBC at Birmingham in next few weeks.
SECCHI CCD Camera
Camera Interface Card
27
Design Features.
•
Command, status, and video data to be transmitted over a SpaceWire link.
•
Communication via SpaceWire implementation of IEEE1355 standard.
•
Video readout rate of 1Mpixel/s dictates a link of greater than 20Mbits/s.
•
Dual-split readout (i.e. two ports running together) dictates a link of greater
than 40Mbits/s.
•
LVDS data signals.
•
FIFO required within the camera to buffer video data prior to transmission –
FIFO size depends on receive-end design topology, operation, and PCI-bus
activity in the case of the EGSE.
•
Housekeeping telemetry of secondary voltage rails and internal temperature.
SECCHI CCD Camera Architecture
Camera Interface Card
28
BACKPLANE
VIDEO DATA
VIDEO DATA
8
54SX ACTEL
FPGA GLUE
LOGIC
9-WAY
MICRO-D
VIDEO DATA
8
4Kx9 FIFO
8
RESET
/EMPTY
FIFO WRITE
/WRITE
/READ
END_OF_FRAME
EMPTY
FIFO READ
IEEE1355
SPACEWIRE
LINK
ENGINE
LVDS
VIDEO
DATA LINK
END OF PACKET
SPACEWIRE CLOCK
IEEE 1355 RESET
9-WAY
MICRO-D
I2C
I2C / UART / ?
2
CAMERA
COMMAND/STATUS
LINK
LVDS
MASTER
CLOCK
OSCILLATOR
20MHz CLOCK
PCU CLOCK
POWER
ON
RESET
RESET
Secondary Power Rails
CEB Temperature
HK ADC
MUX
C L R C R u th e r fo r d Ap p le to n L a b o r a to r y
Pr o je c t:
So la r Te r r e s tr ia l R e la tio n s O b s e r v a to r y ( STER EO )
In s tr u me n t:Su n Ea r th C o n n e c tio n C o r o n a l H e lio s p h e r ic Ima g e r ( SEC C H I)
Su b s y s te m:
C a me r a C o n tr o lle r / Blo c k D ia g r a ms
Sc h e ma tic Title :In te r fa c e C a r d
R AL D o c u me n t N u mb e r :3 - KE- 0 1 4 8 - 0 2 0 - 0 0 - 1
R e v .: 1
D r a w n By : J .M.Kin g
C h e c k e d By :<C h e c k e d :>
R e le a s e d By :<R e le a s e d :>
Sh e e t Siz e : A3
D a te : Su n d a y , J u ly 0 8 , 2 0 0 1
D a te : <C h e c k e d D a te >
D a te : <R e le a s e D a te >
Sh e e t: 1
of 1
SECCHI CCD Camera Architecture
Camera Interface Card
29
Design Philosophy and Progress.
•
Original concept was to use an SMCSLite ASIC developed by the same team
that developed the SMCS332 (Astrium).
•
However, we were unable to get a reliable date for availability.
•
We therefore decided to design our own chip in an ACTEL FPGA (David
Hoyland at Birmingham). Good progress has been made, but the design is
yet to be fully completed.
•
We have an urgent need to establish the overall feasibility of using
SpaceWire (particularly with the EGSE SpaceWire card).
•
SMCSLite has recently become available - Presents us with a fully validated
design !
•
Decision made to build a test system to prove the feasibility of SpaceWire
within the camera system using an SMCSLite chip.
•
Meeting held with NRL two weeks ago to discuss all the issues. Conclusion
was that an early test with the EGSE was essential.
SECCHI CCD Camera
EGSE Hardware
EGSE Hardware
•
PC-based system fitted with a
4Links (UK) SpaceWire PCI card.
•
4Links card employs the SMCS332
SpaceWire ASIC developed for ESA.
30
SMCSLite SpaceWire Chip
31
SMCSLite SpaceWire Chip
32
http://www.estec.esa.nl/microelectronics/presentation/#SMCSLite
Radiation Hard Data Handling Technology: SMCSLite and DS-Link Macrocell Development
(SMCSLite/SMCS116/T7906E)
Final Presentation of Contract 11444/95/NL/FM - Call Off Order #8
Anja Christen, Paul Rastetter, Tim Pike, ASTRIUM - Friedrichshafen/Ottobrunn, Germany The
SMCSLite 1355 chip provides an interface between the serial IEEE-1355 link and a highly
configurable parallel data bus. Additional features of this device are on-chip facilities like timers,
FIFO control, ADC/DAC interfaces, UARTs etc. The device can be completely remotely controlled via
the IEEE-1355 link without the need for a local microcontroller, FPGA or similar. The SMCSLite was
developed at ASTRIUM GmbH in Munich-Ottobrunn during 1998 with partial funding under a CEC
(DIPSAP-II) contract and has been implemented in a MH1RT gate array from ATMEL W&M. The
presentation will cover the features of the SMCSLite, its recent validation at ASTRIUM in Ottobrunn
and the production of a DS-link macrocell as a stand-alone element. The test board used to validate
the SMCSLite functionality will be described.
SMCSLite Test Setup
PC
33
100Mbit/s Spacewire Data
SMCSLite
Test Card
4 Links
Test Pattern Data
WGA Pattern
Card
PC
SMEI System
I2C WGA programming
SMCSLite SpaceWire ASIC Evaluation
Card
and Test Pattern Generator
34
SMCSLite SpaceWire ASIC Evaluation Card
Progress
•
•
•
4Links card now talks to SMCSLite internal
registers.
FIFO interface and EOP insertion works !
Next step is to prove video data link
bandwidth.
Test Pattern Generator
SECCHI CCD Camera
DC-DC Power Converter Unit
Camera Power Requirements.
•
•
•
•
•
•
•
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+28V Primary Input.
In-rush current limiting.
Synchronisable DC-DC switching frequency (n x 50 KHz).
+5V for logic.
+15V for CCD Clock Driver supplies.
+35V for CCD biasing.
Secondary side filtering of all power.
3.3V and 2.5V rails to be derived from +5V.
• Radiation hard or tolerant.
• Single, double or tripple?
• Availability & heritage.
35
SECCHI CCD Camera Architecture
DC-DC Power Converter Unit
36
BACKPLANE
9-WAY
MICRO-D
+5V
+5V
+5V (UF)
+15V
+15V
+15V (UF)
+28V
EMC
FILTER
+28V_RTN
+35V
0V
CHARGE
PUMP
+30V
OUTPUT
FILTERING
0V
+30V (UF)
+28V
IN-RUSH
CURRENT
LIMITER
+28V_RTN
DC-DC
CONVERTER
0V (UF)
SYNC
PCU CLOCK
CLOCK SYNC
(n X 50KHz)
C L R C R u th e r fo r d Ap p le to n L a b o r a to r y
Pr o je c t:
So la r Te r r e s tr ia l R e la tio n s O b s e r v a to r y ( STER EO )
In s tr u me n t:Su n Ea r th C o n n e c tio n C o r o n a l H e lio s p h e r ic Ima g e r ( SEC C H I)
Su b s y s te m:
C a me r a C o n tr o lle r / Blo c k D ia g r a ms
Sc h e ma tic Title :D C - D C Po w e r C o n v e r te r
R AL D o c u me n t N u mb e r :3 - KE- 0 1 4 8 - 0 3 0 - 0 0 - 1
R e v .: 1
D r a w n By : J .M.Kin g
C h e c k e d By :<C h e c k e d :>
R e le a s e d By :<R e le a s e d :>
Sh e e t Siz e : A3
D a te : Su n d a y , J u ly 0 8 , 2 0 0 1
D a te : <C h e c k e d D a te >
D a te : <R e le a s e D a te >
Sh e e t: 1
of 1
SECCHI CCD Camera
DC-DC Power Converter Unit
Procurement Options
•
Lambda Advanced Analog (ART2815T preferred)
•
Mag-3 : now part of Lambda Advanced Analog
•
Interpoint (not if can be avoided ! squealing, optical
feedback…)
•
Others ?
37