Transcript Document

Gate Sizing Based on Lagrangian
Relaxation
Yu-Min Lee
Advisor: Charlie Chung-Ping Chen
UW-Madison
Functionality
• Gate characterization
– Propagation delay
– Gate capacitance
• Posynomial curve fitting
• Lagrangian relaxation(LR) sizer
– Automatic gate sizing
– Optimality guarantee for convex programming
problem
UW-Madison
LR Sizer Structure
Gate Lib/
HSPICE
Gate
Characterization
Curve Fitting
LR Sizer
UW-Madison
ISCAS Format
Circuit
Gate Characterization
• Use HSPICE simulator to characterize the delay of each
gate, NOT, NAND, NOR, … with different sizes and load
capacitance
• Use HSPICE simulator to characterize the equivalent input
capacitance of each gate, NOT, NAND, NOR, … with
different sizes and load capacitance
UW-Madison
Curve Fitting: Posynomial
• Use least-square fitting to find the best posynomial curve for
propagation delay, and equivalent capacitance of each gate
0.5
t prop  a0  a1 Cl / wg  a2 Cl / wg  
Cl : load capacit ance

wg : gat e size
ai : posit ivenumber
Error Distribution
30
Distribution (%)
25
20
15
10
5
UW-Madison
0
-15
-12
-8.5 -5.1 -1.7
1.7
Error (%)
5.1
8.5 11.9 15.3
Lagrangian Relaxation
Minimize f ( x )
subject to g i ( x )  0, i  1..m
n 1
Minimize f ( x )   i g i ( x )
i 1
subject to g i ( x )  0, i  n..m
• LRS (Lagrangian Relaxation Subproblem)
• The optimal solution for any LRS is a lower bound of
the original problem for any type of problem
• There exists Lagrangian multipliers will lead LRS to
find the optimal solution for convex programming
problem
UW-Madison