Transcript Testing and Design for Test

Soft Error Modeling and Mitigation
Mehdi B. Tahoori
Northeastern University
[email protected]
Copyright 2005, M. Tahoori
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Outline



Soft Error Introduction
Soft Error Modeling for Memory Hierarchy
Soft Error Modeling in Random Logic



Combinational logic
Sequential logic
More Issues
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Soft Error: Introduction
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Evidence of Cosmic Ray Strikes

Documented strikes in large servers found in error logs


Normand, “Single Event Upset at Ground Level,” IEEE Transactions
on Nuclear Science, Vol. 43, No. 6, December 1996.
Sun Microsystems, 2000 (R. Baumann, 2002 IRPS Workshop
talk)


Cosmic ray strikes on L2 cache with defective error protection
 caused Sun’s flagship servers to suddenly and mysteriously crash!
Companies affected
 Baby Bell (Atlanta), America Online, Ebay, & dozens of other
corporations
 Verisign moved to IBM Unix servers (for the most part)
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Reactions from Companies

Fujitsu SPARC in 130 nm technology
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
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80% of 200k latches protected with parity
compare with very few latches protected in Mckinley
ISSCC, 2003
IBM declared 1000 years system MTBF as product
goal
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

for Power4 line
very hard to achieve this goal in a cost-effective way
Bossen, 2002 IRPS Workshop Talk
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Impact of Neutron Strike on a Si Device
Figure 3, Ziegler, et al., “IBM
experiments in soft fails in
computer electronics (1978 1994),” IBM J. of R. & D., Vol.
40, No. 1, Jan. 1996.

Strike creates electron-hole pairs that can be absorbed by
source/diffusion areas to change state of device
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Impact of Elevation
Figure 8, Ziegler, et al., “IBM
experiments in soft fails in
computer electronics (1978
- 1994),” IBM J. of R. & D.,
Vol. 40, No. 1, Jan. 1996.


3x - 5x increase in Denver at 5,000 feet
100x increase in airplanes at 30,000+ feet
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Physical Solutions are hard

Shielding?
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Technology solution: SOI?

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Partially-depleted SOI probably no help in 250 nm and beyond
Fully-depleted SOI can help, but very hard to manufacture in high
volumes
Radiation-hardened cells?



No practical absorbent (e.g., approximately > 10 ft of concrete)
unlike Alpha particles
10x improvement possible with significant penalty in performance,
area, cost
2-4x improvement may be possible with less penalty
Some of these techniques will help alleviate the impact of
Soft Errors, but not completely remove it
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Strike on state bit (e.g., in register file)
Bit
Read
no
yes
Bit has
error
protection
yes
benign fault
no error
no
yes
Error
is only detected
(e.g., parity +
no recovery)
Detected, but
unrecoverable
error (DUE)
Copyright 2005, M. Tahoori
Error can be
corrected
(e.g, ECC)
no error
Does bit
matter?
yes
Silent Data
Corruption
(SDC)
no
benign fault
no error
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Definitions

Interval-based



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
MTTF = Mean Time to Failure
MTTR = Mean Time to Repair
MTBF = Mean Time Between Failures = MTTF + MTTR
Availability = MTTF / MTBF
Rate-based



FIT = Failure in Time = 1 failure in a billion hours
1 year MTTF = 109 / (24 * 365) FIT = 114,155 FIT
SER FIT = SDC FIT + DUE FIT
Hypothetical Example
Cache: 40K FIT
+ IQ: 100K FIT
+ FU: 58K FIT
Copyright 2005, M. Tahoori
Total of 198K FIT
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# Vulnerable Bits Growing with Moore’s Law
SDC FIT from Vulnerable
Latches
10000
12x GAP
1000
100
10
100% Vulnerable
20% Vulnerable
2012
2011
2010
2009
2008
2007
2006
2005
2004
2003
1
IBM 1000 year MTBF
Goal
Year
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

Fujitsu SPARC has 20% of 200k latches vulnerable in 2003
Additional SDC FIT from RAM cells, static logic, & dynamic logic
Higher SDC FIT in multiprocessor systems


Gap ~= 100x for 8 processor system!
A data center with 300 such systems will encounter a data corruption
almost every week
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Soft Error Issues
1.
Why is soft error a problem today?


2.
What about system FIT contribution?


3.
System FIT decreased dramatically (e.g., RAID, ECC on DRAM)
Large part of system moving on-chip (e.g., memory controller)
Is this a server problem or a desktop problem?


4.
Industry is at the cross-over point
Future is worse, IF we don’t do anything
Definitely a server (e.g., data center) problem
Desktop problem from IT manager’s point of view
How do software bugs compare to soft error rates?


Limited # of bugs in mature software (e.g., servers, company
environment)
If we don’t do anything, soft errors will be your dominant failure
rate
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Balancing Reliability and Performance in
Memory Hierarchy
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Goals

Accurately estimate reliability in cache memory



early in the design cycle
Methods to increase reliability of cache memory
Minimize power / performance impacts
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Motivation

Memory elements


most vulnerable components to soft errors (Gaisler 97)
Previous method: Fault Injection (Faure 03)
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Software (during design cycle)


time-consuming
Radiation-based

only after chip fab
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Cache Reliability Model
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Separately measures reliability of:

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
Data array
Tag array
Status bits



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Valid bit
Dirty bit
Can be extended to other status bits (coherency, etc)
Model provides an upper bound

on error rate for a given workload
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Errors in Data RAM

Critical Words (CW)


Read by CPU or written to memory
Critical Time (CT)
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Reliability Computation (I)

Vulnerability factor

Fraction of faults that become errors
VFcache
residencytim e of

=
all critical words
Total ExecutionTim e M
N
 CT
i
VFcache =



i=1
TT  M
M: Cache size
TT: Total execution time
CT: Critical time
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Reliability Computation (II)

Define vulnerability as follows:
N
raw FIT   CTi
FITcache =
i=1
TT
FITcache
Vulnerabilitycache =
raw FIT per bit


Independent of environment and cache size
Goal


decrease vulnerability
while not impacting power and performance
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Experimental Setup



SimpleScalar 4.0
SPEC2000 benchmarks
Programs run for 500M instructions
Parameter
Value
LSQ size
8 instructions
RUU size
16 instructions
Fetch Width
4 instr/cycle
Parameter
L1 I-Cache
Value
16KB, 1-way, 32-byte line
1 cycle latency
Issue Width
4 instr/cycle
L1 D-Cache 16KB, 4-way, 32-byte line
Writeback, alloc-on-write-miss
1 cycle latency
Commit
Width
Fetch Queue
4 instr/cycle
L2 Cache
256KB, 4-way, 64-byte line
6 cycle latency, unified
Cycle Time
1 ns
Memory
100 cycle latency
Decode Width 4 instr/cycle
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4 instructions
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Experiments

Examined three methods to reduce vulnerability
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Flushing
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Write Policy
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periodically flush entire cache
change write-thru policy (from write-back)
Refreshing

periodically refetch cache blocks from L2 cache
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D-Cache: Flushing
Copyright 2005, M. Tahoori
4x reduction
in
vulnerability
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D-Cache: Write Policy
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10x reduction
in
vulnerability
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D-Cache: Refresh
Copyright 2005, M. Tahoori
3x reduction
in vulnerability
using write-thru
(30x total)
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Summary
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Reliability estimation of cache hierarchy

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Several methods to reduce vulnerability
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

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Based on critical words and critical times
Flushing
Write-thru policy
Refreshing
30x decrease in vulnerability

with minimal IPC impact
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Soft Error Modeling at Logic-Level
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Exponential increase of Soft Errors
1.00000
0.90000
0.80000
0.70000
0.60000
0.50000
0.40000
0.30000
0.20000
0.10000
0.00000
SRAM: exp(-Qcrit/Qs)
Latch: exp(-Qcrit/Qs)
600 350 250 180 130 100
nm nm nm nm nm nm

50
nm
e-Qcrit/Qs trend with technology scaling (Shivakumar , DSN 2002)



70
nm
Qcrit: the critical charge (depend on characteristics of the circuit)
Qs: the charge collection efficiency of a particle strike on the device
Particles of lower energies occur far frequently than particles of higher
energy
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Soft Error Rate


Error rate of node n
Nominal FIT  Logic Derating  Timing Derating

Norminal FIT


Logic Derating


Occurrence rate of SEUs at node n causing a glitch
Propagation of error from node n to system bistables or
outputs
Timing Derating

Propagated transient captured in system bistables
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Combinational Logic (Logic Derating)
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SER Estimation in Combinational Logic

The main idea:


Traversing structural paths from faults origin to POs
Using signal probabilities for SER estimation
Off-Path Signals
SEU
FF
On-Path Gates
PO
On-Path Signals
FF
Off-Path Signals
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Example: Simple Path
off-path signals
SPA=0.2
A
SPB=0.3
B
PO
PI=a
C
D
On-Path Signals


EPP(gate C) = 10.2=0.2
EPP(gate D) = 0.2(1-SPB)= 0.20.7=0.14
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Propagation Rules

Need 4 logic values

0, 1 : no propagation
a, ā : propagation (same and opposite polarities)
Pa(Ui ) + Pā(Ui ) + P1(Ui ) + P0(Ui ) = 1


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Algorithm

For any gate, gi:
1. Extract all on-path signals (and gates) from gi

to any reachable primary output POj and/or flip-flop ffj
2. Levelize signals on these paths
3. Traverse the paths in order


Use signal probabilities for off-path signals
Use propagation rules for on-path signals
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Example: Reconvergent Fanouts
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Sequential Logic (Timing Derating)
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Glitch Propagation: Simple Path

Duration and time of propagated glitch


Glitch propagation probabilitiy


Depends on propagation and transition delays along the path
Depends on signal probabilities of off-path signals
Error propagation probability (EPP)

Propagation probability (PP)  Latching Probability (LP)
off-path signals
SPB=0.2
B
SEU
A
Copyright 2005, M. Tahoori
SPC=0.4
C
w'
w
t
D
E
t'
FF
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Latching Probability

LP = (S+H+W)/T



S,H : Setup and Hold time
W: glitch width
T : clock period
overlap window = W + S + H
H
S
W
W
T
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Reconvergent Paths

Propagated waveforms

Multiple waveforms, not simple glitches

(inverted)
SEU
1
FF
2
2
Copyright 2005, M. Tahoori
(inverted)
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Approach

Find all possible propagated waveforms

Enhanced static timing analysis

All possible transitions at each reachable gate


Find the probability of each waveform



Due to glitch at error site
Using an approach similar to logic derating
Compute time-logic derating at each node
Compute overall SER
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Example
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Validation

Monte-Carlo simulation
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Inject glitches at the outputs of random gates

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Perform timing-accurate simulation



At random time
Identify if error captured in a flip-flop
Compute soft error rate
Stop

if the computed value reaches confidence interval


E.g. 3% error margin
Or, if simulation doesn’t converge after N iterations

Too time-consuming
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Results: Timing Derating
Run time(sec)
Circuit
s298
s344
s386
s400
s526
s1196
s1238
s1423
s1488
s35932
s38417
s38584
average
#Gates MC Sim Proposed
119
4751
0.26
160
2517
0.35
159
4187
0.15
164
4237
1.5
193
7848
1.6
529
3328
2.2
508
9174
3.3
657
17238
3.9
653
11562
4.8
16065
N/A
537
19253
N/A
671
22179
N/A
645
7204
155
Copyright 2005, M. Tahoori
Speedup
18272
7191
27913
2825
4905
1513
2780
4420
2409
8025
w=50ns
w=70ns
% Diff Sim Status % Diff Sim Status
0.47
C
5.03
NC
1.81
C
3.3
NC
0.91
C
0.51
C
2.45
NC
1.01
NC
2.59
NC
3.48
NC
0.45
C
1.47
C
1.49
C
0.92
C
1.11
C
2.25
C
1.12
C
1.29
C
NC
NC
NC
NC
NC
NC
1.37
2.14
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SER vs Glitch Width
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Summary

Analytical method for SER estimation at logic-level




Very fast and accurate




Logic and timing derating
Based on signal probabilities
Traversing topological paths in the netlist
Compared to Monte-Carlo Fault Injection
4-5 orders of magnitude faster
More than 96% accurate
Application


Reliability measurement
Cost-effective soft error hardening
Copyright 2005, M. Tahoori
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More Issues

Soft error hardening

For individual gate




Gate sizing
Using isolation device (c-pass transistors)
…
For entire design

Balancing reliability and overheads

Area, power, delay
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References





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
J. Kumar, M.B. Tahoori, “Use Of Pass Transistor Logic To Minimize The Impact Of
Soft Errors In Combinational Circuits”, In Workshop on System Effects of Logic
Soft Errors (SELSE), 2005.
G. Asadi, M.B. Tahoori, “An Analytical Approach for Soft Error Rate Estimation In
Digital Circuits”, In IEEE International Symposium on Circuits and Systems
(ISCAS), 2005.
G. Asadi, V. Sridharan, M. B. Tahoori, D. Kaeli, “Balancing Performance and
Reliability in the Memory Hierarchy”, In IEEE Boston Area Architecture (BARC)
Workshop, 2005.
G. Asadi, M.B. Tahoori, “Soft Error Mitigation for SRAM-based FPGAs”, In VLSI
Test Symposium (VTS), 2005.
G. Asadi, V. Sridharan, M. B. Tahoori, D. Kaeli, “Balancing Performance and
Reliability in the Memory Hierarchy”, In IEEE International Symposium on
Performance Analysis of Systems and Software (ISPASS), 2005.
G. Asadi, M.B. Tahoori, “An Accurate SER Estimation Method Based on
Propagation Probability”, In Design Automation and Test in Europe (DATE)
Conference, 2005.
G. Asadi, M.B. Tahoori, “Soft Error Rate Estimation and Mitigation for SRAMbased FPGAs”, In ACM International Conference on Field Programmable Gate
Arrays (FPGA), 2005.
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Questions?
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Origin of Cosmic Rays
Figure 2, Ziegler, et al.,
“IBM experiments in soft
fails in computer
electronics (1978 1994),” IBM J. of R. & D.,
Vol. 40, No. 1, Jan. 1996.

Cosmic rays come from deep space
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Computing FIT rate of a Chip

FIT Rate Law:


Vulnerable Bit Law:


FIT rate of a system is the sum of the FIT rates of its individual
components
FIT rate of a chip is the sum of the FIT rate of vulnerable bits in that
chip!
Total Soft Error FIT =



(for each vulnerable device i) (intrinsic error rate i  vulnerability factor i)
Vulnerability Factor = fraction of faults that become errors
Vulnerability Factor is also known as “derating factor” and “soft error
sensitivity (SES).”
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Issues: Output Dependency


Same error propagated to multiple outputs
Solution


forward signal probability of one PO to the other PO.
SP of POk forwarded to next stages

instead of EPP of POk,
Erroneous
value (a)
POj
POj Erroneous
A
POk
(a)
Copyright 2005, M. Tahoori
value (a)
A
POk
(b)
50